This is because the next patch introduces a three level hierarchy.
--HG--
rename : build_opts/ALPHA_MESI_CMP_directory => build_opts/ALPHA_MESI_Two_Level
rename : build_opts/X86_MESI_CMP_directory => build_opts/X86_MESI_Two_Level
rename : configs/ruby/MESI_CMP_directory.py => configs/ruby/MESI_Two_Level.py
rename : src/mem/protocol/MESI_CMP_directory-L1cache.sm => src/mem/protocol/MESI_Two_Level-L1cache.sm
rename : src/mem/protocol/MESI_CMP_directory-L2cache.sm => src/mem/protocol/MESI_Two_Level-L2cache.sm
rename : src/mem/protocol/MESI_CMP_directory-dir.sm => src/mem/protocol/MESI_Two_Level-dir.sm
rename : src/mem/protocol/MESI_CMP_directory-dma.sm => src/mem/protocol/MESI_Two_Level-dma.sm
rename : src/mem/protocol/MESI_CMP_directory-msg.sm => src/mem/protocol/MESI_Two_Level-msg.sm
rename : src/mem/protocol/MESI_CMP_directory.slicc => src/mem/protocol/MESI_Two_Level.slicc
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/system.pc.com_1.terminal
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
rename : tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/ruby.stats
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt
+++ /dev/null
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MESI_CMP_directory'
--- /dev/null
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MESI_Two_Level'
+++ /dev/null
-TARGET_ISA = 'x86'
-CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
-PROTOCOL = 'MESI_CMP_directory'
--- /dev/null
+TARGET_ISA = 'x86'
+CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
+PROTOCOL = 'MESI_Two_Level'
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import math
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from Ruby import create_topology
-
-#
-# Note: the L1 Cache latency is only used by the sequencer on fast path hits
-#
-class L1Cache(RubyCache):
- latency = 3
-
-#
-# Note: the L2 Cache latency is not currently used
-#
-class L2Cache(RubyCache):
- latency = 15
-
-def define_options(parser):
- return
-
-def create_system(options, system, piobus, dma_ports, ruby_system):
-
- if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
- panic("This script requires the MESI_CMP_directory protocol to be built.")
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes must be
- # listed before the directory nodes and directory nodes before dma nodes, etc.
- #
- l1_cntrl_nodes = []
- l2_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
- l2_bits = int(math.log(options.num_l2caches, 2))
- block_size_bits = int(math.log(options.cacheline_size, 2))
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- #
- l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc,
- start_index_bit = block_size_bits,
- is_icache = True)
- l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc,
- start_index_bit = block_size_bits,
- is_icache = False)
-
- prefetcher = RubyPrefetcher.Prefetcher()
-
- l1_cntrl = L1Cache_Controller(version = i,
- L1Icache = l1i_cache,
- L1Dcache = l1d_cache,
- l2_select_num_bits = l2_bits,
- send_evictions = (
- options.cpu_type == "detailed"),
- prefetcher = prefetcher,
- ruby_system = ruby_system,
- transitions_per_cycle=options.ports,
- enable_prefetch = False)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- ruby_system = ruby_system)
-
- l1_cntrl.sequencer = cpu_seq
-
- if piobus != None:
- cpu_seq.pio_port = piobus.slave
-
- exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
-
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- l2_index_start = block_size_bits + l2_bits
-
- for i in xrange(options.num_l2caches):
- #
- # First create the Ruby objects associated with this cpu
- #
- l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc,
- start_index_bit = l2_index_start)
-
- l2_cntrl = L2Cache_Controller(version = i,
- L2cache = l2_cache,
- transitions_per_cycle=options.ports,
- ruby_system = ruby_system)
-
- exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
- l2_cntrl_nodes.append(l2_cntrl)
-
- phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
- assert(phys_mem_size % options.num_dirs == 0)
- mem_module_size = phys_mem_size / options.num_dirs
-
- # Run each of the ruby memory controllers at a ratio of the frequency of
- # the ruby system
- # clk_divider value is a fix to pass regression.
- ruby_system.memctrl_clk_domain = DerivedClockDomain(
- clk_domain=ruby_system.clk_domain,
- clk_divider=3)
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(
- clk_domain = ruby_system.memctrl_clk_domain,
- version = i,
- ruby_system = ruby_system)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size,
- use_map =
- options.use_map),
- memBuffer = mem_cntrl,
- transitions_per_cycle = options.ports,
- ruby_system = ruby_system)
-
- exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_port in enumerate(dma_ports):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- ruby_system = ruby_system)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq,
- transitions_per_cycle = options.ports,
- ruby_system = ruby_system)
-
- exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
- exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
- dma_cntrl_nodes.append(dma_cntrl)
-
- all_cntrls = l1_cntrl_nodes + \
- l2_cntrl_nodes + \
- dir_cntrl_nodes + \
- dma_cntrl_nodes
-
- topology = create_topology(all_cntrls, options)
-
- return (cpu_sequencers, dir_cntrl_nodes, topology)
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from Ruby import create_topology
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+ latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+ latency = 15
+
+def define_options(parser):
+ return
+
+def create_system(options, system, piobus, dma_ports, ruby_system):
+
+ if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
+ fatal("This script requires the MESI_Two_Level protocol to be built.")
+
+ cpu_sequencers = []
+
+ #
+ # The ruby network creation expects the list of nodes in the system to be
+ # consistent with the NetDest list. Therefore the l1 controller nodes must be
+ # listed before the directory nodes and directory nodes before dma nodes, etc.
+ #
+ l1_cntrl_nodes = []
+ l2_cntrl_nodes = []
+ dir_cntrl_nodes = []
+ dma_cntrl_nodes = []
+
+ #
+ # Must create the individual controllers before the network to ensure the
+ # controller constructors are called before the network constructor
+ #
+ l2_bits = int(math.log(options.num_l2caches, 2))
+ block_size_bits = int(math.log(options.cacheline_size, 2))
+
+ for i in xrange(options.num_cpus):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l1i_cache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc,
+ start_index_bit = block_size_bits,
+ is_icache = True)
+ l1d_cache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc,
+ start_index_bit = block_size_bits,
+ is_icache = False)
+
+ prefetcher = RubyPrefetcher.Prefetcher()
+
+ l1_cntrl = L1Cache_Controller(version = i,
+ L1Icache = l1i_cache,
+ L1Dcache = l1d_cache,
+ l2_select_num_bits = l2_bits,
+ send_evictions = (
+ options.cpu_type == "detailed"),
+ prefetcher = prefetcher,
+ ruby_system = ruby_system,
+ transitions_per_cycle=options.ports,
+ enable_prefetch = False)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ ruby_system = ruby_system)
+
+ l1_cntrl.sequencer = cpu_seq
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.slave
+
+ exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
+
+ #
+ # Add controllers and sequencers to the appropriate lists
+ #
+ cpu_sequencers.append(cpu_seq)
+ l1_cntrl_nodes.append(l1_cntrl)
+
+ l2_index_start = block_size_bits + l2_bits
+
+ for i in xrange(options.num_l2caches):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l2_cache = L2Cache(size = options.l2_size,
+ assoc = options.l2_assoc,
+ start_index_bit = l2_index_start)
+
+ l2_cntrl = L2Cache_Controller(version = i,
+ L2cache = l2_cache,
+ transitions_per_cycle=options.ports,
+ ruby_system = ruby_system)
+
+ exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
+ l2_cntrl_nodes.append(l2_cntrl)
+
+ phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
+ assert(phys_mem_size % options.num_dirs == 0)
+ mem_module_size = phys_mem_size / options.num_dirs
+
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
+ for i in xrange(options.num_dirs):
+ #
+ # Create the Ruby objects associated with the directory controller
+ #
+
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
+
+ dir_size = MemorySize('0B')
+ dir_size.value = mem_module_size
+
+ dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size,
+ use_map =
+ options.use_map),
+ memBuffer = mem_cntrl,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
+
+ exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
+ dir_cntrl_nodes.append(dir_cntrl)
+
+ for i, dma_port in enumerate(dma_ports):
+ #
+ # Create the Ruby objects associated with the dma controller
+ #
+ dma_seq = DMASequencer(version = i,
+ ruby_system = ruby_system)
+
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
+
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+ exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
+ dma_cntrl_nodes.append(dma_cntrl)
+
+ all_cntrls = l1_cntrl_nodes + \
+ l2_cntrl_nodes + \
+ dir_cntrl_nodes + \
+ dma_cntrl_nodes
+
+ topology = create_topology(all_cntrls, options)
+
+ return (cpu_sequencers, dir_cntrl_nodes, topology)
+++ /dev/null
-/*
- * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-machine(L1Cache, "MESI Directory L1 Cache CMP")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- Prefetcher * prefetcher = 'NULL',
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
- bool send_evictions,
- bool enable_prefetch = "False"
-{
- // NODE L1 CACHE
- // From this node's L1 cache TO the network
- // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
- MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false", vnet_type="request";
- // a local L1 -> this L2 bank
- MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false", vnet_type="response";
- MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false", vnet_type="unblock";
-
-
- // To this node's L1 cache FROM the network
- // a L2 bank -> this L1
- MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false", vnet_type="request";
- // a L2 bank -> this L1
- MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false", vnet_type="response";
- // Request Buffer for prefetches
- MessageBuffer optionalQueue, ordered="false";
-
-
- // STATES
- state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
- // Base states
- NP, AccessPermission:Invalid, desc="Not present in either cache";
- I, AccessPermission:Invalid, desc="a L1 cache entry Idle";
- S, AccessPermission:Read_Only, desc="a L1 cache entry Shared";
- E, AccessPermission:Read_Only, desc="a L1 cache entry Exclusive";
- M, AccessPermission:Read_Write, desc="a L1 cache entry Modified", format="!b";
-
- // Transient States
- IS, AccessPermission:Busy, desc="L1 idle, issued GETS, have not seen response yet";
- IM, AccessPermission:Busy, desc="L1 idle, issued GETX, have not seen response yet";
- SM, AccessPermission:Read_Only, desc="L1 idle, issued GETX, have not seen response yet";
- IS_I, AccessPermission:Busy, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
-
- M_I, AccessPermission:Busy, desc="L1 replacing, waiting for ACK";
- SINK_WB_ACK, AccessPermission:Busy, desc="This is to sink WB_Acks from L2";
-
- // Transient States in which block is being prefetched
- PF_IS, AccessPermission:Busy, desc="Issued GETS, have not seen response yet";
- PF_IM, AccessPermission:Busy, desc="Issued GETX, have not seen response yet";
- PF_SM, AccessPermission:Busy, desc="Issued GETX, received data, waiting for acks";
- PF_IS_I, AccessPermission:Busy, desc="Issued GETs, saw inv before data";
- }
-
- // EVENTS
- enumeration(Event, desc="Cache events") {
- // L1 events
- Load, desc="Load request from the home processor";
- Ifetch, desc="I-fetch request from the home processor";
- Store, desc="Store request from the home processor";
-
- Inv, desc="Invalidate request from L2 bank";
-
- // internal generated request
- L1_Replacement, desc="L1 Replacement", format="!r";
-
- // other requests
- Fwd_GETX, desc="GETX from other processor";
- Fwd_GETS, desc="GETS from other processor";
- Fwd_GET_INSTR, desc="GET_INSTR from other processor";
-
- Data, desc="Data for processor";
- Data_Exclusive, desc="Data for processor";
- DataS_fromL1, desc="data for GETS request, need to unblock directory";
- Data_all_Acks, desc="Data for processor, all acks";
-
- Ack, desc="Ack for processor";
- Ack_all, desc="Last ack for processor";
-
- WB_Ack, desc="Ack for replacement";
-
- PF_Load, desc="load request from prefetcher";
- PF_Ifetch, desc="instruction fetch request from prefetcher";
- PF_Store, desc="exclusive load request from prefetcher";
- }
-
- // TYPES
-
- // CacheEntry
- structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
- State CacheState, desc="cache state";
- DataBlock DataBlk, desc="data for the block";
- bool Dirty, default="false", desc="data is dirty";
- bool isPrefetch, desc="Set if this block was prefetched";
- }
-
- // TBE fields
- structure(TBE, desc="...") {
- Address Addr, desc="Physical address for this TBE";
- State TBEState, desc="Transient state";
- DataBlock DataBlk, desc="Buffer for the data block";
- bool Dirty, default="false", desc="data is dirty";
- bool isPrefetch, desc="Set if this was caused by a prefetch";
- int pendingAcks, default="0", desc="number of pending acks";
- }
-
- structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
- }
-
- TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
-
- MessageBuffer mandatoryQueue, ordered="false";
-
- int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
-
- void set_cache_entry(AbstractCacheEntry a);
- void unset_cache_entry();
- void set_tbe(TBE a);
- void unset_tbe();
- void wakeUpBuffers(Address a);
- void profileMsgDelay(int virtualNetworkType, Cycles c);
-
- // inclusive cache returns L1 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
- Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
- if(is_valid(L1Dcache_entry)) {
- return L1Dcache_entry;
- }
-
- Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
- return L1Icache_entry;
- }
-
- Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
- Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
- return L1Dcache_entry;
- }
-
- Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
- Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
- return L1Icache_entry;
- }
-
- State getState(TBE tbe, Entry cache_entry, Address addr) {
- assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
-
- if(is_valid(tbe)) {
- return tbe.TBEState;
- } else if (is_valid(cache_entry)) {
- return cache_entry.CacheState;
- }
- return State:NP;
- }
-
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
- assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
-
- // MUST CHANGE
- if(is_valid(tbe)) {
- tbe.TBEState := state;
- }
-
- if (is_valid(cache_entry)) {
- cache_entry.CacheState := state;
- }
- }
-
- AccessPermission getAccessPermission(Address addr) {
- TBE tbe := L1_TBEs[addr];
- if(is_valid(tbe)) {
- DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
- return L1Cache_State_to_permission(tbe.TBEState);
- }
-
- Entry cache_entry := getCacheEntry(addr);
- if(is_valid(cache_entry)) {
- DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(cache_entry.CacheState));
- return L1Cache_State_to_permission(cache_entry.CacheState);
- }
-
- DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
- return AccessPermission:NotPresent;
- }
-
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
- TBE tbe := L1_TBEs[addr];
- if(is_valid(tbe)) {
- return tbe.DataBlk;
- }
-
- return getCacheEntry(addr).DataBlk;
- }
-
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
- if (is_valid(cache_entry)) {
- cache_entry.changePermission(L1Cache_State_to_permission(state));
- }
- }
-
- Event mandatory_request_type_to_event(RubyRequestType type) {
- if (type == RubyRequestType:LD) {
- return Event:Load;
- } else if (type == RubyRequestType:IFETCH) {
- return Event:Ifetch;
- } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
- return Event:Store;
- } else {
- error("Invalid RubyRequestType");
- }
- }
-
- Event prefetch_request_type_to_event(RubyRequestType type) {
- if (type == RubyRequestType:LD) {
- return Event:PF_Load;
- } else if (type == RubyRequestType:IFETCH) {
- return Event:PF_Ifetch;
- } else if ((type == RubyRequestType:ST) ||
- (type == RubyRequestType:ATOMIC)) {
- return Event:PF_Store;
- } else {
- error("Invalid RubyRequestType");
- }
- }
-
- int getPendingAcks(TBE tbe) {
- return tbe.pendingAcks;
- }
-
- out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
- out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
- out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
- out_port(optionalQueue_out, RubyRequest, optionalQueue);
-
-
- // Prefetch queue between the controller and the prefetcher
- // As per Spracklen et al. (HPCA 2005), the prefetch queue should be
- // implemented as a LIFO structure. The structure would allow for fast
- // searches of all entries in the queue, not just the head msg. All
- // msgs in the structure can be invalidated if a demand miss matches.
- in_port(optionalQueue_in, RubyRequest, optionalQueue, desc="...", rank = 3) {
- if (optionalQueue_in.isReady()) {
- peek(optionalQueue_in, RubyRequest) {
- // Instruction Prefetch
- if (in_msg.Type == RubyRequestType:IFETCH) {
- Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
- if (is_valid(L1Icache_entry)) {
- // The block to be prefetched is already present in the
- // cache. We should drop this request.
- trigger(prefetch_request_type_to_event(in_msg.Type),
- in_msg.LineAddress,
- L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
- }
-
- // Check to see if it is in the OTHER L1
- Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
- if (is_valid(L1Dcache_entry)) {
- // The block is in the wrong L1 cache. We should drop
- // this request.
- trigger(prefetch_request_type_to_event(in_msg.Type),
- in_msg.LineAddress,
- L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
- }
-
- if (L1Icache.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it
- // in the L1 so let's see if the L2 has it
- trigger(prefetch_request_type_to_event(in_msg.Type),
- in_msg.LineAddress,
- L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
- } else {
- // No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement,
- L1Icache.cacheProbe(in_msg.LineAddress),
- getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
- L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
- }
- } else {
- // Data prefetch
- Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
- if (is_valid(L1Dcache_entry)) {
- // The block to be prefetched is already present in the
- // cache. We should drop this request.
- trigger(prefetch_request_type_to_event(in_msg.Type),
- in_msg.LineAddress,
- L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
- }
-
- // Check to see if it is in the OTHER L1
- Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
- if (is_valid(L1Icache_entry)) {
- // The block is in the wrong L1. Just drop the prefetch
- // request.
- trigger(prefetch_request_type_to_event(in_msg.Type),
- in_msg.LineAddress,
- L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
- }
-
- if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it in
- // the L1 let's see if the L2 has it
- trigger(prefetch_request_type_to_event(in_msg.Type),
- in_msg.LineAddress,
- L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
- } else {
- // No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement,
- L1Dcache.cacheProbe(in_msg.LineAddress),
- getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
- L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
- }
- }
- }
- }
- }
-
- // Response IntraChip L1 Network - response msg to this L1 cache
- in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) {
- if (responseIntraChipL1Network_in.isReady()) {
- peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Addr") {
- assert(in_msg.Destination.isElement(machineID));
-
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := L1_TBEs[in_msg.Addr];
-
- if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
- trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
- } else if(in_msg.Type == CoherenceResponseType:DATA) {
- if ((getState(tbe, cache_entry, in_msg.Addr) == State:IS ||
- getState(tbe, cache_entry, in_msg.Addr) == State:IS_I ||
- getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS ||
- getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS_I) &&
- machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
-
- trigger(Event:DataS_fromL1, in_msg.Addr, cache_entry, tbe);
-
- } else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Data_all_Acks, in_msg.Addr, cache_entry, tbe);
- } else {
- trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
- }
- } else if (in_msg.Type == CoherenceResponseType:ACK) {
- if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
- trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
- } else {
- trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
- }
- } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
- trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
- } else {
- error("Invalid L1 response type");
- }
- }
- }
- }
-
- // Request InterChip network - request from this L1 cache to the shared L2
- in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache, rank = 1) {
- if(requestIntraChipL1Network_in.isReady()) {
- peek(requestIntraChipL1Network_in, RequestMsg, block_on="Addr") {
- assert(in_msg.Destination.isElement(machineID));
-
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := L1_TBEs[in_msg.Addr];
-
- if (in_msg.Type == CoherenceRequestType:INV) {
- trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceRequestType:GETX ||
- in_msg.Type == CoherenceRequestType:UPGRADE) {
- // upgrade transforms to GETX due to race
- trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceRequestType:GETS) {
- trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
- trigger(Event:Fwd_GET_INSTR, in_msg.Addr, cache_entry, tbe);
- } else {
- error("Invalid forwarded request type");
- }
- }
- }
- }
-
- // Mandatory Queue betweens Node's CPU and it's L1 caches
- in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank = 0) {
- if (mandatoryQueue_in.isReady()) {
- peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
-
- // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
-
- if (in_msg.Type == RubyRequestType:IFETCH) {
- // ** INSTRUCTION ACCESS ***
-
- Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
- if (is_valid(L1Icache_entry)) {
- // The tag matches for the L1, so the L1 asks the L2 for it.
- trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
- L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
- } else {
-
- // Check to see if it is in the OTHER L1
- Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
- if (is_valid(L1Dcache_entry)) {
- // The block is in the wrong L1, put the request on the queue to the shared L2
- trigger(Event:L1_Replacement, in_msg.LineAddress,
- L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
- }
-
- if (L1Icache.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it
- // in the L1 so let's see if the L2 has it.
- trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
- L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
- } else {
- // No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement, L1Icache.cacheProbe(in_msg.LineAddress),
- getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
- L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
- }
- }
- } else {
-
- // *** DATA ACCESS ***
- Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
- if (is_valid(L1Dcache_entry)) {
- // The tag matches for the L1, so the L1 ask the L2 for it
- trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
- L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
- } else {
-
- // Check to see if it is in the OTHER L1
- Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
- if (is_valid(L1Icache_entry)) {
- // The block is in the wrong L1, put the request on the queue to the shared L2
- trigger(Event:L1_Replacement, in_msg.LineAddress,
- L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
- }
-
- if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
- // L1 does't have the line, but we have space for it
- // in the L1 let's see if the L2 has it.
- trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
- L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
- } else {
- // No room in the L1, so we need to make room in the L1
- trigger(Event:L1_Replacement, L1Dcache.cacheProbe(in_msg.LineAddress),
- getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
- L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
- }
- }
- }
- }
- }
- }
-
- void enqueuePrefetch(Address address, RubyRequestType type) {
- enqueue(optionalQueue_out, RubyRequest, latency=1) {
- out_msg.LineAddress := address;
- out_msg.Type := type;
- out_msg.AccessMode := RubyAccessMode:Supervisor;
- }
- }
-
- // ACTIONS
- action(a_issueGETS, "a", desc="Issue GETS") {
- peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:GETS;
- out_msg.Requestor := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
- out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.AccessMode := in_msg.AccessMode;
- }
- }
- }
-
- action(pa_issuePfGETS, "pa", desc="Issue prefetch GETS") {
- peek(optionalQueue_in, RubyRequest) {
- enqueue(requestIntraChipL1Network_out, RequestMsg,
- latency=l1_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:GETS;
- out_msg.Requestor := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
- out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.AccessMode := in_msg.AccessMode;
- }
- }
- }
-
- action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
- peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:GET_INSTR;
- out_msg.Requestor := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
- out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.AccessMode := in_msg.AccessMode;
- }
- }
- }
-
- action(pai_issuePfGETINSTR, "pai",
- desc="Issue GETINSTR for prefetch request") {
- peek(optionalQueue_in, RubyRequest) {
- enqueue(requestIntraChipL1Network_out, RequestMsg,
- latency=l1_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:GET_INSTR;
- out_msg.Requestor := machineID;
- out_msg.Destination.add(
- mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.AccessMode := in_msg.AccessMode;
-
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
- }
- }
- }
-
- action(b_issueGETX, "b", desc="Issue GETX") {
- peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:GETX;
- out_msg.Requestor := machineID;
- DPRINTF(RubySlicc, "%s\n", machineID);
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
- out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.AccessMode := in_msg.AccessMode;
- }
- }
- }
-
- action(pb_issuePfGETX, "pb", desc="Issue prefetch GETX") {
- peek(optionalQueue_in, RubyRequest) {
- enqueue(requestIntraChipL1Network_out, RequestMsg,
- latency=l1_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:GETX;
- out_msg.Requestor := machineID;
- DPRINTF(RubySlicc, "%s\n", machineID);
-
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
-
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
- out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.AccessMode := in_msg.AccessMode;
- }
- }
- }
-
- action(c_issueUPGRADE, "c", desc="Issue GETX") {
- peek(mandatoryQueue_in, RubyRequest) {
- enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:UPGRADE;
- out_msg.Requestor := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- DPRINTF(RubySlicc, "address: %s, destination: %s\n",
- address, out_msg.Destination);
- out_msg.MessageSize := MessageSizeType:Control;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.AccessMode := in_msg.AccessMode;
- }
- }
- }
-
- action(d_sendDataToRequestor, "d", desc="send data to requestor") {
- peek(requestIntraChipL1Network_in, RequestMsg) {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.Dirty := cache_entry.Dirty;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
- }
-
- action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.Dirty := cache_entry.Dirty;
- out_msg.Sender := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
-
- action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
- peek(requestIntraChipL1Network_in, RequestMsg) {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- assert(is_valid(tbe));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := tbe.DataBlk;
- out_msg.Dirty := tbe.Dirty;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
- }
-
- action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- assert(is_valid(tbe));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := tbe.DataBlk;
- out_msg.Dirty := tbe.Dirty;
- out_msg.Sender := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
-
- action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
- peek(requestIntraChipL1Network_in, RequestMsg) {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:ACK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.MessageSize := MessageSizeType:Response_Control;
- }
- }
- }
-
- action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.Dirty := cache_entry.Dirty;
- out_msg.Sender := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- out_msg.MessageSize := MessageSizeType:Writeback_Data;
- }
- }
-
- action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- assert(is_valid(tbe));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := tbe.DataBlk;
- out_msg.Dirty := tbe.Dirty;
- out_msg.Sender := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- out_msg.MessageSize := MessageSizeType:Writeback_Data;
- }
- }
-
- action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
- peek(requestIntraChipL1Network_in, RequestMsg) {
- enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:ACK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.MessageSize := MessageSizeType:Response_Control;
- out_msg.AckCount := 1;
- }
- }
- }
-
- action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
- if (send_evictions) {
- DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
- sequencer.evictionCallback(address);
- }
- }
-
- action(g_issuePUTX, "g", desc="send data to the L2 cache") {
- enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:PUTX;
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.Dirty := cache_entry.Dirty;
- out_msg.Requestor:= machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- if (cache_entry.Dirty) {
- out_msg.MessageSize := MessageSizeType:Writeback_Data;
- } else {
- out_msg.MessageSize := MessageSizeType:Writeback_Control;
- }
- }
- }
-
- action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
- enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:UNBLOCK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- out_msg.MessageSize := MessageSizeType:Response_Control;
- DPRINTF(RubySlicc, "%s\n", address);
- }
- }
-
- action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
- enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits, intToID(0)));
- out_msg.MessageSize := MessageSizeType:Response_Control;
- DPRINTF(RubySlicc, "%s\n", address);
-
- }
- }
-
- action(dg_invalidate_sc, "dg",
- desc="Invalidate store conditional as the cache lost permissions") {
- sequencer.invalidateSC(address);
- }
-
- action(h_load_hit, "h",
- desc="If not prefetch, notify sequencer the load completed.")
- {
- assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- sequencer.readCallback(address, cache_entry.DataBlk);
- }
-
- action(hx_load_hit, "hx",
- desc="If not prefetch, notify sequencer the load completed.")
- {
- assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- sequencer.readCallback(address, cache_entry.DataBlk, true);
- }
-
- action(hh_store_hit, "\h",
- desc="If not prefetch, notify sequencer that store completed.")
- {
- assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- sequencer.writeCallback(address, cache_entry.DataBlk);
- cache_entry.Dirty := true;
- }
-
- action(hhx_store_hit, "\hx",
- desc="If not prefetch, notify sequencer that store completed.")
- {
- assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
- sequencer.writeCallback(address, cache_entry.DataBlk, true);
- cache_entry.Dirty := true;
- }
-
- action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
- check_allocate(L1_TBEs);
- assert(is_valid(cache_entry));
- L1_TBEs.allocate(address);
- set_tbe(L1_TBEs[address]);
- tbe.isPrefetch := false;
- tbe.Dirty := cache_entry.Dirty;
- tbe.DataBlk := cache_entry.DataBlk;
- }
-
- action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
- mandatoryQueue_in.dequeue();
- }
-
- action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") {
- profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles());
- }
-
- action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") {
- profileMsgDelay(1, responseIntraChipL1Network_in.dequeue_getDelayCycles());
- }
-
- action(s_deallocateTBE, "s", desc="Deallocate TBE") {
- L1_TBEs.deallocate(address);
- unset_tbe();
- }
-
- action(u_writeDataToL1Cache, "u", desc="Write data to cache") {
- peek(responseIntraChipL1Network_in, ResponseMsg) {
- assert(is_valid(cache_entry));
- cache_entry.DataBlk := in_msg.DataBlk;
- cache_entry.Dirty := in_msg.Dirty;
- }
- }
-
- action(q_updateAckCount, "q", desc="Update ack count") {
- peek(responseIntraChipL1Network_in, ResponseMsg) {
- assert(is_valid(tbe));
- tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
- APPEND_TRANSITION_COMMENT(in_msg.AckCount);
- APPEND_TRANSITION_COMMENT(" p: ");
- APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
- }
- }
-
- action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
- if (L1Dcache.isTagPresent(address)) {
- L1Dcache.deallocate(address);
- } else {
- L1Icache.deallocate(address);
- }
- unset_cache_entry();
- }
-
- action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
- if (is_invalid(cache_entry)) {
- set_cache_entry(L1Dcache.allocate(address, new Entry));
- }
- }
-
- action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
- if (is_invalid(cache_entry)) {
- set_cache_entry(L1Icache.allocate(address, new Entry));
- }
- }
-
- action(z_stallAndWaitMandatoryQueue, "\z", desc="recycle L1 request queue") {
- stall_and_wait(mandatoryQueue_in, address);
- }
-
- action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
- wakeUpBuffers(address);
- }
-
- action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
- ++L1Icache.demand_misses;
- }
-
- action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
- ++L1Icache.demand_hits;
- }
-
- action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
- ++L1Dcache.demand_misses;
- }
-
- action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
- ++L1Dcache.demand_hits;
- }
-
- action(po_observeMiss, "\po", desc="Inform the prefetcher about the miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- if (enable_prefetch) {
- prefetcher.observeMiss(in_msg.LineAddress, in_msg.Type);
- }
- }
- }
-
- action(ppm_observePfMiss, "\ppm",
- desc="Inform the prefetcher about the partial miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- prefetcher.observePfMiss(in_msg.LineAddress);
- }
- }
-
- action(pq_popPrefetchQueue, "\pq", desc="Pop the prefetch request queue") {
- optionalQueue_in.dequeue();
- }
-
- action(mp_markPrefetched, "mp", desc="Write data from response queue to cache") {
- assert(is_valid(cache_entry));
- cache_entry.isPrefetch := true;
- }
-
-
- //*****************************************************
- // TRANSITIONS
- //*****************************************************
-
- // Transitions for Load/Store/Replacement/WriteBack from transient states
- transition({IS, IM, IS_I, M_I, SM, SINK_WB_ACK}, {Load, Ifetch, Store, L1_Replacement}) {
- z_stallAndWaitMandatoryQueue;
- }
-
- transition({PF_IS, PF_IS_I}, {Store, L1_Replacement}) {
- z_stallAndWaitMandatoryQueue;
- }
-
- transition({PF_IM, PF_SM}, {Load, Ifetch, L1_Replacement}) {
- z_stallAndWaitMandatoryQueue;
- }
-
- // Transitions from Idle
- transition({NP,I}, L1_Replacement) {
- ff_deallocateL1CacheBlock;
- }
-
- transition({S,E,M,IS,IM,SM,IS_I,M_I,SINK_WB_ACK,PF_IS,PF_IM},
- {PF_Load, PF_Store, PF_Ifetch}) {
- pq_popPrefetchQueue;
- }
-
- transition({NP,I}, Load, IS) {
- oo_allocateL1DCacheBlock;
- i_allocateTBE;
- a_issueGETS;
- uu_profileDataMiss;
- po_observeMiss;
- k_popMandatoryQueue;
- }
-
- transition({NP,I}, PF_Load, PF_IS) {
- oo_allocateL1DCacheBlock;
- i_allocateTBE;
- pa_issuePfGETS;
- pq_popPrefetchQueue;
- }
-
- transition(PF_IS, Load, IS) {
- uu_profileDataMiss;
- ppm_observePfMiss;
- k_popMandatoryQueue;
- }
-
- transition(PF_IS_I, Load, IS_I) {
- uu_profileDataMiss;
- ppm_observePfMiss;
- k_popMandatoryQueue;
- }
-
- transition({NP,I}, Ifetch, IS) {
- pp_allocateL1ICacheBlock;
- i_allocateTBE;
- ai_issueGETINSTR;
- uu_profileInstMiss;
- po_observeMiss;
- k_popMandatoryQueue;
- }
-
- transition({NP,I}, PF_Ifetch, PF_IS) {
- pp_allocateL1ICacheBlock;
- i_allocateTBE;
- pai_issuePfGETINSTR;
- pq_popPrefetchQueue;
- }
-
- // We proactively assume that the prefetch is in to
- // the instruction cache
- transition(PF_IS, Ifetch, IS) {
- uu_profileDataMiss;
- ppm_observePfMiss;
- k_popMandatoryQueue;
- }
-
- transition({NP,I}, Store, IM) {
- oo_allocateL1DCacheBlock;
- i_allocateTBE;
- b_issueGETX;
- uu_profileDataMiss;
- po_observeMiss;
- k_popMandatoryQueue;
- }
-
- transition({NP,I}, PF_Store, PF_IM) {
- oo_allocateL1DCacheBlock;
- i_allocateTBE;
- pb_issuePfGETX;
- pq_popPrefetchQueue;
- }
-
- transition(PF_IM, Store, IM) {
- uu_profileDataMiss;
- ppm_observePfMiss;
- k_popMandatoryQueue;
- }
-
- transition(PF_SM, Store, SM) {
- uu_profileDataMiss;
- ppm_observePfMiss;
- k_popMandatoryQueue;
- }
-
- transition({NP, I}, Inv) {
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- // Transitions from Shared
- transition({S,E,M}, Load) {
- h_load_hit;
- uu_profileDataHit;
- k_popMandatoryQueue;
- }
-
- transition({S,E,M}, Ifetch) {
- h_load_hit;
- uu_profileInstHit;
- k_popMandatoryQueue;
- }
-
- transition(S, Store, SM) {
- i_allocateTBE;
- c_issueUPGRADE;
- uu_profileDataMiss;
- k_popMandatoryQueue;
- }
-
- transition(S, L1_Replacement, I) {
- forward_eviction_to_cpu;
- ff_deallocateL1CacheBlock;
- }
-
- transition(S, Inv, I) {
- forward_eviction_to_cpu;
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- // Transitions from Exclusive
-
- transition({E,M}, Store, M) {
- hh_store_hit;
- uu_profileDataHit;
- k_popMandatoryQueue;
- }
-
- transition(E, L1_Replacement, M_I) {
- // silent E replacement??
- forward_eviction_to_cpu;
- i_allocateTBE;
- g_issuePUTX; // send data, but hold in case forwarded request
- ff_deallocateL1CacheBlock;
- }
-
- transition(E, Inv, I) {
- // don't send data
- forward_eviction_to_cpu;
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- transition(E, Fwd_GETX, I) {
- forward_eviction_to_cpu;
- d_sendDataToRequestor;
- l_popRequestQueue;
- }
-
- transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
- d_sendDataToRequestor;
- d2_sendDataToL2;
- l_popRequestQueue;
- }
-
- // Transitions from Modified
-
- transition(M, L1_Replacement, M_I) {
- forward_eviction_to_cpu;
- i_allocateTBE;
- g_issuePUTX; // send data, but hold in case forwarded request
- ff_deallocateL1CacheBlock;
- }
-
- transition(M_I, WB_Ack, I) {
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(M, Inv, I) {
- forward_eviction_to_cpu;
- f_sendDataToL2;
- l_popRequestQueue;
- }
-
- transition(M_I, Inv, SINK_WB_ACK) {
- ft_sendDataToL2_fromTBE;
- l_popRequestQueue;
- }
-
- transition(M, Fwd_GETX, I) {
- forward_eviction_to_cpu;
- d_sendDataToRequestor;
- l_popRequestQueue;
- }
-
- transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
- d_sendDataToRequestor;
- d2_sendDataToL2;
- l_popRequestQueue;
- }
-
- transition(M_I, Fwd_GETX, SINK_WB_ACK) {
- dt_sendDataToRequestor_fromTBE;
- l_popRequestQueue;
- }
-
- transition(M_I, {Fwd_GETS, Fwd_GET_INSTR}, SINK_WB_ACK) {
- dt_sendDataToRequestor_fromTBE;
- d2t_sendDataToL2_fromTBE;
- l_popRequestQueue;
- }
-
- // Transitions from IS
- transition({IS, IS_I}, Inv, IS_I) {
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- transition({PF_IS, PF_IS_I}, Inv, PF_IS_I) {
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- transition(IS, Data_all_Acks, S) {
- u_writeDataToL1Cache;
- hx_load_hit;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(PF_IS, Data_all_Acks, S) {
- u_writeDataToL1Cache;
- s_deallocateTBE;
- mp_markPrefetched;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(IS_I, Data_all_Acks, I) {
- u_writeDataToL1Cache;
- hx_load_hit;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(PF_IS_I, Data_all_Acks, I) {
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(IS, DataS_fromL1, S) {
- u_writeDataToL1Cache;
- j_sendUnblock;
- hx_load_hit;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(PF_IS, DataS_fromL1, S) {
- u_writeDataToL1Cache;
- j_sendUnblock;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(IS_I, DataS_fromL1, I) {
- u_writeDataToL1Cache;
- j_sendUnblock;
- hx_load_hit;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(PF_IS_I, DataS_fromL1, I) {
- j_sendUnblock;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- // directory is blocked when sending exclusive data
- transition(IS_I, Data_Exclusive, E) {
- u_writeDataToL1Cache;
- hx_load_hit;
- jj_sendExclusiveUnblock;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- // directory is blocked when sending exclusive data
- transition(PF_IS_I, Data_Exclusive, E) {
- u_writeDataToL1Cache;
- jj_sendExclusiveUnblock;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(IS, Data_Exclusive, E) {
- u_writeDataToL1Cache;
- hx_load_hit;
- jj_sendExclusiveUnblock;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(PF_IS, Data_Exclusive, E) {
- u_writeDataToL1Cache;
- jj_sendExclusiveUnblock;
- s_deallocateTBE;
- mp_markPrefetched;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- // Transitions from IM
- transition(IM, Inv, IM) {
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- transition({PF_IM, PF_SM}, Inv, PF_IM) {
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- transition(IM, Data, SM) {
- u_writeDataToL1Cache;
- q_updateAckCount;
- o_popIncomingResponseQueue;
- }
-
- transition(PF_IM, Data, PF_SM) {
- u_writeDataToL1Cache;
- q_updateAckCount;
- o_popIncomingResponseQueue;
- }
-
- transition(IM, Data_all_Acks, M) {
- u_writeDataToL1Cache;
- hhx_store_hit;
- jj_sendExclusiveUnblock;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(PF_IM, Data_all_Acks, M) {
- u_writeDataToL1Cache;
- jj_sendExclusiveUnblock;
- s_deallocateTBE;
- mp_markPrefetched;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- // transitions from SM
- transition(SM, Inv, IM) {
- fi_sendInvAck;
- dg_invalidate_sc;
- l_popRequestQueue;
- }
-
- transition({SM, IM, PF_SM, PF_IM}, Ack) {
- q_updateAckCount;
- o_popIncomingResponseQueue;
- }
-
- transition(SM, Ack_all, M) {
- jj_sendExclusiveUnblock;
- hhx_store_hit;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(PF_SM, Ack_all, M) {
- jj_sendExclusiveUnblock;
- s_deallocateTBE;
- mp_markPrefetched;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(SINK_WB_ACK, Inv){
- fi_sendInvAck;
- l_popRequestQueue;
- }
-
- transition(SINK_WB_ACK, WB_Ack, I){
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-}
+++ /dev/null
-/*
- * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * $Id: MSI_MOSI_CMP_directory-L2cache.sm 1.12 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
- *
- */
-
-machine(L2Cache, "MESI Directory L2 Cache CMP")
- : CacheMemory * L2cache,
- Cycles l2_request_latency = 2,
- Cycles l2_response_latency = 2,
- Cycles to_l1_latency = 1
-{
- // L2 BANK QUEUES
- // From local bank of L2 cache TO the network
- MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0",
- ordered="false", vnet_type="request"; // this L2 bank -> Memory
- MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0",
- ordered="false", vnet_type="request"; // this L2 bank -> a local L1
- MessageBuffer responseFromL2Cache, network="To", virtual_network="1",
- ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || Memory
-
- // FROM the network to this local bank of L2 cache
- MessageBuffer unblockToL2Cache, network="From", virtual_network="2",
- ordered="false", vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
- MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0",
- ordered="false", vnet_type="request"; // a local L1 -> this L2 bank
- MessageBuffer responseToL2Cache, network="From", virtual_network="1",
- ordered="false", vnet_type="response"; // a local L1 || Memory -> this L2 bank
-
- // STATES
- state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
- // Base states
- NP, AccessPermission:Invalid, desc="Not present in either cache";
- SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
- M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
- MT, AccessPermission:Maybe_Stale, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
-
- // L2 replacement
- M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
- MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
- MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
- I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
- S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
-
- // Transient States for fetching data from memory
- ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
- IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
- IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
-
- // Blocking states
- SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
- MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
-
- MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
- MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
- MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data, waiting for unblock";
-
- }
-
- // EVENTS
- enumeration(Event, desc="L2 Cache events") {
- // L2 events
-
- // events initiated by the local L1s
- L1_GET_INSTR, desc="a L1I GET INSTR request for a block maped to us";
- L1_GETS, desc="a L1D GETS request for a block maped to us";
- L1_GETX, desc="a L1D GETX request for a block maped to us";
- L1_UPGRADE, desc="a L1D GETX request for a block maped to us";
-
- L1_PUTX, desc="L1 replacing data";
- L1_PUTX_old, desc="L1 replacing data, but no longer sharer";
-
- // events initiated by this L2
- L2_Replacement, desc="L2 Replacement", format="!r";
- L2_Replacement_clean, desc="L2 Replacement, but data is clean", format="!r";
-
- // events from memory controller
- Mem_Data, desc="data from memory", format="!r";
- Mem_Ack, desc="ack from memory", format="!r";
-
- // M->S data writeback
- WB_Data, desc="data from L1";
- WB_Data_clean, desc="clean data from L1";
- Ack, desc="writeback ack";
- Ack_all, desc="writeback ack";
-
- Unblock, desc="Unblock from L1 requestor";
- Exclusive_Unblock, desc="Unblock from L1 requestor";
-
- MEM_Inv, desc="Invalidation from directory";
- }
-
- // TYPES
-
- // CacheEntry
- structure(Entry, desc="...", interface="AbstractCacheEntry") {
- State CacheState, desc="cache state";
- NetDest Sharers, desc="tracks the L1 shares on-chip";
- MachineID Exclusive, desc="Exclusive holder of block";
- DataBlock DataBlk, desc="data for the block";
- bool Dirty, default="false", desc="data is dirty";
- }
-
- // TBE fields
- structure(TBE, desc="...") {
- Address Addr, desc="Physical address for this TBE";
- State TBEState, desc="Transient state";
- DataBlock DataBlk, desc="Buffer for the data block";
- bool Dirty, default="false", desc="Data is Dirty";
-
- NetDest L1_GetS_IDs, desc="Set of the internal processors that want the block in shared state";
- MachineID L1_GetX_ID, desc="ID of the L1 cache to forward the block to once we get a response";
- int pendingAcks, desc="number of pending acks for invalidates during writeback";
- }
-
- structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
- }
-
- TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
-
- void set_cache_entry(AbstractCacheEntry a);
- void unset_cache_entry();
- void set_tbe(TBE a);
- void unset_tbe();
- void wakeUpBuffers(Address a);
- void profileMsgDelay(int virtualNetworkType, Cycles c);
-
- // inclusive cache, returns L2 entries only
- Entry getCacheEntry(Address addr), return_by_pointer="yes" {
- return static_cast(Entry, "pointer", L2cache[addr]);
- }
-
- bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
- if (is_valid(cache_entry)) {
- return cache_entry.Sharers.isElement(requestor);
- } else {
- return false;
- }
- }
-
- void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
- assert(is_valid(cache_entry));
- DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
- machineID, requestor, addr);
- cache_entry.Sharers.add(requestor);
- }
-
- State getState(TBE tbe, Entry cache_entry, Address addr) {
- if(is_valid(tbe)) {
- return tbe.TBEState;
- } else if (is_valid(cache_entry)) {
- return cache_entry.CacheState;
- }
- return State:NP;
- }
-
- void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
- // MUST CHANGE
- if (is_valid(tbe)) {
- tbe.TBEState := state;
- }
-
- if (is_valid(cache_entry)) {
- cache_entry.CacheState := state;
- }
- }
-
- AccessPermission getAccessPermission(Address addr) {
- TBE tbe := L2_TBEs[addr];
- if(is_valid(tbe)) {
- DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
- return L2Cache_State_to_permission(tbe.TBEState);
- }
-
- Entry cache_entry := getCacheEntry(addr);
- if(is_valid(cache_entry)) {
- DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(cache_entry.CacheState));
- return L2Cache_State_to_permission(cache_entry.CacheState);
- }
-
- DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
- return AccessPermission:NotPresent;
- }
-
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
- TBE tbe := L2_TBEs[addr];
- if(is_valid(tbe)) {
- return tbe.DataBlk;
- }
-
- return getCacheEntry(addr).DataBlk;
- }
-
- void setAccessPermission(Entry cache_entry, Address addr, State state) {
- if (is_valid(cache_entry)) {
- cache_entry.changePermission(L2Cache_State_to_permission(state));
- }
- }
-
- Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
- MachineID requestor, Entry cache_entry) {
- if(type == CoherenceRequestType:GETS) {
- return Event:L1_GETS;
- } else if(type == CoherenceRequestType:GET_INSTR) {
- return Event:L1_GET_INSTR;
- } else if (type == CoherenceRequestType:GETX) {
- return Event:L1_GETX;
- } else if (type == CoherenceRequestType:UPGRADE) {
- if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
- return Event:L1_UPGRADE;
- } else {
- return Event:L1_GETX;
- }
- } else if (type == CoherenceRequestType:PUTX) {
- if (isSharer(addr, requestor, cache_entry)) {
- return Event:L1_PUTX;
- } else {
- return Event:L1_PUTX_old;
- }
- } else {
- DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
- error("Invalid L1 forwarded request type");
- }
- }
-
- int getPendingAcks(TBE tbe) {
- return tbe.pendingAcks;
- }
-
- bool isDirty(Entry cache_entry) {
- assert(is_valid(cache_entry));
- return cache_entry.Dirty;
- }
-
- // ** OUT_PORTS **
-
- out_port(L1RequestIntraChipL2Network_out, RequestMsg, L1RequestFromL2Cache);
- out_port(DirRequestIntraChipL2Network_out, RequestMsg, DirRequestFromL2Cache);
- out_port(responseIntraChipL2Network_out, ResponseMsg, responseFromL2Cache);
-
-
- in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
- if(L1unblockNetwork_in.isReady()) {
- peek(L1unblockNetwork_in, ResponseMsg) {
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := L2_TBEs[in_msg.Addr];
- DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
- in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
- in_msg.Sender, in_msg.Type, in_msg.Destination);
-
- assert(in_msg.Destination.isElement(machineID));
- if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
- trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
- trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe);
- } else {
- error("unknown unblock message");
- }
- }
- }
- }
-
- // Response IntraChip L2 Network - response msg to this particular L2 bank
- in_port(responseIntraChipL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
- if (responseIntraChipL2Network_in.isReady()) {
- peek(responseIntraChipL2Network_in, ResponseMsg) {
- // test wether it's from a local L1 or an off chip source
- assert(in_msg.Destination.isElement(machineID));
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := L2_TBEs[in_msg.Addr];
-
- if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
- if(in_msg.Type == CoherenceResponseType:DATA) {
- if (in_msg.Dirty) {
- trigger(Event:WB_Data, in_msg.Addr, cache_entry, tbe);
- } else {
- trigger(Event:WB_Data_clean, in_msg.Addr, cache_entry, tbe);
- }
- } else if (in_msg.Type == CoherenceResponseType:ACK) {
- if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
- trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
- } else {
- trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
- }
- } else {
- error("unknown message type");
- }
-
- } else { // external message
- if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
- trigger(Event:Mem_Data, in_msg.Addr, cache_entry, tbe);
- } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
- trigger(Event:Mem_Ack, in_msg.Addr, cache_entry, tbe);
- } else if(in_msg.Type == CoherenceResponseType:INV) {
- trigger(Event:MEM_Inv, in_msg.Addr, cache_entry, tbe);
- } else {
- error("unknown message type");
- }
- }
- }
- } // if not ready, do nothing
- }
-
- // L1 Request
- in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
- if(L1RequestIntraChipL2Network_in.isReady()) {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- Entry cache_entry := getCacheEntry(in_msg.Addr);
- TBE tbe := L2_TBEs[in_msg.Addr];
-
- DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
- in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
- in_msg.Requestor, in_msg.Type, in_msg.Destination);
-
- assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
- assert(in_msg.Destination.isElement(machineID));
-
- if (is_valid(cache_entry)) {
- // The L2 contains the block, so proceeded with handling the request
- trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
- in_msg.Requestor, cache_entry),
- in_msg.Addr, cache_entry, tbe);
- } else {
- if (L2cache.cacheAvail(in_msg.Addr)) {
- // L2 does't have the line, but we have space for it in the L2
- trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
- in_msg.Requestor, cache_entry),
- in_msg.Addr, cache_entry, tbe);
- } else {
- // No room in the L2, so we need to make room before handling the request
- Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr));
- if (isDirty(L2cache_entry)) {
- trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
- L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
- } else {
- trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr),
- L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
- }
- }
- }
- }
- }
- }
-
-
- // ACTIONS
-
- action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency=l2_request_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:GETS;
- out_msg.Requestor := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
- out_msg.MessageSize := MessageSizeType:Control;
- }
- }
- }
-
- action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := in_msg.Type;
- out_msg.Requestor := in_msg.Requestor;
- out_msg.Destination.add(cache_entry.Exclusive);
- out_msg.MessageSize := MessageSizeType:Request_Control;
- }
- }
- }
-
- action(c_exclusiveReplacement, "c", desc="Send data to memory") {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:MEMORY_DATA;
- out_msg.Sender := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.Dirty := cache_entry.Dirty;
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
-
- action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:ACK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
- out_msg.MessageSize := MessageSizeType:Response_Control;
- }
- }
-
- action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
- assert(is_valid(tbe));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:MEMORY_DATA;
- out_msg.Sender := machineID;
- out_msg.Destination.add(map_Address_to_Directory(address));
- out_msg.DataBlk := tbe.DataBlk;
- out_msg.Dirty := tbe.Dirty;
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
-
- action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.MessageSize := MessageSizeType:Response_Data;
-
- out_msg.AckCount := 0 - cache_entry.Sharers.count();
- if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
- out_msg.AckCount := out_msg.AckCount + 1;
- }
- }
- }
- }
-
- action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.MessageSize := MessageSizeType:Response_Data;
-
- out_msg.AckCount := 0 - cache_entry.Sharers.count();
- if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
- out_msg.AckCount := out_msg.AckCount + 1;
- }
- }
- }
- }
-
- action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.MessageSize := MessageSizeType:Response_Data;
- out_msg.AckCount := 0;
- }
- }
- }
-
- action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
- assert(is_valid(tbe));
- assert(tbe.L1_GetS_IDs.count() > 0);
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.Sender := machineID;
- out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
-
- action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
- assert(is_valid(tbe));
- assert(tbe.L1_GetS_IDs.count() == 1);
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
- out_msg.Sender := machineID;
- out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
- out_msg.DataBlk := cache_entry.DataBlk;
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
-
- action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
- assert(is_valid(tbe));
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.Sender := machineID;
- out_msg.Destination.add(tbe.L1_GetX_ID);
- DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
- out_msg.DataBlk := cache_entry.DataBlk;
- DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
- out_msg.Addr, out_msg.Destination, out_msg.DataBlk);
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
-
- action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
- enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:INV;
- out_msg.Requestor := machineID;
- out_msg.Destination := cache_entry.Sharers;
- out_msg.MessageSize := MessageSizeType:Request_Control;
- }
- }
-
- action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:INV;
- out_msg.Requestor := in_msg.Requestor;
- out_msg.Destination := cache_entry.Sharers;
- out_msg.MessageSize := MessageSizeType:Request_Control;
- }
- }
- }
-
- action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceRequestType:INV;
- out_msg.Requestor := in_msg.Requestor;
- out_msg.Destination := cache_entry.Sharers;
- out_msg.Destination.remove(in_msg.Requestor);
- out_msg.MessageSize := MessageSizeType:Request_Control;
- }
- }
- }
-
- // OTHER ACTIONS
- action(i_allocateTBE, "i", desc="Allocate TBE for request") {
- check_allocate(L2_TBEs);
- assert(is_valid(cache_entry));
- L2_TBEs.allocate(address);
- set_tbe(L2_TBEs[address]);
- tbe.L1_GetS_IDs.clear();
- tbe.DataBlk := cache_entry.DataBlk;
- tbe.Dirty := cache_entry.Dirty;
- tbe.pendingAcks := cache_entry.Sharers.count();
- }
-
- action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
- L2_TBEs.deallocate(address);
- unset_tbe();
- }
-
- action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
- profileMsgDelay(0, L1RequestIntraChipL2Network_in.dequeue_getDelayCycles());
- }
-
- action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
- profileMsgDelay(0, L1unblockNetwork_in.dequeue_getDelayCycles());
- }
-
- action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
- profileMsgDelay(1, responseIntraChipL2Network_in.dequeue_getDelayCycles());
- }
-
- action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
- peek(responseIntraChipL2Network_in, ResponseMsg) {
- assert(is_valid(cache_entry));
- cache_entry.DataBlk := in_msg.DataBlk;
- if (in_msg.Dirty) {
- cache_entry.Dirty := in_msg.Dirty;
- }
- }
- }
-
- action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- assert(is_valid(cache_entry));
- cache_entry.DataBlk := in_msg.DataBlk;
- if (in_msg.Dirty) {
- cache_entry.Dirty := in_msg.Dirty;
- }
- }
- }
-
- action(q_updateAck, "q", desc="update pending ack count") {
- peek(responseIntraChipL2Network_in, ResponseMsg) {
- assert(is_valid(tbe));
- tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
- APPEND_TRANSITION_COMMENT(in_msg.AckCount);
- APPEND_TRANSITION_COMMENT(" p: ");
- APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
- }
- }
-
- action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
- peek(responseIntraChipL2Network_in, ResponseMsg) {
- assert(is_valid(tbe));
- tbe.DataBlk := in_msg.DataBlk;
- tbe.Dirty := in_msg.Dirty;
- }
- }
-
- action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- assert(is_valid(tbe));
- tbe.L1_GetS_IDs.add(in_msg.Requestor);
- }
- }
-
- action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- assert(is_valid(tbe));
- tbe.L1_GetX_ID := in_msg.Requestor;
- }
- }
-
- action(set_setMRU, "\set", desc="set the MRU entry") {
- L2cache.setMRU(address);
- }
-
- action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
- if (is_invalid(cache_entry)) {
- set_cache_entry(L2cache.allocate(address, new Entry));
- }
- }
-
- action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
- L2cache.deallocate(address);
- unset_cache_entry();
- }
-
- action(t_sendWBAck, "t", desc="Send writeback ACK") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:WB_ACK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.MessageSize := MessageSizeType:Response_Control;
- }
- }
- }
-
- action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
- assert(is_valid(cache_entry));
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:ACK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Requestor);
- out_msg.MessageSize := MessageSizeType:Response_Control;
- // upgrader doesn't get ack from itself, hence the + 1
- out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
- }
- }
- }
-
- action(uu_profileMiss, "\um", desc="Profile the demand miss") {
- ++L2cache.demand_misses;
- }
-
- action(uu_profileHit, "\uh", desc="Profile the demand hit") {
- ++L2cache.demand_hits;
- }
-
- action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- assert(is_valid(cache_entry));
- addSharer(address, in_msg.Requestor, cache_entry);
- APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
- }
- }
-
- action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
- peek(L1unblockNetwork_in, ResponseMsg) {
- assert(is_valid(cache_entry));
- addSharer(address, in_msg.Sender, cache_entry);
- }
- }
-
- action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- assert(is_valid(cache_entry));
- cache_entry.Sharers.remove(in_msg.Requestor);
- }
- }
-
- action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- assert(is_valid(cache_entry));
- cache_entry.Sharers.clear();
- }
- }
-
- action(mm_markExclusive, "\m", desc="set the exclusive owner") {
- peek(L1RequestIntraChipL2Network_in, RequestMsg) {
- assert(is_valid(cache_entry));
- cache_entry.Sharers.clear();
- cache_entry.Exclusive := in_msg.Requestor;
- addSharer(address, in_msg.Requestor, cache_entry);
- }
- }
-
- action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
- peek(L1unblockNetwork_in, ResponseMsg) {
- assert(is_valid(cache_entry));
- cache_entry.Sharers.clear();
- cache_entry.Exclusive := in_msg.Sender;
- addSharer(address, in_msg.Sender, cache_entry);
- }
- }
-
- action(zz_stallAndWaitL1RequestQueue, "zz", desc="recycle L1 request queue") {
- stall_and_wait(L1RequestIntraChipL2Network_in, address);
- }
-
- action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
- responseIntraChipL2Network_in.recycle();
- }
-
- action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
- wakeUpBuffers(address);
- }
-
- //*****************************************************
- // TRANSITIONS
- //*****************************************************
-
-
- //===============================================
- // BASE STATE - I
-
- // Transitions from I (Idle)
- transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, MT_IB, MT_SB}, L1_PUTX) {
- t_sendWBAck;
- jj_popL1RequestQueue;
- }
-
- transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, MT_IB, MT_SB}, L1_PUTX_old) {
- t_sendWBAck;
- jj_popL1RequestQueue;
- }
-
- transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
- zz_stallAndWaitL1RequestQueue;
- }
-
- transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
- zn_recycleResponseNetwork;
- }
-
- transition({I_I, S_I, M_I, MT_I, MCT_I, NP}, MEM_Inv) {
- o_popIncomingResponseQueue;
- }
-
-
- transition({SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
- zz_stallAndWaitL1RequestQueue;
- }
-
-
- transition(NP, L1_GETS, ISS) {
- qq_allocateL2CacheBlock;
- ll_clearSharers;
- nn_addSharer;
- i_allocateTBE;
- ss_recordGetSL1ID;
- a_issueFetchToMemory;
- uu_profileMiss;
- jj_popL1RequestQueue;
- }
-
- transition(NP, L1_GET_INSTR, IS) {
- qq_allocateL2CacheBlock;
- ll_clearSharers;
- nn_addSharer;
- i_allocateTBE;
- ss_recordGetSL1ID;
- a_issueFetchToMemory;
- uu_profileMiss;
- jj_popL1RequestQueue;
- }
-
- transition(NP, L1_GETX, IM) {
- qq_allocateL2CacheBlock;
- ll_clearSharers;
- // nn_addSharer;
- i_allocateTBE;
- xx_recordGetXL1ID;
- a_issueFetchToMemory;
- uu_profileMiss;
- jj_popL1RequestQueue;
- }
-
-
- // transitions from IS/IM
-
- transition(ISS, Mem_Data, MT_MB) {
- m_writeDataToCache;
- ex_sendExclusiveDataToGetSRequestors;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- }
-
- transition(IS, Mem_Data, SS) {
- m_writeDataToCache;
- e_sendDataToGetSRequestors;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(IM, Mem_Data, MT_MB) {
- m_writeDataToCache;
- ee_sendDataToGetXRequestor;
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- }
-
- transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
- nn_addSharer;
- ss_recordGetSL1ID;
- uu_profileMiss;
- jj_popL1RequestQueue;
- }
-
- transition({IS, ISS}, L1_GETX) {
- zz_stallAndWaitL1RequestQueue;
- }
-
- transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
- zz_stallAndWaitL1RequestQueue;
- }
-
- // transitions from SS
- transition(SS, {L1_GETS, L1_GET_INSTR}) {
- ds_sendSharedDataToRequestor;
- nn_addSharer;
- set_setMRU;
- uu_profileHit;
- jj_popL1RequestQueue;
- }
-
-
- transition(SS, L1_GETX, SS_MB) {
- d_sendDataToRequestor;
- // fw_sendFwdInvToSharers;
- fwm_sendFwdInvToSharersMinusRequestor;
- set_setMRU;
- uu_profileHit;
- jj_popL1RequestQueue;
- }
-
- transition(SS, L1_UPGRADE, SS_MB) {
- fwm_sendFwdInvToSharersMinusRequestor;
- ts_sendInvAckToUpgrader;
- set_setMRU;
- uu_profileHit;
- jj_popL1RequestQueue;
- }
-
- transition(SS, L2_Replacement_clean, I_I) {
- i_allocateTBE;
- f_sendInvToSharers;
- rr_deallocateL2CacheBlock;
- }
-
- transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
- i_allocateTBE;
- f_sendInvToSharers;
- rr_deallocateL2CacheBlock;
- }
-
-
- transition(M, L1_GETX, MT_MB) {
- d_sendDataToRequestor;
- set_setMRU;
- uu_profileHit;
- jj_popL1RequestQueue;
- }
-
- transition(M, L1_GET_INSTR, SS) {
- d_sendDataToRequestor;
- nn_addSharer;
- set_setMRU;
- uu_profileHit;
- jj_popL1RequestQueue;
- }
-
- transition(M, L1_GETS, MT_MB) {
- dd_sendExclusiveDataToRequestor;
- set_setMRU;
- uu_profileHit;
- jj_popL1RequestQueue;
- }
-
- transition(M, {L2_Replacement, MEM_Inv}, M_I) {
- i_allocateTBE;
- c_exclusiveReplacement;
- rr_deallocateL2CacheBlock;
- }
-
- transition(M, L2_Replacement_clean, M_I) {
- i_allocateTBE;
- c_exclusiveCleanReplacement;
- rr_deallocateL2CacheBlock;
- }
-
-
- // transitions from MT
-
- transition(MT, L1_GETX, MT_MB) {
- b_forwardRequestToExclusive;
- uu_profileMiss;
- set_setMRU;
- jj_popL1RequestQueue;
- }
-
-
- transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
- b_forwardRequestToExclusive;
- uu_profileMiss;
- set_setMRU;
- jj_popL1RequestQueue;
- }
-
- transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
- i_allocateTBE;
- f_sendInvToSharers;
- rr_deallocateL2CacheBlock;
- }
-
- transition(MT, L2_Replacement_clean, MCT_I) {
- i_allocateTBE;
- f_sendInvToSharers;
- rr_deallocateL2CacheBlock;
- }
-
- transition(MT, L1_PUTX, M) {
- ll_clearSharers;
- mr_writeDataToCacheFromRequest;
- t_sendWBAck;
- jj_popL1RequestQueue;
- }
-
- transition({SS_MB,MT_MB}, Exclusive_Unblock, MT) {
- // update actual directory
- mmu_markExclusiveFromUnblock;
- k_popUnblockQueue;
- kd_wakeUpDependents;
- }
-
- transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
- zz_stallAndWaitL1RequestQueue;
- }
-
- transition(MT_IIB, Unblock, MT_IB) {
- nnu_addSharerFromUnblock;
- k_popUnblockQueue;
- }
-
- transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
- m_writeDataToCache;
- o_popIncomingResponseQueue;
- }
-
- transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
- m_writeDataToCache;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(MT_SB, Unblock, SS) {
- nnu_addSharerFromUnblock;
- k_popUnblockQueue;
- kd_wakeUpDependents;
- }
-
- // writeback states
- transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
- zz_stallAndWaitL1RequestQueue;
- }
-
- transition(I_I, Ack) {
- q_updateAck;
- o_popIncomingResponseQueue;
- }
-
- transition(I_I, Ack_all, M_I) {
- c_exclusiveCleanReplacement;
- o_popIncomingResponseQueue;
- }
-
- transition({MT_I, MCT_I}, WB_Data, M_I) {
- qq_writeDataToTBE;
- ct_exclusiveReplacementFromTBE;
- o_popIncomingResponseQueue;
- }
-
- transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
- c_exclusiveCleanReplacement;
- o_popIncomingResponseQueue;
- }
-
- transition(MCT_I, {L1_PUTX, L1_PUTX_old}){
- zz_stallAndWaitL1RequestQueue;
- }
-
- // L1 never changed Dirty data
- transition(MT_I, {WB_Data_clean, Ack_all}, M_I) {
- ct_exclusiveReplacementFromTBE;
- o_popIncomingResponseQueue;
- }
-
- transition(MT_I, {L1_PUTX, L1_PUTX_old}){
- zz_stallAndWaitL1RequestQueue;
- }
-
- // possible race between unblock and immediate replacement
- transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
- zz_stallAndWaitL1RequestQueue;
- }
-
- transition(S_I, Ack) {
- q_updateAck;
- o_popIncomingResponseQueue;
- }
-
- transition(S_I, Ack_all, M_I) {
- ct_exclusiveReplacementFromTBE;
- o_popIncomingResponseQueue;
- }
-
- transition(M_I, Mem_Ack, NP) {
- s_deallocateTBE;
- o_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-}
+++ /dev/null
-/*
- * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00 mikem@royal16.cs.wisc.edu $
- */
-
-// This file is copied from Yasuko Watanabe's prefetch / memory protocol
-// Copied here by aep 12/14/07
-
-
-machine(Directory, "MESI_CMP_filter_directory protocol")
- : DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles to_mem_ctrl_latency = 1,
- Cycles directory_latency = 6,
-{
- MessageBuffer requestToDir, network="From", virtual_network="0",
- ordered="false", vnet_type="request";
- MessageBuffer responseToDir, network="From", virtual_network="1",
- ordered="false", vnet_type="response";
- MessageBuffer responseFromDir, network="To", virtual_network="1",
- ordered="false", vnet_type="response";
-
- // STATES
- state_declaration(State, desc="Directory states", default="Directory_State_I") {
- // Base states
- I, AccessPermission:Read_Write, desc="dir is the owner and memory is up-to-date, all other copies are Invalid";
- ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
- ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
-
- M, AccessPermission:Maybe_Stale, desc="memory copy may be stale, i.e. other modified copies may exist";
- IM, AccessPermission:Busy, desc="Intermediate State I>M";
- MI, AccessPermission:Busy, desc="Intermediate State M>I";
- M_DRD, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
- M_DRDI, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
- M_DWR, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
- M_DWRI, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
- }
-
- // Events
- enumeration(Event, desc="Directory events") {
- Fetch, desc="A memory fetch arrives";
- Data, desc="writeback data arrives";
- Memory_Data, desc="Fetched data from memory arrives";
- Memory_Ack, desc="Writeback Ack from memory arrives";
-//added by SS for dma
- DMA_READ, desc="A DMA Read memory request";
- DMA_WRITE, desc="A DMA Write memory request";
- CleanReplacement, desc="Clean Replacement in L2 cache";
-
- }
-
- // TYPES
-
- // DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
- State DirectoryState, desc="Directory state";
- DataBlock DataBlk, desc="data for the block";
- MachineID Owner;
- }
-
- // TBE entries for DMA requests
- structure(TBE, desc="TBE entries for outstanding DMA requests") {
- Address PhysicalAddress, desc="physical address";
- State TBEState, desc="Transient State";
- DataBlock DataBlk, desc="Data to be written (DMA write only)";
- int Len, desc="...";
- }
-
- structure(TBETable, external="yes") {
- TBE lookup(Address);
- void allocate(Address);
- void deallocate(Address);
- bool isPresent(Address);
- }
-
-
- // ** OBJECTS **
- TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
-
- void set_tbe(TBE tbe);
- void unset_tbe();
- void wakeUpBuffers(Address a);
-
- Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
- Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
-
- if (is_valid(dir_entry)) {
- return dir_entry;
- }
-
- dir_entry := static_cast(Entry, "pointer",
- directory.allocate(addr, new Entry));
- return dir_entry;
- }
-
- State getState(TBE tbe, Address addr) {
- if (is_valid(tbe)) {
- return tbe.TBEState;
- } else if (directory.isPresent(addr)) {
- return getDirectoryEntry(addr).DirectoryState;
- } else {
- return State:I;
- }
- }
-
- void setState(TBE tbe, Address addr, State state) {
- if (is_valid(tbe)) {
- tbe.TBEState := state;
- }
-
- if (directory.isPresent(addr)) {
- getDirectoryEntry(addr).DirectoryState := state;
- }
- }
-
- AccessPermission getAccessPermission(Address addr) {
- TBE tbe := TBEs[addr];
- if(is_valid(tbe)) {
- DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(tbe.TBEState));
- return Directory_State_to_permission(tbe.TBEState);
- }
-
- if(directory.isPresent(addr)) {
- DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
- return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
- }
-
- DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
- return AccessPermission:NotPresent;
- }
-
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
- TBE tbe := TBEs[addr];
- if(is_valid(tbe)) {
- return tbe.DataBlk;
- }
-
- return getDirectoryEntry(addr).DataBlk;
- }
-
- void setAccessPermission(Address addr, State state) {
- if (directory.isPresent(addr)) {
- getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
- }
- }
-
- bool isGETRequest(CoherenceRequestType type) {
- return (type == CoherenceRequestType:GETS) ||
- (type == CoherenceRequestType:GET_INSTR) ||
- (type == CoherenceRequestType:GETX);
- }
-
-
- // ** OUT_PORTS **
- out_port(responseNetwork_out, ResponseMsg, responseFromDir);
- out_port(memQueue_out, MemoryMsg, memBuffer);
-
- // ** IN_PORTS **
-
- in_port(requestNetwork_in, RequestMsg, requestToDir, rank = 0) {
- if (requestNetwork_in.isReady()) {
- peek(requestNetwork_in, RequestMsg) {
- assert(in_msg.Destination.isElement(machineID));
- if (isGETRequest(in_msg.Type)) {
- trigger(Event:Fetch, in_msg.Addr, TBEs[in_msg.Addr]);
- } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
- trigger(Event:DMA_READ, makeLineAddress(in_msg.Addr),
- TBEs[makeLineAddress(in_msg.Addr)]);
- } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
- trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Addr),
- TBEs[makeLineAddress(in_msg.Addr)]);
- } else {
- DPRINTF(RubySlicc, "%s\n", in_msg);
- error("Invalid message");
- }
- }
- }
- }
-
- in_port(responseNetwork_in, ResponseMsg, responseToDir, rank = 1) {
- if (responseNetwork_in.isReady()) {
- peek(responseNetwork_in, ResponseMsg) {
- assert(in_msg.Destination.isElement(machineID));
- if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
- trigger(Event:Data, in_msg.Addr, TBEs[in_msg.Addr]);
- } else if (in_msg.Type == CoherenceResponseType:ACK) {
- trigger(Event:CleanReplacement, in_msg.Addr, TBEs[in_msg.Addr]);
- } else {
- DPRINTF(RubySlicc, "%s\n", in_msg.Type);
- error("Invalid message");
- }
- }
- }
- }
-
- // off-chip memory request/response is done
- in_port(memQueue_in, MemoryMsg, memBuffer, rank = 2) {
- if (memQueue_in.isReady()) {
- peek(memQueue_in, MemoryMsg) {
- if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
- trigger(Event:Memory_Data, in_msg.Addr, TBEs[in_msg.Addr]);
- } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
- trigger(Event:Memory_Ack, in_msg.Addr, TBEs[in_msg.Addr]);
- } else {
- DPRINTF(RubySlicc, "%s\n", in_msg.Type);
- error("Invalid message");
- }
- }
- }
- }
-
-
- // Actions
- action(a_sendAck, "a", desc="Send ack to L2") {
- peek(responseNetwork_in, ResponseMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:MEMORY_ACK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.Sender);
- out_msg.MessageSize := MessageSizeType:Response_Control;
- }
- }
- }
-
- action(d_sendData, "d", desc="Send data to requestor") {
- peek(memQueue_in, MemoryMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:MEMORY_DATA;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.OriginalRequestorMachId);
- out_msg.DataBlk := in_msg.DataBlk;
- out_msg.Dirty := false;
- out_msg.MessageSize := MessageSizeType:Response_Data;
-
- Entry e := getDirectoryEntry(in_msg.Addr);
- e.Owner := in_msg.OriginalRequestorMachId;
- }
- }
- }
-
- // Actions
- action(aa_sendAck, "aa", desc="Send ack to L2") {
- peek(memQueue_in, MemoryMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:MEMORY_ACK;
- out_msg.Sender := machineID;
- out_msg.Destination.add(in_msg.OriginalRequestorMachId);
- out_msg.MessageSize := MessageSizeType:Response_Control;
- }
- }
- }
-
- action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
- requestNetwork_in.dequeue();
- }
-
- action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") {
- responseNetwork_in.dequeue();
- }
-
- action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
- memQueue_in.dequeue();
- }
-
- action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
- wakeUpBuffers(address);
- }
-
- action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
- peek(requestNetwork_in, RequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := MemoryRequestType:MEMORY_READ;
- out_msg.Sender := machineID;
- out_msg.OriginalRequestorMachId := in_msg.Requestor;
- out_msg.MessageSize := in_msg.MessageSize;
- out_msg.Prefetch := in_msg.Prefetch;
- out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
-
- DPRINTF(RubySlicc, "%s\n", out_msg);
- }
- }
- }
-
- action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
- peek(responseNetwork_in, ResponseMsg) {
- enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := MemoryRequestType:MEMORY_WB;
- out_msg.Sender := machineID;
- out_msg.OriginalRequestorMachId := in_msg.Sender;
- out_msg.DataBlk := in_msg.DataBlk;
- out_msg.MessageSize := in_msg.MessageSize;
- //out_msg.Prefetch := in_msg.Prefetch;
-
- DPRINTF(RubySlicc, "%s\n", out_msg);
- }
- }
- }
-
- action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
- peek(responseNetwork_in, ResponseMsg) {
- getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
- DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
- in_msg.Addr, in_msg.DataBlk);
- }
- }
-//added by SS for dma
- action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
- peek(requestNetwork_in, RequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := MemoryRequestType:MEMORY_READ;
- out_msg.Sender := machineID;
- out_msg.OriginalRequestorMachId := machineID;
- out_msg.MessageSize := in_msg.MessageSize;
- out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
- DPRINTF(RubySlicc, "%s\n", out_msg);
- }
- }
- }
-
- action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
- requestNetwork_in.dequeue();
- }
-
- action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
- peek(memQueue_in, MemoryMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
- out_msg.Destination.add(map_Address_to_DMA(address));
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
- }
-
- action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
- peek(requestNetwork_in, RequestMsg) {
- getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Addr), in_msg.Len);
- }
- }
-
- action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
- peek(requestNetwork_in, RequestMsg) {
- enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := MemoryRequestType:MEMORY_WB;
- out_msg.OriginalRequestorMachId := machineID;
- //out_msg.DataBlk := in_msg.DataBlk;
- out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(address), in_msg.Len);
-
-
- out_msg.MessageSize := in_msg.MessageSize;
- //out_msg.Prefetch := in_msg.Prefetch;
-
- DPRINTF(RubySlicc, "%s\n", out_msg);
- }
- }
- }
-
- action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
- enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:ACK;
- out_msg.Destination.add(map_Address_to_DMA(address));
- out_msg.MessageSize := MessageSizeType:Writeback_Control;
- }
- }
-
- action(z_stallAndWaitRequest, "z", desc="recycle request queue") {
- stall_and_wait(requestNetwork_in, address);
- }
-
- action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
- requestNetwork_in.recycle();
- }
-
- action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
- peek(requestNetwork_in, RequestMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:INV;
- out_msg.Sender := machineID;
- out_msg.Destination.add(getDirectoryEntry(address).Owner);
- out_msg.MessageSize := MessageSizeType:Response_Control;
- }
- }
- }
-
-
- action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
- peek(responseNetwork_in, ResponseMsg) {
- enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
- out_msg.Addr := address;
- out_msg.Type := CoherenceResponseType:DATA;
- out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
- out_msg.Destination.add(map_Address_to_DMA(address));
- out_msg.MessageSize := MessageSizeType:Response_Data;
- }
- }
- }
-
- action(v_allocateTBE, "v", desc="Allocate TBE") {
- peek(requestNetwork_in, RequestMsg) {
- TBEs.allocate(address);
- set_tbe(TBEs[address]);
- tbe.DataBlk := in_msg.DataBlk;
- tbe.PhysicalAddress := in_msg.Addr;
- tbe.Len := in_msg.Len;
- }
- }
-
- action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
- assert(is_valid(tbe));
- //getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
- getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
-
-
- }
-
-
- action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
- peek(responseNetwork_in, ResponseMsg) {
- enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
- assert(is_valid(tbe));
- out_msg.Addr := address;
- out_msg.Type := MemoryRequestType:MEMORY_WB;
- out_msg.OriginalRequestorMachId := in_msg.Sender;
- //out_msg.DataBlk := in_msg.DataBlk;
- //out_msg.DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
- out_msg.DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
-
- out_msg.MessageSize := in_msg.MessageSize;
- //out_msg.Prefetch := in_msg.Prefetch;
-
- DPRINTF(RubySlicc, "%s\n", out_msg);
- }
- }
- }
-
- action(w_deallocateTBE, "w", desc="Deallocate TBE") {
- TBEs.deallocate(address);
- unset_tbe();
- }
-
-
- // TRANSITIONS
-
- transition(I, Fetch, IM) {
- qf_queueMemoryFetchRequest;
- j_popIncomingRequestQueue;
- }
-
- transition(M, Fetch) {
- inv_sendCacheInvalidate;
- z_stallAndWaitRequest;
- }
-
- transition(IM, Memory_Data, M) {
- d_sendData;
- l_popMemQueue;
- kd_wakeUpDependents;
- }
-//added by SS
- transition(M, CleanReplacement, I) {
- a_sendAck;
- k_popIncomingResponseQueue;
- kd_wakeUpDependents;
- }
-
- transition(M, Data, MI) {
- m_writeDataToMemory;
- qw_queueMemoryWBRequest;
- k_popIncomingResponseQueue;
- }
-
- transition(MI, Memory_Ack, I) {
- aa_sendAck;
- l_popMemQueue;
- kd_wakeUpDependents;
- }
-
-
-//added by SS for dma support
- transition(I, DMA_READ, ID) {
- qf_queueMemoryFetchRequestDMA;
- j_popIncomingRequestQueue;
- }
-
- transition(ID, Memory_Data, I) {
- dr_sendDMAData;
- l_popMemQueue;
- kd_wakeUpDependents;
- }
-
- transition(I, DMA_WRITE, ID_W) {
- dw_writeDMAData;
- qw_queueMemoryWBRequest_partial;
- j_popIncomingRequestQueue;
- }
-
- transition(ID_W, Memory_Ack, I) {
- da_sendDMAAck;
- l_popMemQueue;
- kd_wakeUpDependents;
- }
-
- transition({ID, ID_W, M_DRDI, M_DWRI, IM, MI}, {Fetch, Data} ) {
- z_stallAndWaitRequest;
- }
-
- transition({ID, ID_W, M_DRD, M_DRDI, M_DWR, M_DWRI, IM, MI}, {DMA_WRITE, DMA_READ} ) {
- zz_recycleDMAQueue;
- }
-
-
- transition(M, DMA_READ, M_DRD) {
- inv_sendCacheInvalidate;
- j_popIncomingRequestQueue;
- }
-
- transition(M_DRD, Data, M_DRDI) {
- drp_sendDMAData;
- m_writeDataToMemory;
- qw_queueMemoryWBRequest;
- k_popIncomingResponseQueue;
- }
-
- transition(M_DRDI, Memory_Ack, I) {
- aa_sendAck;
- l_popMemQueue;
- kd_wakeUpDependents;
- }
-
- transition(M, DMA_WRITE, M_DWR) {
- v_allocateTBE;
- inv_sendCacheInvalidate;
- j_popIncomingRequestQueue;
- }
-
- transition(M_DWR, Data, M_DWRI) {
- m_writeDataToMemory;
- qw_queueMemoryWBRequest_partialTBE;
- k_popIncomingResponseQueue;
- }
-
- transition(M_DWRI, Memory_Ack, I) {
- dwt_writeDMADataFromTBE;
- aa_sendAck;
- da_sendDMAAck;
- w_deallocateTBE;
- l_popMemQueue;
- kd_wakeUpDependents;
- }
-}
+++ /dev/null
-/*
- * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
- * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
-{
-
- MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
- MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
-
- state_declaration(State, desc="DMA states", default="DMA_State_READY") {
- READY, AccessPermission:Invalid, desc="Ready to accept a new request";
- BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
- BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
- }
-
- enumeration(Event, desc="DMA events") {
- ReadRequest, desc="A new read request";
- WriteRequest, desc="A new write request";
- Data, desc="Data from a DMA memory read";
- Ack, desc="DMA write to memory completed";
- }
-
- structure(DMASequencer, external="yes") {
- void ackCallback();
- void dataCallback(DataBlock);
- }
-
- MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
- State cur_state, no_vector="true";
-
- State getState(Address addr) {
- return cur_state;
- }
- void setState(Address addr, State state) {
- cur_state := state;
- }
-
- AccessPermission getAccessPermission(Address addr) {
- return AccessPermission:NotPresent;
- }
-
- void setAccessPermission(Address addr, State state) {
- }
-
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
- error("DMA does not support get data block.");
- }
-
- out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
-
- in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
- if (dmaRequestQueue_in.isReady()) {
- peek(dmaRequestQueue_in, SequencerMsg) {
- if (in_msg.Type == SequencerRequestType:LD ) {
- trigger(Event:ReadRequest, in_msg.LineAddress);
- } else if (in_msg.Type == SequencerRequestType:ST) {
- trigger(Event:WriteRequest, in_msg.LineAddress);
- } else {
- error("Invalid request type");
- }
- }
- }
- }
-
- in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
- if (dmaResponseQueue_in.isReady()) {
- peek( dmaResponseQueue_in, ResponseMsg) {
- if (in_msg.Type == CoherenceResponseType:ACK) {
- trigger(Event:Ack, makeLineAddress(in_msg.Addr));
- } else if (in_msg.Type == CoherenceResponseType:DATA) {
- trigger(Event:Data, makeLineAddress(in_msg.Addr));
- } else {
- error("Invalid response type");
- }
- }
- }
- }
-
- action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
- peek(dmaRequestQueue_in, SequencerMsg) {
- enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
- out_msg.Addr := in_msg.PhysicalAddress;
- out_msg.Type := CoherenceRequestType:DMA_READ;
- out_msg.DataBlk := in_msg.DataBlk;
- out_msg.Len := in_msg.Len;
- out_msg.Destination.add(map_Address_to_Directory(address));
- out_msg.MessageSize := MessageSizeType:Writeback_Control;
- }
- }
- }
-
- action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
- peek(dmaRequestQueue_in, SequencerMsg) {
- enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
- out_msg.Addr := in_msg.PhysicalAddress;
- out_msg.Type := CoherenceRequestType:DMA_WRITE;
- out_msg.DataBlk := in_msg.DataBlk;
- out_msg.Len := in_msg.Len;
- out_msg.Destination.add(map_Address_to_Directory(address));
- out_msg.MessageSize := MessageSizeType:Writeback_Control;
- }
- }
- }
-
- action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
- dma_sequencer.ackCallback();
- }
-
- action(d_dataCallback, "d", desc="Write data to dma sequencer") {
- peek (dmaResponseQueue_in, ResponseMsg) {
- dma_sequencer.dataCallback(in_msg.DataBlk);
- }
- }
-
- action(p_popRequestQueue, "p", desc="Pop request queue") {
- dmaRequestQueue_in.dequeue();
- }
-
- action(p_popResponseQueue, "\p", desc="Pop request queue") {
- dmaResponseQueue_in.dequeue();
- }
-
- action(z_stall, "z", desc="dma is busy..stall") {
- // do nothing
- }
-
- transition(READY, ReadRequest, BUSY_RD) {
- s_sendReadRequest;
- p_popRequestQueue;
- }
-
- transition(READY, WriteRequest, BUSY_WR) {
- s_sendWriteRequest;
- p_popRequestQueue;
- }
-
- transition(BUSY_RD, Data, READY) {
- d_dataCallback;
- p_popResponseQueue;
- }
-
- transition(BUSY_WR, Ack, READY) {
- a_ackCallback;
- p_popResponseQueue;
- }
-}
+++ /dev/null
-
-/*
- * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-// CoherenceRequestType
-enumeration(CoherenceRequestType, desc="...") {
- GETX, desc="Get eXclusive";
- UPGRADE, desc="UPGRADE to exclusive";
- GETS, desc="Get Shared";
- GET_INSTR, desc="Get Instruction";
- INV, desc="INValidate";
- PUTX, desc="Replacement message";
-
- WB_ACK, desc="Writeback ack";
-
- DMA_READ, desc="DMA Read";
- DMA_WRITE, desc="DMA Write";
-}
-
-// CoherenceResponseType
-enumeration(CoherenceResponseType, desc="...") {
- MEMORY_ACK, desc="Ack from memory controller";
- DATA, desc="Data block for L1 cache in S state";
- DATA_EXCLUSIVE, desc="Data block for L1 cache in M/E state";
- MEMORY_DATA, desc="Data block from / to main memory";
- ACK, desc="Generic invalidate ack";
- WB_ACK, desc="writeback ack";
- UNBLOCK, desc="unblock";
- EXCLUSIVE_UNBLOCK, desc="exclusive unblock";
- INV, desc="Invalidate from directory";
-}
-
-// RequestMsg
-structure(RequestMsg, desc="...", interface="NetworkMessage") {
- Address Addr, desc="Physical address for this request";
- CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
- RubyAccessMode AccessMode, desc="user/supervisor access type";
- MachineID Requestor , desc="What component request";
- NetDest Destination, desc="What components receive the request, includes MachineType and num";
- MessageSizeType MessageSize, desc="size category of the message";
- DataBlock DataBlk, desc="Data for the cache line (if PUTX)";
- int Len;
- bool Dirty, default="false", desc="Dirty bit";
- PrefetchBit Prefetch, desc="Is this a prefetch request";
-
- bool functionalRead(Packet *pkt) {
- // Only PUTX messages contains the data block
- if (Type == CoherenceRequestType:PUTX) {
- return testAndRead(Addr, DataBlk, pkt);
- }
-
- return false;
- }
-
- bool functionalWrite(Packet *pkt) {
- // No check on message type required since the protocol should
- // read data from those messages that contain the block
- return testAndWrite(Addr, DataBlk, pkt);
- }
-}
-
-// ResponseMsg
-structure(ResponseMsg, desc="...", interface="NetworkMessage") {
- Address Addr, desc="Physical address for this request";
- CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
- MachineID Sender, desc="What component sent the data";
- NetDest Destination, desc="Node to whom the data is sent";
- DataBlock DataBlk, desc="Data for the cache line";
- bool Dirty, default="false", desc="Dirty bit";
- int AckCount, default="0", desc="number of acks in this message";
- MessageSizeType MessageSize, desc="size category of the message";
-
- bool functionalRead(Packet *pkt) {
- // Valid data block is only present in message with following types
- if (Type == CoherenceResponseType:DATA ||
- Type == CoherenceResponseType:DATA_EXCLUSIVE ||
- Type == CoherenceResponseType:MEMORY_DATA) {
-
- return testAndRead(Addr, DataBlk, pkt);
- }
-
- return false;
- }
-
- bool functionalWrite(Packet *pkt) {
- // No check on message type required since the protocol should
- // read data from those messages that contain the block
- return testAndWrite(Addr, DataBlk, pkt);
- }
-}
+++ /dev/null
-protocol "MESI_CMP_directory";
-include "RubySlicc_interfaces.slicc";
-include "MESI_CMP_directory-msg.sm";
-include "MESI_CMP_directory-L1cache.sm";
-include "MESI_CMP_directory-L2cache.sm";
-include "MESI_CMP_directory-dir.sm";
-include "MESI_CMP_directory-dma.sm";
--- /dev/null
+/*
+ * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+machine(L1Cache, "MESI Directory L1 Cache CMP")
+ : Sequencer * sequencer,
+ CacheMemory * L1Icache,
+ CacheMemory * L1Dcache,
+ Prefetcher * prefetcher = 'NULL',
+ int l2_select_num_bits,
+ Cycles l1_request_latency = 2,
+ Cycles l1_response_latency = 2,
+ Cycles to_l2_latency = 1,
+ bool send_evictions,
+ bool enable_prefetch = "False"
+{
+ // NODE L1 CACHE
+ // From this node's L1 cache TO the network
+ // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
+ MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false", vnet_type="request";
+ // a local L1 -> this L2 bank
+ MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false", vnet_type="response";
+ MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false", vnet_type="unblock";
+
+
+ // To this node's L1 cache FROM the network
+ // a L2 bank -> this L1
+ MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false", vnet_type="request";
+ // a L2 bank -> this L1
+ MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false", vnet_type="response";
+ // Request Buffer for prefetches
+ MessageBuffer optionalQueue, ordered="false";
+
+
+ // STATES
+ state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
+ // Base states
+ NP, AccessPermission:Invalid, desc="Not present in either cache";
+ I, AccessPermission:Invalid, desc="a L1 cache entry Idle";
+ S, AccessPermission:Read_Only, desc="a L1 cache entry Shared";
+ E, AccessPermission:Read_Only, desc="a L1 cache entry Exclusive";
+ M, AccessPermission:Read_Write, desc="a L1 cache entry Modified", format="!b";
+
+ // Transient States
+ IS, AccessPermission:Busy, desc="L1 idle, issued GETS, have not seen response yet";
+ IM, AccessPermission:Busy, desc="L1 idle, issued GETX, have not seen response yet";
+ SM, AccessPermission:Read_Only, desc="L1 idle, issued GETX, have not seen response yet";
+ IS_I, AccessPermission:Busy, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
+
+ M_I, AccessPermission:Busy, desc="L1 replacing, waiting for ACK";
+ SINK_WB_ACK, AccessPermission:Busy, desc="This is to sink WB_Acks from L2";
+
+ // Transient States in which block is being prefetched
+ PF_IS, AccessPermission:Busy, desc="Issued GETS, have not seen response yet";
+ PF_IM, AccessPermission:Busy, desc="Issued GETX, have not seen response yet";
+ PF_SM, AccessPermission:Busy, desc="Issued GETX, received data, waiting for acks";
+ PF_IS_I, AccessPermission:Busy, desc="Issued GETs, saw inv before data";
+ }
+
+ // EVENTS
+ enumeration(Event, desc="Cache events") {
+ // L1 events
+ Load, desc="Load request from the home processor";
+ Ifetch, desc="I-fetch request from the home processor";
+ Store, desc="Store request from the home processor";
+
+ Inv, desc="Invalidate request from L2 bank";
+
+ // internal generated request
+ L1_Replacement, desc="L1 Replacement", format="!r";
+
+ // other requests
+ Fwd_GETX, desc="GETX from other processor";
+ Fwd_GETS, desc="GETS from other processor";
+ Fwd_GET_INSTR, desc="GET_INSTR from other processor";
+
+ Data, desc="Data for processor";
+ Data_Exclusive, desc="Data for processor";
+ DataS_fromL1, desc="data for GETS request, need to unblock directory";
+ Data_all_Acks, desc="Data for processor, all acks";
+
+ Ack, desc="Ack for processor";
+ Ack_all, desc="Last ack for processor";
+
+ WB_Ack, desc="Ack for replacement";
+
+ PF_Load, desc="load request from prefetcher";
+ PF_Ifetch, desc="instruction fetch request from prefetcher";
+ PF_Store, desc="exclusive load request from prefetcher";
+ }
+
+ // TYPES
+
+ // CacheEntry
+ structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
+ State CacheState, desc="cache state";
+ DataBlock DataBlk, desc="data for the block";
+ bool Dirty, default="false", desc="data is dirty";
+ bool isPrefetch, desc="Set if this block was prefetched";
+ }
+
+ // TBE fields
+ structure(TBE, desc="...") {
+ Address Addr, desc="Physical address for this TBE";
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="Buffer for the data block";
+ bool Dirty, default="false", desc="data is dirty";
+ bool isPrefetch, desc="Set if this was caused by a prefetch";
+ int pendingAcks, default="0", desc="number of pending acks";
+ }
+
+ structure(TBETable, external="yes") {
+ TBE lookup(Address);
+ void allocate(Address);
+ void deallocate(Address);
+ bool isPresent(Address);
+ }
+
+ TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+
+ MessageBuffer mandatoryQueue, ordered="false";
+
+ int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
+
+ void set_cache_entry(AbstractCacheEntry a);
+ void unset_cache_entry();
+ void set_tbe(TBE a);
+ void unset_tbe();
+ void wakeUpBuffers(Address a);
+ void profileMsgDelay(int virtualNetworkType, Cycles c);
+
+ // inclusive cache returns L1 entries only
+ Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
+ if(is_valid(L1Dcache_entry)) {
+ return L1Dcache_entry;
+ }
+
+ Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
+ return L1Icache_entry;
+ }
+
+ Entry getL1DCacheEntry(Address addr), return_by_pointer="yes" {
+ Entry L1Dcache_entry := static_cast(Entry, "pointer", L1Dcache[addr]);
+ return L1Dcache_entry;
+ }
+
+ Entry getL1ICacheEntry(Address addr), return_by_pointer="yes" {
+ Entry L1Icache_entry := static_cast(Entry, "pointer", L1Icache[addr]);
+ return L1Icache_entry;
+ }
+
+ State getState(TBE tbe, Entry cache_entry, Address addr) {
+ assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
+
+ if(is_valid(tbe)) {
+ return tbe.TBEState;
+ } else if (is_valid(cache_entry)) {
+ return cache_entry.CacheState;
+ }
+ return State:NP;
+ }
+
+ void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ assert((L1Dcache.isTagPresent(addr) && L1Icache.isTagPresent(addr)) == false);
+
+ // MUST CHANGE
+ if(is_valid(tbe)) {
+ tbe.TBEState := state;
+ }
+
+ if (is_valid(cache_entry)) {
+ cache_entry.CacheState := state;
+ }
+ }
+
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := L1_TBEs[addr];
+ if(is_valid(tbe)) {
+ DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
+ return L1Cache_State_to_permission(tbe.TBEState);
+ }
+
+ Entry cache_entry := getCacheEntry(addr);
+ if(is_valid(cache_entry)) {
+ DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(cache_entry.CacheState));
+ return L1Cache_State_to_permission(cache_entry.CacheState);
+ }
+
+ DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
+ return AccessPermission:NotPresent;
+ }
+
+ DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := L1_TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
+ return getCacheEntry(addr).DataBlk;
+ }
+
+ void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ if (is_valid(cache_entry)) {
+ cache_entry.changePermission(L1Cache_State_to_permission(state));
+ }
+ }
+
+ Event mandatory_request_type_to_event(RubyRequestType type) {
+ if (type == RubyRequestType:LD) {
+ return Event:Load;
+ } else if (type == RubyRequestType:IFETCH) {
+ return Event:Ifetch;
+ } else if ((type == RubyRequestType:ST) || (type == RubyRequestType:ATOMIC)) {
+ return Event:Store;
+ } else {
+ error("Invalid RubyRequestType");
+ }
+ }
+
+ Event prefetch_request_type_to_event(RubyRequestType type) {
+ if (type == RubyRequestType:LD) {
+ return Event:PF_Load;
+ } else if (type == RubyRequestType:IFETCH) {
+ return Event:PF_Ifetch;
+ } else if ((type == RubyRequestType:ST) ||
+ (type == RubyRequestType:ATOMIC)) {
+ return Event:PF_Store;
+ } else {
+ error("Invalid RubyRequestType");
+ }
+ }
+
+ int getPendingAcks(TBE tbe) {
+ return tbe.pendingAcks;
+ }
+
+ out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
+ out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
+ out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
+ out_port(optionalQueue_out, RubyRequest, optionalQueue);
+
+
+ // Prefetch queue between the controller and the prefetcher
+ // As per Spracklen et al. (HPCA 2005), the prefetch queue should be
+ // implemented as a LIFO structure. The structure would allow for fast
+ // searches of all entries in the queue, not just the head msg. All
+ // msgs in the structure can be invalidated if a demand miss matches.
+ in_port(optionalQueue_in, RubyRequest, optionalQueue, desc="...", rank = 3) {
+ if (optionalQueue_in.isReady()) {
+ peek(optionalQueue_in, RubyRequest) {
+ // Instruction Prefetch
+ if (in_msg.Type == RubyRequestType:IFETCH) {
+ Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Icache_entry)) {
+ // The block to be prefetched is already present in the
+ // cache. We should drop this request.
+ trigger(prefetch_request_type_to_event(in_msg.Type),
+ in_msg.LineAddress,
+ L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+ }
+
+ // Check to see if it is in the OTHER L1
+ Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Dcache_entry)) {
+ // The block is in the wrong L1 cache. We should drop
+ // this request.
+ trigger(prefetch_request_type_to_event(in_msg.Type),
+ in_msg.LineAddress,
+ L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+ }
+
+ if (L1Icache.cacheAvail(in_msg.LineAddress)) {
+ // L1 does't have the line, but we have space for it
+ // in the L1 so let's see if the L2 has it
+ trigger(prefetch_request_type_to_event(in_msg.Type),
+ in_msg.LineAddress,
+ L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+ } else {
+ // No room in the L1, so we need to make room in the L1
+ trigger(Event:L1_Replacement,
+ L1Icache.cacheProbe(in_msg.LineAddress),
+ getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
+ L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
+ }
+ } else {
+ // Data prefetch
+ Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Dcache_entry)) {
+ // The block to be prefetched is already present in the
+ // cache. We should drop this request.
+ trigger(prefetch_request_type_to_event(in_msg.Type),
+ in_msg.LineAddress,
+ L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+ }
+
+ // Check to see if it is in the OTHER L1
+ Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Icache_entry)) {
+ // The block is in the wrong L1. Just drop the prefetch
+ // request.
+ trigger(prefetch_request_type_to_event(in_msg.Type),
+ in_msg.LineAddress,
+ L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+ }
+
+ if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
+ // L1 does't have the line, but we have space for it in
+ // the L1 let's see if the L2 has it
+ trigger(prefetch_request_type_to_event(in_msg.Type),
+ in_msg.LineAddress,
+ L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+ } else {
+ // No room in the L1, so we need to make room in the L1
+ trigger(Event:L1_Replacement,
+ L1Dcache.cacheProbe(in_msg.LineAddress),
+ getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
+ L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
+ }
+ }
+ }
+ }
+ }
+
+ // Response IntraChip L1 Network - response msg to this L1 cache
+ in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) {
+ if (responseIntraChipL1Network_in.isReady()) {
+ peek(responseIntraChipL1Network_in, ResponseMsg, block_on="Addr") {
+ assert(in_msg.Destination.isElement(machineID));
+
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L1_TBEs[in_msg.Addr];
+
+ if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
+ trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
+ } else if(in_msg.Type == CoherenceResponseType:DATA) {
+ if ((getState(tbe, cache_entry, in_msg.Addr) == State:IS ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:IS_I ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS ||
+ getState(tbe, cache_entry, in_msg.Addr) == State:PF_IS_I) &&
+ machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
+
+ trigger(Event:DataS_fromL1, in_msg.Addr, cache_entry, tbe);
+
+ } else if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
+ trigger(Event:Data_all_Acks, in_msg.Addr, cache_entry, tbe);
+ } else {
+ trigger(Event:Data, in_msg.Addr, cache_entry, tbe);
+ }
+ } else if (in_msg.Type == CoherenceResponseType:ACK) {
+ if ( (getPendingAcks(tbe) - in_msg.AckCount) == 0 ) {
+ trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
+ } else {
+ trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
+ }
+ } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
+ trigger(Event:WB_Ack, in_msg.Addr, cache_entry, tbe);
+ } else {
+ error("Invalid L1 response type");
+ }
+ }
+ }
+ }
+
+ // Request InterChip network - request from this L1 cache to the shared L2
+ in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache, rank = 1) {
+ if(requestIntraChipL1Network_in.isReady()) {
+ peek(requestIntraChipL1Network_in, RequestMsg, block_on="Addr") {
+ assert(in_msg.Destination.isElement(machineID));
+
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L1_TBEs[in_msg.Addr];
+
+ if (in_msg.Type == CoherenceRequestType:INV) {
+ trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
+ } else if (in_msg.Type == CoherenceRequestType:GETX ||
+ in_msg.Type == CoherenceRequestType:UPGRADE) {
+ // upgrade transforms to GETX due to race
+ trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe);
+ } else if (in_msg.Type == CoherenceRequestType:GETS) {
+ trigger(Event:Fwd_GETS, in_msg.Addr, cache_entry, tbe);
+ } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
+ trigger(Event:Fwd_GET_INSTR, in_msg.Addr, cache_entry, tbe);
+ } else {
+ error("Invalid forwarded request type");
+ }
+ }
+ }
+ }
+
+ // Mandatory Queue betweens Node's CPU and it's L1 caches
+ in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank = 0) {
+ if (mandatoryQueue_in.isReady()) {
+ peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") {
+
+ // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
+
+ if (in_msg.Type == RubyRequestType:IFETCH) {
+ // ** INSTRUCTION ACCESS ***
+
+ Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Icache_entry)) {
+ // The tag matches for the L1, so the L1 asks the L2 for it.
+ trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
+ L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+ } else {
+
+ // Check to see if it is in the OTHER L1
+ Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Dcache_entry)) {
+ // The block is in the wrong L1, put the request on the queue to the shared L2
+ trigger(Event:L1_Replacement, in_msg.LineAddress,
+ L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+ }
+
+ if (L1Icache.cacheAvail(in_msg.LineAddress)) {
+ // L1 does't have the line, but we have space for it
+ // in the L1 so let's see if the L2 has it.
+ trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
+ L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+ } else {
+ // No room in the L1, so we need to make room in the L1
+ trigger(Event:L1_Replacement, L1Icache.cacheProbe(in_msg.LineAddress),
+ getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
+ L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
+ }
+ }
+ } else {
+
+ // *** DATA ACCESS ***
+ Entry L1Dcache_entry := getL1DCacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Dcache_entry)) {
+ // The tag matches for the L1, so the L1 ask the L2 for it
+ trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
+ L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+ } else {
+
+ // Check to see if it is in the OTHER L1
+ Entry L1Icache_entry := getL1ICacheEntry(in_msg.LineAddress);
+ if (is_valid(L1Icache_entry)) {
+ // The block is in the wrong L1, put the request on the queue to the shared L2
+ trigger(Event:L1_Replacement, in_msg.LineAddress,
+ L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+ }
+
+ if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
+ // L1 does't have the line, but we have space for it
+ // in the L1 let's see if the L2 has it.
+ trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
+ L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+ } else {
+ // No room in the L1, so we need to make room in the L1
+ trigger(Event:L1_Replacement, L1Dcache.cacheProbe(in_msg.LineAddress),
+ getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
+ L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
+ }
+ }
+ }
+ }
+ }
+ }
+
+ void enqueuePrefetch(Address address, RubyRequestType type) {
+ enqueue(optionalQueue_out, RubyRequest, latency=1) {
+ out_msg.LineAddress := address;
+ out_msg.Type := type;
+ out_msg.AccessMode := RubyAccessMode:Supervisor;
+ }
+ }
+
+ // ACTIONS
+ action(a_issueGETS, "a", desc="Issue GETS") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:GETS;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
+ out_msg.MessageSize := MessageSizeType:Control;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.AccessMode := in_msg.AccessMode;
+ }
+ }
+ }
+
+ action(pa_issuePfGETS, "pa", desc="Issue prefetch GETS") {
+ peek(optionalQueue_in, RubyRequest) {
+ enqueue(requestIntraChipL1Network_out, RequestMsg,
+ latency=l1_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:GETS;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
+ out_msg.MessageSize := MessageSizeType:Control;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.AccessMode := in_msg.AccessMode;
+ }
+ }
+ }
+
+ action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:GET_INSTR;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
+ out_msg.MessageSize := MessageSizeType:Control;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.AccessMode := in_msg.AccessMode;
+ }
+ }
+ }
+
+ action(pai_issuePfGETINSTR, "pai",
+ desc="Issue GETINSTR for prefetch request") {
+ peek(optionalQueue_in, RubyRequest) {
+ enqueue(requestIntraChipL1Network_out, RequestMsg,
+ latency=l1_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:GET_INSTR;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(
+ mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ out_msg.MessageSize := MessageSizeType:Control;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.AccessMode := in_msg.AccessMode;
+
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
+ }
+ }
+ }
+
+ action(b_issueGETX, "b", desc="Issue GETX") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:GETX;
+ out_msg.Requestor := machineID;
+ DPRINTF(RubySlicc, "%s\n", machineID);
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
+ out_msg.MessageSize := MessageSizeType:Control;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.AccessMode := in_msg.AccessMode;
+ }
+ }
+ }
+
+ action(pb_issuePfGETX, "pb", desc="Issue prefetch GETX") {
+ peek(optionalQueue_in, RubyRequest) {
+ enqueue(requestIntraChipL1Network_out, RequestMsg,
+ latency=l1_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:GETX;
+ out_msg.Requestor := machineID;
+ DPRINTF(RubySlicc, "%s\n", machineID);
+
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
+ out_msg.MessageSize := MessageSizeType:Control;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.AccessMode := in_msg.AccessMode;
+ }
+ }
+ }
+
+ action(c_issueUPGRADE, "c", desc="Issue GETX") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ enqueue(requestIntraChipL1Network_out, RequestMsg, latency= l1_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:UPGRADE;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ DPRINTF(RubySlicc, "address: %s, destination: %s\n",
+ address, out_msg.Destination);
+ out_msg.MessageSize := MessageSizeType:Control;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.AccessMode := in_msg.AccessMode;
+ }
+ }
+ }
+
+ action(d_sendDataToRequestor, "d", desc="send data to requestor") {
+ peek(requestIntraChipL1Network_in, RequestMsg) {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.Dirty := cache_entry.Dirty;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+ }
+
+ action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.Dirty := cache_entry.Dirty;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+
+ action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
+ peek(requestIntraChipL1Network_in, RequestMsg) {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ assert(is_valid(tbe));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := tbe.DataBlk;
+ out_msg.Dirty := tbe.Dirty;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+ }
+
+ action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ assert(is_valid(tbe));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := tbe.DataBlk;
+ out_msg.Dirty := tbe.Dirty;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+
+ action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
+ peek(requestIntraChipL1Network_in, RequestMsg) {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:ACK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ }
+ }
+ }
+
+ action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.Dirty := cache_entry.Dirty;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ out_msg.MessageSize := MessageSizeType:Writeback_Data;
+ }
+ }
+
+ action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ assert(is_valid(tbe));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := tbe.DataBlk;
+ out_msg.Dirty := tbe.Dirty;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ out_msg.MessageSize := MessageSizeType:Writeback_Data;
+ }
+ }
+
+ action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
+ peek(requestIntraChipL1Network_in, RequestMsg) {
+ enqueue(responseIntraChipL1Network_out, ResponseMsg, latency=l1_response_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:ACK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ out_msg.AckCount := 1;
+ }
+ }
+ }
+
+ action(forward_eviction_to_cpu, "\cc", desc="sends eviction information to the processor") {
+ if (send_evictions) {
+ DPRINTF(RubySlicc, "Sending invalidation for %s to the CPU\n", address);
+ sequencer.evictionCallback(address);
+ }
+ }
+
+ action(g_issuePUTX, "g", desc="send data to the L2 cache") {
+ enqueue(requestIntraChipL1Network_out, RequestMsg, latency=l1_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:PUTX;
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.Dirty := cache_entry.Dirty;
+ out_msg.Requestor:= machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ if (cache_entry.Dirty) {
+ out_msg.MessageSize := MessageSizeType:Writeback_Data;
+ } else {
+ out_msg.MessageSize := MessageSizeType:Writeback_Control;
+ }
+ }
+ }
+
+ action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
+ enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:UNBLOCK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ DPRINTF(RubySlicc, "%s\n", address);
+ }
+ }
+
+ action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
+ enqueue(unblockNetwork_out, ResponseMsg, latency=to_l2_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache,
+ l2_select_low_bit, l2_select_num_bits, intToID(0)));
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ DPRINTF(RubySlicc, "%s\n", address);
+
+ }
+ }
+
+ action(dg_invalidate_sc, "dg",
+ desc="Invalidate store conditional as the cache lost permissions") {
+ sequencer.invalidateSC(address);
+ }
+
+ action(h_load_hit, "h",
+ desc="If not prefetch, notify sequencer the load completed.")
+ {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ sequencer.readCallback(address, cache_entry.DataBlk);
+ }
+
+ action(hx_load_hit, "hx",
+ desc="If not prefetch, notify sequencer the load completed.")
+ {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ sequencer.readCallback(address, cache_entry.DataBlk, true);
+ }
+
+ action(hh_store_hit, "\h",
+ desc="If not prefetch, notify sequencer that store completed.")
+ {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ sequencer.writeCallback(address, cache_entry.DataBlk);
+ cache_entry.Dirty := true;
+ }
+
+ action(hhx_store_hit, "\hx",
+ desc="If not prefetch, notify sequencer that store completed.")
+ {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
+ sequencer.writeCallback(address, cache_entry.DataBlk, true);
+ cache_entry.Dirty := true;
+ }
+
+ action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
+ check_allocate(L1_TBEs);
+ assert(is_valid(cache_entry));
+ L1_TBEs.allocate(address);
+ set_tbe(L1_TBEs[address]);
+ tbe.isPrefetch := false;
+ tbe.Dirty := cache_entry.Dirty;
+ tbe.DataBlk := cache_entry.DataBlk;
+ }
+
+ action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
+ mandatoryQueue_in.dequeue();
+ }
+
+ action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") {
+ profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles());
+ }
+
+ action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") {
+ profileMsgDelay(1, responseIntraChipL1Network_in.dequeue_getDelayCycles());
+ }
+
+ action(s_deallocateTBE, "s", desc="Deallocate TBE") {
+ L1_TBEs.deallocate(address);
+ unset_tbe();
+ }
+
+ action(u_writeDataToL1Cache, "u", desc="Write data to cache") {
+ peek(responseIntraChipL1Network_in, ResponseMsg) {
+ assert(is_valid(cache_entry));
+ cache_entry.DataBlk := in_msg.DataBlk;
+ cache_entry.Dirty := in_msg.Dirty;
+ }
+ }
+
+ action(q_updateAckCount, "q", desc="Update ack count") {
+ peek(responseIntraChipL1Network_in, ResponseMsg) {
+ assert(is_valid(tbe));
+ tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
+ APPEND_TRANSITION_COMMENT(in_msg.AckCount);
+ APPEND_TRANSITION_COMMENT(" p: ");
+ APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
+ }
+ }
+
+ action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
+ if (L1Dcache.isTagPresent(address)) {
+ L1Dcache.deallocate(address);
+ } else {
+ L1Icache.deallocate(address);
+ }
+ unset_cache_entry();
+ }
+
+ action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
+ if (is_invalid(cache_entry)) {
+ set_cache_entry(L1Dcache.allocate(address, new Entry));
+ }
+ }
+
+ action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
+ if (is_invalid(cache_entry)) {
+ set_cache_entry(L1Icache.allocate(address, new Entry));
+ }
+ }
+
+ action(z_stallAndWaitMandatoryQueue, "\z", desc="recycle L1 request queue") {
+ stall_and_wait(mandatoryQueue_in, address);
+ }
+
+ action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
+ wakeUpBuffers(address);
+ }
+
+ action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") {
+ ++L1Icache.demand_misses;
+ }
+
+ action(uu_profileInstHit, "\uih", desc="Profile the demand hit") {
+ ++L1Icache.demand_hits;
+ }
+
+ action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") {
+ ++L1Dcache.demand_misses;
+ }
+
+ action(uu_profileDataHit, "\udh", desc="Profile the demand hit") {
+ ++L1Dcache.demand_hits;
+ }
+
+ action(po_observeMiss, "\po", desc="Inform the prefetcher about the miss") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ if (enable_prefetch) {
+ prefetcher.observeMiss(in_msg.LineAddress, in_msg.Type);
+ }
+ }
+ }
+
+ action(ppm_observePfMiss, "\ppm",
+ desc="Inform the prefetcher about the partial miss") {
+ peek(mandatoryQueue_in, RubyRequest) {
+ prefetcher.observePfMiss(in_msg.LineAddress);
+ }
+ }
+
+ action(pq_popPrefetchQueue, "\pq", desc="Pop the prefetch request queue") {
+ optionalQueue_in.dequeue();
+ }
+
+ action(mp_markPrefetched, "mp", desc="Write data from response queue to cache") {
+ assert(is_valid(cache_entry));
+ cache_entry.isPrefetch := true;
+ }
+
+
+ //*****************************************************
+ // TRANSITIONS
+ //*****************************************************
+
+ // Transitions for Load/Store/Replacement/WriteBack from transient states
+ transition({IS, IM, IS_I, M_I, SM, SINK_WB_ACK}, {Load, Ifetch, Store, L1_Replacement}) {
+ z_stallAndWaitMandatoryQueue;
+ }
+
+ transition({PF_IS, PF_IS_I}, {Store, L1_Replacement}) {
+ z_stallAndWaitMandatoryQueue;
+ }
+
+ transition({PF_IM, PF_SM}, {Load, Ifetch, L1_Replacement}) {
+ z_stallAndWaitMandatoryQueue;
+ }
+
+ // Transitions from Idle
+ transition({NP,I}, L1_Replacement) {
+ ff_deallocateL1CacheBlock;
+ }
+
+ transition({S,E,M,IS,IM,SM,IS_I,M_I,SINK_WB_ACK,PF_IS,PF_IM},
+ {PF_Load, PF_Store, PF_Ifetch}) {
+ pq_popPrefetchQueue;
+ }
+
+ transition({NP,I}, Load, IS) {
+ oo_allocateL1DCacheBlock;
+ i_allocateTBE;
+ a_issueGETS;
+ uu_profileDataMiss;
+ po_observeMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition({NP,I}, PF_Load, PF_IS) {
+ oo_allocateL1DCacheBlock;
+ i_allocateTBE;
+ pa_issuePfGETS;
+ pq_popPrefetchQueue;
+ }
+
+ transition(PF_IS, Load, IS) {
+ uu_profileDataMiss;
+ ppm_observePfMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition(PF_IS_I, Load, IS_I) {
+ uu_profileDataMiss;
+ ppm_observePfMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition({NP,I}, Ifetch, IS) {
+ pp_allocateL1ICacheBlock;
+ i_allocateTBE;
+ ai_issueGETINSTR;
+ uu_profileInstMiss;
+ po_observeMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition({NP,I}, PF_Ifetch, PF_IS) {
+ pp_allocateL1ICacheBlock;
+ i_allocateTBE;
+ pai_issuePfGETINSTR;
+ pq_popPrefetchQueue;
+ }
+
+ // We proactively assume that the prefetch is in to
+ // the instruction cache
+ transition(PF_IS, Ifetch, IS) {
+ uu_profileDataMiss;
+ ppm_observePfMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition({NP,I}, Store, IM) {
+ oo_allocateL1DCacheBlock;
+ i_allocateTBE;
+ b_issueGETX;
+ uu_profileDataMiss;
+ po_observeMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition({NP,I}, PF_Store, PF_IM) {
+ oo_allocateL1DCacheBlock;
+ i_allocateTBE;
+ pb_issuePfGETX;
+ pq_popPrefetchQueue;
+ }
+
+ transition(PF_IM, Store, IM) {
+ uu_profileDataMiss;
+ ppm_observePfMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition(PF_SM, Store, SM) {
+ uu_profileDataMiss;
+ ppm_observePfMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition({NP, I}, Inv) {
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ // Transitions from Shared
+ transition({S,E,M}, Load) {
+ h_load_hit;
+ uu_profileDataHit;
+ k_popMandatoryQueue;
+ }
+
+ transition({S,E,M}, Ifetch) {
+ h_load_hit;
+ uu_profileInstHit;
+ k_popMandatoryQueue;
+ }
+
+ transition(S, Store, SM) {
+ i_allocateTBE;
+ c_issueUPGRADE;
+ uu_profileDataMiss;
+ k_popMandatoryQueue;
+ }
+
+ transition(S, L1_Replacement, I) {
+ forward_eviction_to_cpu;
+ ff_deallocateL1CacheBlock;
+ }
+
+ transition(S, Inv, I) {
+ forward_eviction_to_cpu;
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ // Transitions from Exclusive
+
+ transition({E,M}, Store, M) {
+ hh_store_hit;
+ uu_profileDataHit;
+ k_popMandatoryQueue;
+ }
+
+ transition(E, L1_Replacement, M_I) {
+ // silent E replacement??
+ forward_eviction_to_cpu;
+ i_allocateTBE;
+ g_issuePUTX; // send data, but hold in case forwarded request
+ ff_deallocateL1CacheBlock;
+ }
+
+ transition(E, Inv, I) {
+ // don't send data
+ forward_eviction_to_cpu;
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ transition(E, Fwd_GETX, I) {
+ forward_eviction_to_cpu;
+ d_sendDataToRequestor;
+ l_popRequestQueue;
+ }
+
+ transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
+ d_sendDataToRequestor;
+ d2_sendDataToL2;
+ l_popRequestQueue;
+ }
+
+ // Transitions from Modified
+
+ transition(M, L1_Replacement, M_I) {
+ forward_eviction_to_cpu;
+ i_allocateTBE;
+ g_issuePUTX; // send data, but hold in case forwarded request
+ ff_deallocateL1CacheBlock;
+ }
+
+ transition(M_I, WB_Ack, I) {
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(M, Inv, I) {
+ forward_eviction_to_cpu;
+ f_sendDataToL2;
+ l_popRequestQueue;
+ }
+
+ transition(M_I, Inv, SINK_WB_ACK) {
+ ft_sendDataToL2_fromTBE;
+ l_popRequestQueue;
+ }
+
+ transition(M, Fwd_GETX, I) {
+ forward_eviction_to_cpu;
+ d_sendDataToRequestor;
+ l_popRequestQueue;
+ }
+
+ transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
+ d_sendDataToRequestor;
+ d2_sendDataToL2;
+ l_popRequestQueue;
+ }
+
+ transition(M_I, Fwd_GETX, SINK_WB_ACK) {
+ dt_sendDataToRequestor_fromTBE;
+ l_popRequestQueue;
+ }
+
+ transition(M_I, {Fwd_GETS, Fwd_GET_INSTR}, SINK_WB_ACK) {
+ dt_sendDataToRequestor_fromTBE;
+ d2t_sendDataToL2_fromTBE;
+ l_popRequestQueue;
+ }
+
+ // Transitions from IS
+ transition({IS, IS_I}, Inv, IS_I) {
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ transition({PF_IS, PF_IS_I}, Inv, PF_IS_I) {
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ transition(IS, Data_all_Acks, S) {
+ u_writeDataToL1Cache;
+ hx_load_hit;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(PF_IS, Data_all_Acks, S) {
+ u_writeDataToL1Cache;
+ s_deallocateTBE;
+ mp_markPrefetched;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(IS_I, Data_all_Acks, I) {
+ u_writeDataToL1Cache;
+ hx_load_hit;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(PF_IS_I, Data_all_Acks, I) {
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(IS, DataS_fromL1, S) {
+ u_writeDataToL1Cache;
+ j_sendUnblock;
+ hx_load_hit;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(PF_IS, DataS_fromL1, S) {
+ u_writeDataToL1Cache;
+ j_sendUnblock;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(IS_I, DataS_fromL1, I) {
+ u_writeDataToL1Cache;
+ j_sendUnblock;
+ hx_load_hit;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(PF_IS_I, DataS_fromL1, I) {
+ j_sendUnblock;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ // directory is blocked when sending exclusive data
+ transition(IS_I, Data_Exclusive, E) {
+ u_writeDataToL1Cache;
+ hx_load_hit;
+ jj_sendExclusiveUnblock;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ // directory is blocked when sending exclusive data
+ transition(PF_IS_I, Data_Exclusive, E) {
+ u_writeDataToL1Cache;
+ jj_sendExclusiveUnblock;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(IS, Data_Exclusive, E) {
+ u_writeDataToL1Cache;
+ hx_load_hit;
+ jj_sendExclusiveUnblock;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(PF_IS, Data_Exclusive, E) {
+ u_writeDataToL1Cache;
+ jj_sendExclusiveUnblock;
+ s_deallocateTBE;
+ mp_markPrefetched;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ // Transitions from IM
+ transition(IM, Inv, IM) {
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ transition({PF_IM, PF_SM}, Inv, PF_IM) {
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ transition(IM, Data, SM) {
+ u_writeDataToL1Cache;
+ q_updateAckCount;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(PF_IM, Data, PF_SM) {
+ u_writeDataToL1Cache;
+ q_updateAckCount;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(IM, Data_all_Acks, M) {
+ u_writeDataToL1Cache;
+ hhx_store_hit;
+ jj_sendExclusiveUnblock;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(PF_IM, Data_all_Acks, M) {
+ u_writeDataToL1Cache;
+ jj_sendExclusiveUnblock;
+ s_deallocateTBE;
+ mp_markPrefetched;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ // transitions from SM
+ transition(SM, Inv, IM) {
+ fi_sendInvAck;
+ dg_invalidate_sc;
+ l_popRequestQueue;
+ }
+
+ transition({SM, IM, PF_SM, PF_IM}, Ack) {
+ q_updateAckCount;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(SM, Ack_all, M) {
+ jj_sendExclusiveUnblock;
+ hhx_store_hit;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(PF_SM, Ack_all, M) {
+ jj_sendExclusiveUnblock;
+ s_deallocateTBE;
+ mp_markPrefetched;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(SINK_WB_ACK, Inv){
+ fi_sendInvAck;
+ l_popRequestQueue;
+ }
+
+ transition(SINK_WB_ACK, WB_Ack, I){
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+}
--- /dev/null
+/*
+ * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $Id: MSI_MOSI_CMP_directory-L2cache.sm 1.12 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
+ *
+ */
+
+machine(L2Cache, "MESI Directory L2 Cache CMP")
+ : CacheMemory * L2cache,
+ Cycles l2_request_latency = 2,
+ Cycles l2_response_latency = 2,
+ Cycles to_l1_latency = 1
+{
+ // L2 BANK QUEUES
+ // From local bank of L2 cache TO the network
+ MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0",
+ ordered="false", vnet_type="request"; // this L2 bank -> Memory
+ MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0",
+ ordered="false", vnet_type="request"; // this L2 bank -> a local L1
+ MessageBuffer responseFromL2Cache, network="To", virtual_network="1",
+ ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || Memory
+
+ // FROM the network to this local bank of L2 cache
+ MessageBuffer unblockToL2Cache, network="From", virtual_network="2",
+ ordered="false", vnet_type="unblock"; // a local L1 || Memory -> this L2 bank
+ MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0",
+ ordered="false", vnet_type="request"; // a local L1 -> this L2 bank
+ MessageBuffer responseToL2Cache, network="From", virtual_network="1",
+ ordered="false", vnet_type="response"; // a local L1 || Memory -> this L2 bank
+
+ // STATES
+ state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") {
+ // Base states
+ NP, AccessPermission:Invalid, desc="Not present in either cache";
+ SS, AccessPermission:Read_Only, desc="L2 cache entry Shared, also present in one or more L1s";
+ M, AccessPermission:Read_Write, desc="L2 cache entry Modified, not present in any L1s", format="!b";
+ MT, AccessPermission:Maybe_Stale, desc="L2 cache entry Modified in a local L1, assume L2 copy stale", format="!b";
+
+ // L2 replacement
+ M_I, AccessPermission:Busy, desc="L2 cache replacing, have all acks, sent dirty data to memory, waiting for ACK from memory";
+ MT_I, AccessPermission:Busy, desc="L2 cache replacing, getting data from exclusive";
+ MCT_I, AccessPermission:Busy, desc="L2 cache replacing, clean in L2, getting data or ack from exclusive";
+ I_I, AccessPermission:Busy, desc="L2 replacing clean data, need to inv sharers and then drop data";
+ S_I, AccessPermission:Busy, desc="L2 replacing dirty data, collecting acks from L1s";
+
+ // Transient States for fetching data from memory
+ ISS, AccessPermission:Busy, desc="L2 idle, got single L1_GETS, issued memory fetch, have not seen response yet";
+ IS, AccessPermission:Busy, desc="L2 idle, got L1_GET_INSTR or multiple L1_GETS, issued memory fetch, have not seen response yet";
+ IM, AccessPermission:Busy, desc="L2 idle, got L1_GETX, issued memory fetch, have not seen response(s) yet";
+
+ // Blocking states
+ SS_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from SS";
+ MT_MB, AccessPermission:Busy, desc="Blocked for L1_GETX from MT";
+
+ MT_IIB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, waiting for unblock and data";
+ MT_IB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got unblock, waiting for data";
+ MT_SB, AccessPermission:Busy, desc="Blocked for L1_GETS from MT, got data, waiting for unblock";
+
+ }
+
+ // EVENTS
+ enumeration(Event, desc="L2 Cache events") {
+ // L2 events
+
+ // events initiated by the local L1s
+ L1_GET_INSTR, desc="a L1I GET INSTR request for a block maped to us";
+ L1_GETS, desc="a L1D GETS request for a block maped to us";
+ L1_GETX, desc="a L1D GETX request for a block maped to us";
+ L1_UPGRADE, desc="a L1D GETX request for a block maped to us";
+
+ L1_PUTX, desc="L1 replacing data";
+ L1_PUTX_old, desc="L1 replacing data, but no longer sharer";
+
+ // events initiated by this L2
+ L2_Replacement, desc="L2 Replacement", format="!r";
+ L2_Replacement_clean, desc="L2 Replacement, but data is clean", format="!r";
+
+ // events from memory controller
+ Mem_Data, desc="data from memory", format="!r";
+ Mem_Ack, desc="ack from memory", format="!r";
+
+ // M->S data writeback
+ WB_Data, desc="data from L1";
+ WB_Data_clean, desc="clean data from L1";
+ Ack, desc="writeback ack";
+ Ack_all, desc="writeback ack";
+
+ Unblock, desc="Unblock from L1 requestor";
+ Exclusive_Unblock, desc="Unblock from L1 requestor";
+
+ MEM_Inv, desc="Invalidation from directory";
+ }
+
+ // TYPES
+
+ // CacheEntry
+ structure(Entry, desc="...", interface="AbstractCacheEntry") {
+ State CacheState, desc="cache state";
+ NetDest Sharers, desc="tracks the L1 shares on-chip";
+ MachineID Exclusive, desc="Exclusive holder of block";
+ DataBlock DataBlk, desc="data for the block";
+ bool Dirty, default="false", desc="data is dirty";
+ }
+
+ // TBE fields
+ structure(TBE, desc="...") {
+ Address Addr, desc="Physical address for this TBE";
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="Buffer for the data block";
+ bool Dirty, default="false", desc="Data is Dirty";
+
+ NetDest L1_GetS_IDs, desc="Set of the internal processors that want the block in shared state";
+ MachineID L1_GetX_ID, desc="ID of the L1 cache to forward the block to once we get a response";
+ int pendingAcks, desc="number of pending acks for invalidates during writeback";
+ }
+
+ structure(TBETable, external="yes") {
+ TBE lookup(Address);
+ void allocate(Address);
+ void deallocate(Address);
+ bool isPresent(Address);
+ }
+
+ TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+
+ void set_cache_entry(AbstractCacheEntry a);
+ void unset_cache_entry();
+ void set_tbe(TBE a);
+ void unset_tbe();
+ void wakeUpBuffers(Address a);
+ void profileMsgDelay(int virtualNetworkType, Cycles c);
+
+ // inclusive cache, returns L2 entries only
+ Entry getCacheEntry(Address addr), return_by_pointer="yes" {
+ return static_cast(Entry, "pointer", L2cache[addr]);
+ }
+
+ bool isSharer(Address addr, MachineID requestor, Entry cache_entry) {
+ if (is_valid(cache_entry)) {
+ return cache_entry.Sharers.isElement(requestor);
+ } else {
+ return false;
+ }
+ }
+
+ void addSharer(Address addr, MachineID requestor, Entry cache_entry) {
+ assert(is_valid(cache_entry));
+ DPRINTF(RubySlicc, "machineID: %s, requestor: %s, address: %s\n",
+ machineID, requestor, addr);
+ cache_entry.Sharers.add(requestor);
+ }
+
+ State getState(TBE tbe, Entry cache_entry, Address addr) {
+ if(is_valid(tbe)) {
+ return tbe.TBEState;
+ } else if (is_valid(cache_entry)) {
+ return cache_entry.CacheState;
+ }
+ return State:NP;
+ }
+
+ void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+ // MUST CHANGE
+ if (is_valid(tbe)) {
+ tbe.TBEState := state;
+ }
+
+ if (is_valid(cache_entry)) {
+ cache_entry.CacheState := state;
+ }
+ }
+
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := L2_TBEs[addr];
+ if(is_valid(tbe)) {
+ DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
+ return L2Cache_State_to_permission(tbe.TBEState);
+ }
+
+ Entry cache_entry := getCacheEntry(addr);
+ if(is_valid(cache_entry)) {
+ DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(cache_entry.CacheState));
+ return L2Cache_State_to_permission(cache_entry.CacheState);
+ }
+
+ DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
+ return AccessPermission:NotPresent;
+ }
+
+ DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := L2_TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
+ return getCacheEntry(addr).DataBlk;
+ }
+
+ void setAccessPermission(Entry cache_entry, Address addr, State state) {
+ if (is_valid(cache_entry)) {
+ cache_entry.changePermission(L2Cache_State_to_permission(state));
+ }
+ }
+
+ Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
+ MachineID requestor, Entry cache_entry) {
+ if(type == CoherenceRequestType:GETS) {
+ return Event:L1_GETS;
+ } else if(type == CoherenceRequestType:GET_INSTR) {
+ return Event:L1_GET_INSTR;
+ } else if (type == CoherenceRequestType:GETX) {
+ return Event:L1_GETX;
+ } else if (type == CoherenceRequestType:UPGRADE) {
+ if ( is_valid(cache_entry) && cache_entry.Sharers.isElement(requestor) ) {
+ return Event:L1_UPGRADE;
+ } else {
+ return Event:L1_GETX;
+ }
+ } else if (type == CoherenceRequestType:PUTX) {
+ if (isSharer(addr, requestor, cache_entry)) {
+ return Event:L1_PUTX;
+ } else {
+ return Event:L1_PUTX_old;
+ }
+ } else {
+ DPRINTF(RubySlicc, "address: %s, Request Type: %s\n", addr, type);
+ error("Invalid L1 forwarded request type");
+ }
+ }
+
+ int getPendingAcks(TBE tbe) {
+ return tbe.pendingAcks;
+ }
+
+ bool isDirty(Entry cache_entry) {
+ assert(is_valid(cache_entry));
+ return cache_entry.Dirty;
+ }
+
+ // ** OUT_PORTS **
+
+ out_port(L1RequestIntraChipL2Network_out, RequestMsg, L1RequestFromL2Cache);
+ out_port(DirRequestIntraChipL2Network_out, RequestMsg, DirRequestFromL2Cache);
+ out_port(responseIntraChipL2Network_out, ResponseMsg, responseFromL2Cache);
+
+
+ in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) {
+ if(L1unblockNetwork_in.isReady()) {
+ peek(L1unblockNetwork_in, ResponseMsg) {
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L2_TBEs[in_msg.Addr];
+ DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
+ in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
+ in_msg.Sender, in_msg.Type, in_msg.Destination);
+
+ assert(in_msg.Destination.isElement(machineID));
+ if (in_msg.Type == CoherenceResponseType:EXCLUSIVE_UNBLOCK) {
+ trigger(Event:Exclusive_Unblock, in_msg.Addr, cache_entry, tbe);
+ } else if (in_msg.Type == CoherenceResponseType:UNBLOCK) {
+ trigger(Event:Unblock, in_msg.Addr, cache_entry, tbe);
+ } else {
+ error("unknown unblock message");
+ }
+ }
+ }
+ }
+
+ // Response IntraChip L2 Network - response msg to this particular L2 bank
+ in_port(responseIntraChipL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) {
+ if (responseIntraChipL2Network_in.isReady()) {
+ peek(responseIntraChipL2Network_in, ResponseMsg) {
+ // test wether it's from a local L1 or an off chip source
+ assert(in_msg.Destination.isElement(machineID));
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L2_TBEs[in_msg.Addr];
+
+ if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
+ if(in_msg.Type == CoherenceResponseType:DATA) {
+ if (in_msg.Dirty) {
+ trigger(Event:WB_Data, in_msg.Addr, cache_entry, tbe);
+ } else {
+ trigger(Event:WB_Data_clean, in_msg.Addr, cache_entry, tbe);
+ }
+ } else if (in_msg.Type == CoherenceResponseType:ACK) {
+ if ((getPendingAcks(tbe) - in_msg.AckCount) == 0) {
+ trigger(Event:Ack_all, in_msg.Addr, cache_entry, tbe);
+ } else {
+ trigger(Event:Ack, in_msg.Addr, cache_entry, tbe);
+ }
+ } else {
+ error("unknown message type");
+ }
+
+ } else { // external message
+ if(in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
+ trigger(Event:Mem_Data, in_msg.Addr, cache_entry, tbe);
+ } else if(in_msg.Type == CoherenceResponseType:MEMORY_ACK) {
+ trigger(Event:Mem_Ack, in_msg.Addr, cache_entry, tbe);
+ } else if(in_msg.Type == CoherenceResponseType:INV) {
+ trigger(Event:MEM_Inv, in_msg.Addr, cache_entry, tbe);
+ } else {
+ error("unknown message type");
+ }
+ }
+ }
+ } // if not ready, do nothing
+ }
+
+ // L1 Request
+ in_port(L1RequestIntraChipL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) {
+ if(L1RequestIntraChipL2Network_in.isReady()) {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ Entry cache_entry := getCacheEntry(in_msg.Addr);
+ TBE tbe := L2_TBEs[in_msg.Addr];
+
+ DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
+ in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
+ in_msg.Requestor, in_msg.Type, in_msg.Destination);
+
+ assert(machineIDToMachineType(in_msg.Requestor) == MachineType:L1Cache);
+ assert(in_msg.Destination.isElement(machineID));
+
+ if (is_valid(cache_entry)) {
+ // The L2 contains the block, so proceeded with handling the request
+ trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
+ in_msg.Requestor, cache_entry),
+ in_msg.Addr, cache_entry, tbe);
+ } else {
+ if (L2cache.cacheAvail(in_msg.Addr)) {
+ // L2 does't have the line, but we have space for it in the L2
+ trigger(L1Cache_request_type_to_event(in_msg.Type, in_msg.Addr,
+ in_msg.Requestor, cache_entry),
+ in_msg.Addr, cache_entry, tbe);
+ } else {
+ // No room in the L2, so we need to make room before handling the request
+ Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr));
+ if (isDirty(L2cache_entry)) {
+ trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
+ L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
+ } else {
+ trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr),
+ L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
+ }
+ }
+ }
+ }
+ }
+ }
+
+
+ // ACTIONS
+
+ action(a_issueFetchToMemory, "a", desc="fetch data from memory") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(DirRequestIntraChipL2Network_out, RequestMsg, latency=l2_request_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:GETS;
+ out_msg.Requestor := machineID;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.MessageSize := MessageSizeType:Control;
+ }
+ }
+ }
+
+ action(b_forwardRequestToExclusive, "b", desc="Forward request to the exclusive L1") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := in_msg.Type;
+ out_msg.Requestor := in_msg.Requestor;
+ out_msg.Destination.add(cache_entry.Exclusive);
+ out_msg.MessageSize := MessageSizeType:Request_Control;
+ }
+ }
+ }
+
+ action(c_exclusiveReplacement, "c", desc="Send data to memory") {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:MEMORY_DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.Dirty := cache_entry.Dirty;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+
+ action(c_exclusiveCleanReplacement, "cc", desc="Send ack to memory for clean replacement") {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:ACK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ }
+ }
+
+ action(ct_exclusiveReplacementFromTBE, "ct", desc="Send data to memory") {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ assert(is_valid(tbe));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:MEMORY_DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.DataBlk := tbe.DataBlk;
+ out_msg.Dirty := tbe.Dirty;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+
+ action(d_sendDataToRequestor, "d", desc="Send data from cache to reqeustor") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+
+ out_msg.AckCount := 0 - cache_entry.Sharers.count();
+ if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
+ out_msg.AckCount := out_msg.AckCount + 1;
+ }
+ }
+ }
+ }
+
+ action(dd_sendExclusiveDataToRequestor, "dd", desc="Send data from cache to reqeustor") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+
+ out_msg.AckCount := 0 - cache_entry.Sharers.count();
+ if (cache_entry.Sharers.isElement(in_msg.Requestor)) {
+ out_msg.AckCount := out_msg.AckCount + 1;
+ }
+ }
+ }
+ }
+
+ action(ds_sendSharedDataToRequestor, "ds", desc="Send data from cache to reqeustor") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=l2_response_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ out_msg.AckCount := 0;
+ }
+ }
+ }
+
+ action(e_sendDataToGetSRequestors, "e", desc="Send data from cache to all GetS IDs") {
+ assert(is_valid(tbe));
+ assert(tbe.L1_GetS_IDs.count() > 0);
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+
+ action(ex_sendExclusiveDataToGetSRequestors, "ex", desc="Send data from cache to all GetS IDs") {
+ assert(is_valid(tbe));
+ assert(tbe.L1_GetS_IDs.count() == 1);
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE;
+ out_msg.Sender := machineID;
+ out_msg.Destination := tbe.L1_GetS_IDs; // internal nodes
+ out_msg.DataBlk := cache_entry.DataBlk;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+
+ action(ee_sendDataToGetXRequestor, "ee", desc="Send data from cache to GetX ID") {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ assert(is_valid(tbe));
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(tbe.L1_GetX_ID);
+ DPRINTF(RubySlicc, "%s\n", out_msg.Destination);
+ out_msg.DataBlk := cache_entry.DataBlk;
+ DPRINTF(RubySlicc, "Address: %s, Destination: %s, DataBlock: %s\n",
+ out_msg.Addr, out_msg.Destination, out_msg.DataBlk);
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+
+ action(f_sendInvToSharers, "f", desc="invalidate sharers for L2 replacement") {
+ enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:INV;
+ out_msg.Requestor := machineID;
+ out_msg.Destination := cache_entry.Sharers;
+ out_msg.MessageSize := MessageSizeType:Request_Control;
+ }
+ }
+
+ action(fw_sendFwdInvToSharers, "fw", desc="invalidate sharers for request") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:INV;
+ out_msg.Requestor := in_msg.Requestor;
+ out_msg.Destination := cache_entry.Sharers;
+ out_msg.MessageSize := MessageSizeType:Request_Control;
+ }
+ }
+ }
+
+ action(fwm_sendFwdInvToSharersMinusRequestor, "fwm", desc="invalidate sharers for request, requestor is sharer") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(L1RequestIntraChipL2Network_out, RequestMsg, latency=to_l1_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceRequestType:INV;
+ out_msg.Requestor := in_msg.Requestor;
+ out_msg.Destination := cache_entry.Sharers;
+ out_msg.Destination.remove(in_msg.Requestor);
+ out_msg.MessageSize := MessageSizeType:Request_Control;
+ }
+ }
+ }
+
+ // OTHER ACTIONS
+ action(i_allocateTBE, "i", desc="Allocate TBE for request") {
+ check_allocate(L2_TBEs);
+ assert(is_valid(cache_entry));
+ L2_TBEs.allocate(address);
+ set_tbe(L2_TBEs[address]);
+ tbe.L1_GetS_IDs.clear();
+ tbe.DataBlk := cache_entry.DataBlk;
+ tbe.Dirty := cache_entry.Dirty;
+ tbe.pendingAcks := cache_entry.Sharers.count();
+ }
+
+ action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
+ L2_TBEs.deallocate(address);
+ unset_tbe();
+ }
+
+ action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") {
+ profileMsgDelay(0, L1RequestIntraChipL2Network_in.dequeue_getDelayCycles());
+ }
+
+ action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") {
+ profileMsgDelay(0, L1unblockNetwork_in.dequeue_getDelayCycles());
+ }
+
+ action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") {
+ profileMsgDelay(1, responseIntraChipL2Network_in.dequeue_getDelayCycles());
+ }
+
+ action(m_writeDataToCache, "m", desc="Write data from response queue to cache") {
+ peek(responseIntraChipL2Network_in, ResponseMsg) {
+ assert(is_valid(cache_entry));
+ cache_entry.DataBlk := in_msg.DataBlk;
+ if (in_msg.Dirty) {
+ cache_entry.Dirty := in_msg.Dirty;
+ }
+ }
+ }
+
+ action(mr_writeDataToCacheFromRequest, "mr", desc="Write data from response queue to cache") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ assert(is_valid(cache_entry));
+ cache_entry.DataBlk := in_msg.DataBlk;
+ if (in_msg.Dirty) {
+ cache_entry.Dirty := in_msg.Dirty;
+ }
+ }
+ }
+
+ action(q_updateAck, "q", desc="update pending ack count") {
+ peek(responseIntraChipL2Network_in, ResponseMsg) {
+ assert(is_valid(tbe));
+ tbe.pendingAcks := tbe.pendingAcks - in_msg.AckCount;
+ APPEND_TRANSITION_COMMENT(in_msg.AckCount);
+ APPEND_TRANSITION_COMMENT(" p: ");
+ APPEND_TRANSITION_COMMENT(tbe.pendingAcks);
+ }
+ }
+
+ action(qq_writeDataToTBE, "\qq", desc="Write data from response queue to TBE") {
+ peek(responseIntraChipL2Network_in, ResponseMsg) {
+ assert(is_valid(tbe));
+ tbe.DataBlk := in_msg.DataBlk;
+ tbe.Dirty := in_msg.Dirty;
+ }
+ }
+
+ action(ss_recordGetSL1ID, "\s", desc="Record L1 GetS for load response") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ assert(is_valid(tbe));
+ tbe.L1_GetS_IDs.add(in_msg.Requestor);
+ }
+ }
+
+ action(xx_recordGetXL1ID, "\x", desc="Record L1 GetX for store response") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ assert(is_valid(tbe));
+ tbe.L1_GetX_ID := in_msg.Requestor;
+ }
+ }
+
+ action(set_setMRU, "\set", desc="set the MRU entry") {
+ L2cache.setMRU(address);
+ }
+
+ action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag of block B.") {
+ if (is_invalid(cache_entry)) {
+ set_cache_entry(L2cache.allocate(address, new Entry));
+ }
+ }
+
+ action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
+ L2cache.deallocate(address);
+ unset_cache_entry();
+ }
+
+ action(t_sendWBAck, "t", desc="Send writeback ACK") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:WB_ACK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ }
+ }
+ }
+
+ action(ts_sendInvAckToUpgrader, "ts", desc="Send ACK to upgrader") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ enqueue(responseIntraChipL2Network_out, ResponseMsg, latency=to_l1_latency) {
+ assert(is_valid(cache_entry));
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:ACK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Requestor);
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ // upgrader doesn't get ack from itself, hence the + 1
+ out_msg.AckCount := 0 - cache_entry.Sharers.count() + 1;
+ }
+ }
+ }
+
+ action(uu_profileMiss, "\um", desc="Profile the demand miss") {
+ ++L2cache.demand_misses;
+ }
+
+ action(uu_profileHit, "\uh", desc="Profile the demand hit") {
+ ++L2cache.demand_hits;
+ }
+
+ action(nn_addSharer, "\n", desc="Add L1 sharer to list") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ assert(is_valid(cache_entry));
+ addSharer(address, in_msg.Requestor, cache_entry);
+ APPEND_TRANSITION_COMMENT( cache_entry.Sharers );
+ }
+ }
+
+ action(nnu_addSharerFromUnblock, "\nu", desc="Add L1 sharer to list") {
+ peek(L1unblockNetwork_in, ResponseMsg) {
+ assert(is_valid(cache_entry));
+ addSharer(address, in_msg.Sender, cache_entry);
+ }
+ }
+
+ action(kk_removeRequestSharer, "\k", desc="Remove L1 Request sharer from list") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ assert(is_valid(cache_entry));
+ cache_entry.Sharers.remove(in_msg.Requestor);
+ }
+ }
+
+ action(ll_clearSharers, "\l", desc="Remove all L1 sharers from list") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ assert(is_valid(cache_entry));
+ cache_entry.Sharers.clear();
+ }
+ }
+
+ action(mm_markExclusive, "\m", desc="set the exclusive owner") {
+ peek(L1RequestIntraChipL2Network_in, RequestMsg) {
+ assert(is_valid(cache_entry));
+ cache_entry.Sharers.clear();
+ cache_entry.Exclusive := in_msg.Requestor;
+ addSharer(address, in_msg.Requestor, cache_entry);
+ }
+ }
+
+ action(mmu_markExclusiveFromUnblock, "\mu", desc="set the exclusive owner") {
+ peek(L1unblockNetwork_in, ResponseMsg) {
+ assert(is_valid(cache_entry));
+ cache_entry.Sharers.clear();
+ cache_entry.Exclusive := in_msg.Sender;
+ addSharer(address, in_msg.Sender, cache_entry);
+ }
+ }
+
+ action(zz_stallAndWaitL1RequestQueue, "zz", desc="recycle L1 request queue") {
+ stall_and_wait(L1RequestIntraChipL2Network_in, address);
+ }
+
+ action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") {
+ responseIntraChipL2Network_in.recycle();
+ }
+
+ action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
+ wakeUpBuffers(address);
+ }
+
+ //*****************************************************
+ // TRANSITIONS
+ //*****************************************************
+
+
+ //===============================================
+ // BASE STATE - I
+
+ // Transitions from I (Idle)
+ transition({NP, IS, ISS, IM, SS, M, M_I, I_I, S_I, MT_IB, MT_SB}, L1_PUTX) {
+ t_sendWBAck;
+ jj_popL1RequestQueue;
+ }
+
+ transition({NP, SS, M, MT, M_I, I_I, S_I, IS, ISS, IM, MT_IB, MT_SB}, L1_PUTX_old) {
+ t_sendWBAck;
+ jj_popL1RequestQueue;
+ }
+
+ transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L2_Replacement, L2_Replacement_clean}) {
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ transition({IM, IS, ISS, SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, MEM_Inv) {
+ zn_recycleResponseNetwork;
+ }
+
+ transition({I_I, S_I, M_I, MT_I, MCT_I, NP}, MEM_Inv) {
+ o_popIncomingResponseQueue;
+ }
+
+
+ transition({SS_MB, MT_MB, MT_IIB, MT_IB, MT_SB}, {L1_GETS, L1_GET_INSTR, L1_GETX, L1_UPGRADE}) {
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+
+ transition(NP, L1_GETS, ISS) {
+ qq_allocateL2CacheBlock;
+ ll_clearSharers;
+ nn_addSharer;
+ i_allocateTBE;
+ ss_recordGetSL1ID;
+ a_issueFetchToMemory;
+ uu_profileMiss;
+ jj_popL1RequestQueue;
+ }
+
+ transition(NP, L1_GET_INSTR, IS) {
+ qq_allocateL2CacheBlock;
+ ll_clearSharers;
+ nn_addSharer;
+ i_allocateTBE;
+ ss_recordGetSL1ID;
+ a_issueFetchToMemory;
+ uu_profileMiss;
+ jj_popL1RequestQueue;
+ }
+
+ transition(NP, L1_GETX, IM) {
+ qq_allocateL2CacheBlock;
+ ll_clearSharers;
+ // nn_addSharer;
+ i_allocateTBE;
+ xx_recordGetXL1ID;
+ a_issueFetchToMemory;
+ uu_profileMiss;
+ jj_popL1RequestQueue;
+ }
+
+
+ // transitions from IS/IM
+
+ transition(ISS, Mem_Data, MT_MB) {
+ m_writeDataToCache;
+ ex_sendExclusiveDataToGetSRequestors;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(IS, Mem_Data, SS) {
+ m_writeDataToCache;
+ e_sendDataToGetSRequestors;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(IM, Mem_Data, MT_MB) {
+ m_writeDataToCache;
+ ee_sendDataToGetXRequestor;
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ }
+
+ transition({IS, ISS}, {L1_GETS, L1_GET_INSTR}, IS) {
+ nn_addSharer;
+ ss_recordGetSL1ID;
+ uu_profileMiss;
+ jj_popL1RequestQueue;
+ }
+
+ transition({IS, ISS}, L1_GETX) {
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ transition(IM, {L1_GETX, L1_GETS, L1_GET_INSTR}) {
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ // transitions from SS
+ transition(SS, {L1_GETS, L1_GET_INSTR}) {
+ ds_sendSharedDataToRequestor;
+ nn_addSharer;
+ set_setMRU;
+ uu_profileHit;
+ jj_popL1RequestQueue;
+ }
+
+
+ transition(SS, L1_GETX, SS_MB) {
+ d_sendDataToRequestor;
+ // fw_sendFwdInvToSharers;
+ fwm_sendFwdInvToSharersMinusRequestor;
+ set_setMRU;
+ uu_profileHit;
+ jj_popL1RequestQueue;
+ }
+
+ transition(SS, L1_UPGRADE, SS_MB) {
+ fwm_sendFwdInvToSharersMinusRequestor;
+ ts_sendInvAckToUpgrader;
+ set_setMRU;
+ uu_profileHit;
+ jj_popL1RequestQueue;
+ }
+
+ transition(SS, L2_Replacement_clean, I_I) {
+ i_allocateTBE;
+ f_sendInvToSharers;
+ rr_deallocateL2CacheBlock;
+ }
+
+ transition(SS, {L2_Replacement, MEM_Inv}, S_I) {
+ i_allocateTBE;
+ f_sendInvToSharers;
+ rr_deallocateL2CacheBlock;
+ }
+
+
+ transition(M, L1_GETX, MT_MB) {
+ d_sendDataToRequestor;
+ set_setMRU;
+ uu_profileHit;
+ jj_popL1RequestQueue;
+ }
+
+ transition(M, L1_GET_INSTR, SS) {
+ d_sendDataToRequestor;
+ nn_addSharer;
+ set_setMRU;
+ uu_profileHit;
+ jj_popL1RequestQueue;
+ }
+
+ transition(M, L1_GETS, MT_MB) {
+ dd_sendExclusiveDataToRequestor;
+ set_setMRU;
+ uu_profileHit;
+ jj_popL1RequestQueue;
+ }
+
+ transition(M, {L2_Replacement, MEM_Inv}, M_I) {
+ i_allocateTBE;
+ c_exclusiveReplacement;
+ rr_deallocateL2CacheBlock;
+ }
+
+ transition(M, L2_Replacement_clean, M_I) {
+ i_allocateTBE;
+ c_exclusiveCleanReplacement;
+ rr_deallocateL2CacheBlock;
+ }
+
+
+ // transitions from MT
+
+ transition(MT, L1_GETX, MT_MB) {
+ b_forwardRequestToExclusive;
+ uu_profileMiss;
+ set_setMRU;
+ jj_popL1RequestQueue;
+ }
+
+
+ transition(MT, {L1_GETS, L1_GET_INSTR}, MT_IIB) {
+ b_forwardRequestToExclusive;
+ uu_profileMiss;
+ set_setMRU;
+ jj_popL1RequestQueue;
+ }
+
+ transition(MT, {L2_Replacement, MEM_Inv}, MT_I) {
+ i_allocateTBE;
+ f_sendInvToSharers;
+ rr_deallocateL2CacheBlock;
+ }
+
+ transition(MT, L2_Replacement_clean, MCT_I) {
+ i_allocateTBE;
+ f_sendInvToSharers;
+ rr_deallocateL2CacheBlock;
+ }
+
+ transition(MT, L1_PUTX, M) {
+ ll_clearSharers;
+ mr_writeDataToCacheFromRequest;
+ t_sendWBAck;
+ jj_popL1RequestQueue;
+ }
+
+ transition({SS_MB,MT_MB}, Exclusive_Unblock, MT) {
+ // update actual directory
+ mmu_markExclusiveFromUnblock;
+ k_popUnblockQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(MT_IIB, {L1_PUTX, L1_PUTX_old}){
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ transition(MT_IIB, Unblock, MT_IB) {
+ nnu_addSharerFromUnblock;
+ k_popUnblockQueue;
+ }
+
+ transition(MT_IIB, {WB_Data, WB_Data_clean}, MT_SB) {
+ m_writeDataToCache;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(MT_IB, {WB_Data, WB_Data_clean}, SS) {
+ m_writeDataToCache;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(MT_SB, Unblock, SS) {
+ nnu_addSharerFromUnblock;
+ k_popUnblockQueue;
+ kd_wakeUpDependents;
+ }
+
+ // writeback states
+ transition({I_I, S_I, MT_I, MCT_I, M_I}, {L1_GETX, L1_UPGRADE, L1_GETS, L1_GET_INSTR}) {
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ transition(I_I, Ack) {
+ q_updateAck;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(I_I, Ack_all, M_I) {
+ c_exclusiveCleanReplacement;
+ o_popIncomingResponseQueue;
+ }
+
+ transition({MT_I, MCT_I}, WB_Data, M_I) {
+ qq_writeDataToTBE;
+ ct_exclusiveReplacementFromTBE;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(MCT_I, {WB_Data_clean, Ack_all}, M_I) {
+ c_exclusiveCleanReplacement;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(MCT_I, {L1_PUTX, L1_PUTX_old}){
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ // L1 never changed Dirty data
+ transition(MT_I, {WB_Data_clean, Ack_all}, M_I) {
+ ct_exclusiveReplacementFromTBE;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(MT_I, {L1_PUTX, L1_PUTX_old}){
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ // possible race between unblock and immediate replacement
+ transition({MT_MB,SS_MB}, {L1_PUTX, L1_PUTX_old}) {
+ zz_stallAndWaitL1RequestQueue;
+ }
+
+ transition(S_I, Ack) {
+ q_updateAck;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(S_I, Ack_all, M_I) {
+ ct_exclusiveReplacementFromTBE;
+ o_popIncomingResponseQueue;
+ }
+
+ transition(M_I, Mem_Ack, NP) {
+ s_deallocateTBE;
+ o_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+}
--- /dev/null
+/*
+ * Copyright (c) 1999-2013 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00 mikem@royal16.cs.wisc.edu $
+ */
+
+// This file is copied from Yasuko Watanabe's prefetch / memory protocol
+// Copied here by aep 12/14/07
+
+
+machine(Directory, "MESI Two Level directory protocol")
+ : DirectoryMemory * directory,
+ MemoryControl * memBuffer,
+ Cycles to_mem_ctrl_latency = 1,
+ Cycles directory_latency = 6,
+{
+ MessageBuffer requestToDir, network="From", virtual_network="0",
+ ordered="false", vnet_type="request";
+ MessageBuffer responseToDir, network="From", virtual_network="1",
+ ordered="false", vnet_type="response";
+ MessageBuffer responseFromDir, network="To", virtual_network="1",
+ ordered="false", vnet_type="response";
+
+ // STATES
+ state_declaration(State, desc="Directory states", default="Directory_State_I") {
+ // Base states
+ I, AccessPermission:Read_Write, desc="dir is the owner and memory is up-to-date, all other copies are Invalid";
+ ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
+ ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
+
+ M, AccessPermission:Maybe_Stale, desc="memory copy may be stale, i.e. other modified copies may exist";
+ IM, AccessPermission:Busy, desc="Intermediate State I>M";
+ MI, AccessPermission:Busy, desc="Intermediate State M>I";
+ M_DRD, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
+ M_DRDI, AccessPermission:Busy, desc="Intermediate State when there is a dma read";
+ M_DWR, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
+ M_DWRI, AccessPermission:Busy, desc="Intermediate State when there is a dma write";
+ }
+
+ // Events
+ enumeration(Event, desc="Directory events") {
+ Fetch, desc="A memory fetch arrives";
+ Data, desc="writeback data arrives";
+ Memory_Data, desc="Fetched data from memory arrives";
+ Memory_Ack, desc="Writeback Ack from memory arrives";
+//added by SS for dma
+ DMA_READ, desc="A DMA Read memory request";
+ DMA_WRITE, desc="A DMA Write memory request";
+ CleanReplacement, desc="Clean Replacement in L2 cache";
+
+ }
+
+ // TYPES
+
+ // DirectoryEntry
+ structure(Entry, desc="...", interface="AbstractEntry") {
+ State DirectoryState, desc="Directory state";
+ DataBlock DataBlk, desc="data for the block";
+ MachineID Owner;
+ }
+
+ // TBE entries for DMA requests
+ structure(TBE, desc="TBE entries for outstanding DMA requests") {
+ Address PhysicalAddress, desc="physical address";
+ State TBEState, desc="Transient State";
+ DataBlock DataBlk, desc="Data to be written (DMA write only)";
+ int Len, desc="...";
+ }
+
+ structure(TBETable, external="yes") {
+ TBE lookup(Address);
+ void allocate(Address);
+ void deallocate(Address);
+ bool isPresent(Address);
+ }
+
+
+ // ** OBJECTS **
+ TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
+
+ void set_tbe(TBE tbe);
+ void unset_tbe();
+ void wakeUpBuffers(Address a);
+
+ Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
+ Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
+
+ if (is_valid(dir_entry)) {
+ return dir_entry;
+ }
+
+ dir_entry := static_cast(Entry, "pointer",
+ directory.allocate(addr, new Entry));
+ return dir_entry;
+ }
+
+ State getState(TBE tbe, Address addr) {
+ if (is_valid(tbe)) {
+ return tbe.TBEState;
+ } else if (directory.isPresent(addr)) {
+ return getDirectoryEntry(addr).DirectoryState;
+ } else {
+ return State:I;
+ }
+ }
+
+ void setState(TBE tbe, Address addr, State state) {
+ if (is_valid(tbe)) {
+ tbe.TBEState := state;
+ }
+
+ if (directory.isPresent(addr)) {
+ getDirectoryEntry(addr).DirectoryState := state;
+ }
+ }
+
+ AccessPermission getAccessPermission(Address addr) {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(tbe.TBEState));
+ return Directory_State_to_permission(tbe.TBEState);
+ }
+
+ if(directory.isPresent(addr)) {
+ DPRINTF(RubySlicc, "%s\n", Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState));
+ return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+ }
+
+ DPRINTF(RubySlicc, "%s\n", AccessPermission:NotPresent);
+ return AccessPermission:NotPresent;
+ }
+
+ DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ return tbe.DataBlk;
+ }
+
+ return getDirectoryEntry(addr).DataBlk;
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ if (directory.isPresent(addr)) {
+ getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+ }
+ }
+
+ bool isGETRequest(CoherenceRequestType type) {
+ return (type == CoherenceRequestType:GETS) ||
+ (type == CoherenceRequestType:GET_INSTR) ||
+ (type == CoherenceRequestType:GETX);
+ }
+
+
+ // ** OUT_PORTS **
+ out_port(responseNetwork_out, ResponseMsg, responseFromDir);
+ out_port(memQueue_out, MemoryMsg, memBuffer);
+
+ // ** IN_PORTS **
+
+ in_port(requestNetwork_in, RequestMsg, requestToDir, rank = 0) {
+ if (requestNetwork_in.isReady()) {
+ peek(requestNetwork_in, RequestMsg) {
+ assert(in_msg.Destination.isElement(machineID));
+ if (isGETRequest(in_msg.Type)) {
+ trigger(Event:Fetch, in_msg.Addr, TBEs[in_msg.Addr]);
+ } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
+ trigger(Event:DMA_READ, makeLineAddress(in_msg.Addr),
+ TBEs[makeLineAddress(in_msg.Addr)]);
+ } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
+ trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Addr),
+ TBEs[makeLineAddress(in_msg.Addr)]);
+ } else {
+ DPRINTF(RubySlicc, "%s\n", in_msg);
+ error("Invalid message");
+ }
+ }
+ }
+ }
+
+ in_port(responseNetwork_in, ResponseMsg, responseToDir, rank = 1) {
+ if (responseNetwork_in.isReady()) {
+ peek(responseNetwork_in, ResponseMsg) {
+ assert(in_msg.Destination.isElement(machineID));
+ if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
+ trigger(Event:Data, in_msg.Addr, TBEs[in_msg.Addr]);
+ } else if (in_msg.Type == CoherenceResponseType:ACK) {
+ trigger(Event:CleanReplacement, in_msg.Addr, TBEs[in_msg.Addr]);
+ } else {
+ DPRINTF(RubySlicc, "%s\n", in_msg.Type);
+ error("Invalid message");
+ }
+ }
+ }
+ }
+
+ // off-chip memory request/response is done
+ in_port(memQueue_in, MemoryMsg, memBuffer, rank = 2) {
+ if (memQueue_in.isReady()) {
+ peek(memQueue_in, MemoryMsg) {
+ if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
+ trigger(Event:Memory_Data, in_msg.Addr, TBEs[in_msg.Addr]);
+ } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
+ trigger(Event:Memory_Ack, in_msg.Addr, TBEs[in_msg.Addr]);
+ } else {
+ DPRINTF(RubySlicc, "%s\n", in_msg.Type);
+ error("Invalid message");
+ }
+ }
+ }
+ }
+
+
+ // Actions
+ action(a_sendAck, "a", desc="Send ack to L2") {
+ peek(responseNetwork_in, ResponseMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:MEMORY_ACK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.Sender);
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ }
+ }
+ }
+
+ action(d_sendData, "d", desc="Send data to requestor") {
+ peek(memQueue_in, MemoryMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:MEMORY_DATA;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.OriginalRequestorMachId);
+ out_msg.DataBlk := in_msg.DataBlk;
+ out_msg.Dirty := false;
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+
+ Entry e := getDirectoryEntry(in_msg.Addr);
+ e.Owner := in_msg.OriginalRequestorMachId;
+ }
+ }
+ }
+
+ // Actions
+ action(aa_sendAck, "aa", desc="Send ack to L2") {
+ peek(memQueue_in, MemoryMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:MEMORY_ACK;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(in_msg.OriginalRequestorMachId);
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ }
+ }
+ }
+
+ action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") {
+ requestNetwork_in.dequeue();
+ }
+
+ action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") {
+ responseNetwork_in.dequeue();
+ }
+
+ action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
+ memQueue_in.dequeue();
+ }
+
+ action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
+ wakeUpBuffers(address);
+ }
+
+ action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
+ peek(requestNetwork_in, RequestMsg) {
+ enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := MemoryRequestType:MEMORY_READ;
+ out_msg.Sender := machineID;
+ out_msg.OriginalRequestorMachId := in_msg.Requestor;
+ out_msg.MessageSize := in_msg.MessageSize;
+ out_msg.Prefetch := in_msg.Prefetch;
+ out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
+
+ DPRINTF(RubySlicc, "%s\n", out_msg);
+ }
+ }
+ }
+
+ action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
+ peek(responseNetwork_in, ResponseMsg) {
+ enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := MemoryRequestType:MEMORY_WB;
+ out_msg.Sender := machineID;
+ out_msg.OriginalRequestorMachId := in_msg.Sender;
+ out_msg.DataBlk := in_msg.DataBlk;
+ out_msg.MessageSize := in_msg.MessageSize;
+ //out_msg.Prefetch := in_msg.Prefetch;
+
+ DPRINTF(RubySlicc, "%s\n", out_msg);
+ }
+ }
+ }
+
+ action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
+ peek(responseNetwork_in, ResponseMsg) {
+ getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
+ DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
+ in_msg.Addr, in_msg.DataBlk);
+ }
+ }
+//added by SS for dma
+ action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
+ peek(requestNetwork_in, RequestMsg) {
+ enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := MemoryRequestType:MEMORY_READ;
+ out_msg.Sender := machineID;
+ out_msg.OriginalRequestorMachId := machineID;
+ out_msg.MessageSize := in_msg.MessageSize;
+ out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
+ DPRINTF(RubySlicc, "%s\n", out_msg);
+ }
+ }
+ }
+
+ action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
+ requestNetwork_in.dequeue();
+ }
+
+ action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
+ peek(memQueue_in, MemoryMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
+ out_msg.Destination.add(map_Address_to_DMA(address));
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+ }
+
+ action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
+ peek(requestNetwork_in, RequestMsg) {
+ getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Addr), in_msg.Len);
+ }
+ }
+
+ action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
+ peek(requestNetwork_in, RequestMsg) {
+ enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := MemoryRequestType:MEMORY_WB;
+ out_msg.OriginalRequestorMachId := machineID;
+ //out_msg.DataBlk := in_msg.DataBlk;
+ out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(address), in_msg.Len);
+
+
+ out_msg.MessageSize := in_msg.MessageSize;
+ //out_msg.Prefetch := in_msg.Prefetch;
+
+ DPRINTF(RubySlicc, "%s\n", out_msg);
+ }
+ }
+ }
+
+ action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:ACK;
+ out_msg.Destination.add(map_Address_to_DMA(address));
+ out_msg.MessageSize := MessageSizeType:Writeback_Control;
+ }
+ }
+
+ action(z_stallAndWaitRequest, "z", desc="recycle request queue") {
+ stall_and_wait(requestNetwork_in, address);
+ }
+
+ action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") {
+ requestNetwork_in.recycle();
+ }
+
+ action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
+ peek(requestNetwork_in, RequestMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:INV;
+ out_msg.Sender := machineID;
+ out_msg.Destination.add(getDirectoryEntry(address).Owner);
+ out_msg.MessageSize := MessageSizeType:Response_Control;
+ }
+ }
+ }
+
+
+ action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
+ peek(responseNetwork_in, ResponseMsg) {
+ enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) {
+ out_msg.Addr := address;
+ out_msg.Type := CoherenceResponseType:DATA;
+ out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
+ out_msg.Destination.add(map_Address_to_DMA(address));
+ out_msg.MessageSize := MessageSizeType:Response_Data;
+ }
+ }
+ }
+
+ action(v_allocateTBE, "v", desc="Allocate TBE") {
+ peek(requestNetwork_in, RequestMsg) {
+ TBEs.allocate(address);
+ set_tbe(TBEs[address]);
+ tbe.DataBlk := in_msg.DataBlk;
+ tbe.PhysicalAddress := in_msg.Addr;
+ tbe.Len := in_msg.Len;
+ }
+ }
+
+ action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
+ assert(is_valid(tbe));
+ //getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
+ getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
+
+
+ }
+
+
+ action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
+ peek(responseNetwork_in, ResponseMsg) {
+ enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) {
+ assert(is_valid(tbe));
+ out_msg.Addr := address;
+ out_msg.Type := MemoryRequestType:MEMORY_WB;
+ out_msg.OriginalRequestorMachId := in_msg.Sender;
+ //out_msg.DataBlk := in_msg.DataBlk;
+ //out_msg.DataBlk.copyPartial(tbe.DataBlk, tbe.Offset, tbe.Len);
+ out_msg.DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
+
+ out_msg.MessageSize := in_msg.MessageSize;
+ //out_msg.Prefetch := in_msg.Prefetch;
+
+ DPRINTF(RubySlicc, "%s\n", out_msg);
+ }
+ }
+ }
+
+ action(w_deallocateTBE, "w", desc="Deallocate TBE") {
+ TBEs.deallocate(address);
+ unset_tbe();
+ }
+
+
+ // TRANSITIONS
+
+ transition(I, Fetch, IM) {
+ qf_queueMemoryFetchRequest;
+ j_popIncomingRequestQueue;
+ }
+
+ transition(M, Fetch) {
+ inv_sendCacheInvalidate;
+ z_stallAndWaitRequest;
+ }
+
+ transition(IM, Memory_Data, M) {
+ d_sendData;
+ l_popMemQueue;
+ kd_wakeUpDependents;
+ }
+//added by SS
+ transition(M, CleanReplacement, I) {
+ a_sendAck;
+ k_popIncomingResponseQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(M, Data, MI) {
+ m_writeDataToMemory;
+ qw_queueMemoryWBRequest;
+ k_popIncomingResponseQueue;
+ }
+
+ transition(MI, Memory_Ack, I) {
+ aa_sendAck;
+ l_popMemQueue;
+ kd_wakeUpDependents;
+ }
+
+
+//added by SS for dma support
+ transition(I, DMA_READ, ID) {
+ qf_queueMemoryFetchRequestDMA;
+ j_popIncomingRequestQueue;
+ }
+
+ transition(ID, Memory_Data, I) {
+ dr_sendDMAData;
+ l_popMemQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(I, DMA_WRITE, ID_W) {
+ dw_writeDMAData;
+ qw_queueMemoryWBRequest_partial;
+ j_popIncomingRequestQueue;
+ }
+
+ transition(ID_W, Memory_Ack, I) {
+ da_sendDMAAck;
+ l_popMemQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition({ID, ID_W, M_DRDI, M_DWRI, IM, MI}, {Fetch, Data} ) {
+ z_stallAndWaitRequest;
+ }
+
+ transition({ID, ID_W, M_DRD, M_DRDI, M_DWR, M_DWRI, IM, MI}, {DMA_WRITE, DMA_READ} ) {
+ zz_recycleDMAQueue;
+ }
+
+
+ transition(M, DMA_READ, M_DRD) {
+ inv_sendCacheInvalidate;
+ j_popIncomingRequestQueue;
+ }
+
+ transition(M_DRD, Data, M_DRDI) {
+ drp_sendDMAData;
+ m_writeDataToMemory;
+ qw_queueMemoryWBRequest;
+ k_popIncomingResponseQueue;
+ }
+
+ transition(M_DRDI, Memory_Ack, I) {
+ aa_sendAck;
+ l_popMemQueue;
+ kd_wakeUpDependents;
+ }
+
+ transition(M, DMA_WRITE, M_DWR) {
+ v_allocateTBE;
+ inv_sendCacheInvalidate;
+ j_popIncomingRequestQueue;
+ }
+
+ transition(M_DWR, Data, M_DWRI) {
+ m_writeDataToMemory;
+ qw_queueMemoryWBRequest_partialTBE;
+ k_popIncomingResponseQueue;
+ }
+
+ transition(M_DWRI, Memory_Ack, I) {
+ dwt_writeDMADataFromTBE;
+ aa_sendAck;
+ da_sendDMAAck;
+ w_deallocateTBE;
+ l_popMemQueue;
+ kd_wakeUpDependents;
+ }
+}
--- /dev/null
+/*
+ * Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
+ * Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+machine(DMA, "DMA Controller")
+: DMASequencer * dma_sequencer,
+ Cycles request_latency = 6
+{
+
+ MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true";
+ MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request", no_vector="true";
+
+ state_declaration(State, desc="DMA states", default="DMA_State_READY") {
+ READY, AccessPermission:Invalid, desc="Ready to accept a new request";
+ BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request";
+ BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request";
+ }
+
+ enumeration(Event, desc="DMA events") {
+ ReadRequest, desc="A new read request";
+ WriteRequest, desc="A new write request";
+ Data, desc="Data from a DMA memory read";
+ Ack, desc="DMA write to memory completed";
+ }
+
+ structure(DMASequencer, external="yes") {
+ void ackCallback();
+ void dataCallback(DataBlock);
+ }
+
+ MessageBuffer mandatoryQueue, ordered="false", no_vector="true";
+ State cur_state, no_vector="true";
+
+ State getState(Address addr) {
+ return cur_state;
+ }
+ void setState(Address addr, State state) {
+ cur_state := state;
+ }
+
+ AccessPermission getAccessPermission(Address addr) {
+ return AccessPermission:NotPresent;
+ }
+
+ void setAccessPermission(Address addr, State state) {
+ }
+
+ DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ error("DMA does not support get data block.");
+ }
+
+ out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
+
+ in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
+ if (dmaRequestQueue_in.isReady()) {
+ peek(dmaRequestQueue_in, SequencerMsg) {
+ if (in_msg.Type == SequencerRequestType:LD ) {
+ trigger(Event:ReadRequest, in_msg.LineAddress);
+ } else if (in_msg.Type == SequencerRequestType:ST) {
+ trigger(Event:WriteRequest, in_msg.LineAddress);
+ } else {
+ error("Invalid request type");
+ }
+ }
+ }
+ }
+
+ in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") {
+ if (dmaResponseQueue_in.isReady()) {
+ peek( dmaResponseQueue_in, ResponseMsg) {
+ if (in_msg.Type == CoherenceResponseType:ACK) {
+ trigger(Event:Ack, makeLineAddress(in_msg.Addr));
+ } else if (in_msg.Type == CoherenceResponseType:DATA) {
+ trigger(Event:Data, makeLineAddress(in_msg.Addr));
+ } else {
+ error("Invalid response type");
+ }
+ }
+ }
+ }
+
+ action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") {
+ peek(dmaRequestQueue_in, SequencerMsg) {
+ enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
+ out_msg.Addr := in_msg.PhysicalAddress;
+ out_msg.Type := CoherenceRequestType:DMA_READ;
+ out_msg.DataBlk := in_msg.DataBlk;
+ out_msg.Len := in_msg.Len;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.MessageSize := MessageSizeType:Writeback_Control;
+ }
+ }
+ }
+
+ action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") {
+ peek(dmaRequestQueue_in, SequencerMsg) {
+ enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) {
+ out_msg.Addr := in_msg.PhysicalAddress;
+ out_msg.Type := CoherenceRequestType:DMA_WRITE;
+ out_msg.DataBlk := in_msg.DataBlk;
+ out_msg.Len := in_msg.Len;
+ out_msg.Destination.add(map_Address_to_Directory(address));
+ out_msg.MessageSize := MessageSizeType:Writeback_Control;
+ }
+ }
+ }
+
+ action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
+ dma_sequencer.ackCallback();
+ }
+
+ action(d_dataCallback, "d", desc="Write data to dma sequencer") {
+ peek (dmaResponseQueue_in, ResponseMsg) {
+ dma_sequencer.dataCallback(in_msg.DataBlk);
+ }
+ }
+
+ action(p_popRequestQueue, "p", desc="Pop request queue") {
+ dmaRequestQueue_in.dequeue();
+ }
+
+ action(p_popResponseQueue, "\p", desc="Pop request queue") {
+ dmaResponseQueue_in.dequeue();
+ }
+
+ action(z_stall, "z", desc="dma is busy..stall") {
+ // do nothing
+ }
+
+ transition(READY, ReadRequest, BUSY_RD) {
+ s_sendReadRequest;
+ p_popRequestQueue;
+ }
+
+ transition(READY, WriteRequest, BUSY_WR) {
+ s_sendWriteRequest;
+ p_popRequestQueue;
+ }
+
+ transition(BUSY_RD, Data, READY) {
+ d_dataCallback;
+ p_popResponseQueue;
+ }
+
+ transition(BUSY_WR, Ack, READY) {
+ a_ackCallback;
+ p_popResponseQueue;
+ }
+}
--- /dev/null
+
+/*
+ * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+// CoherenceRequestType
+enumeration(CoherenceRequestType, desc="...") {
+ GETX, desc="Get eXclusive";
+ UPGRADE, desc="UPGRADE to exclusive";
+ GETS, desc="Get Shared";
+ GET_INSTR, desc="Get Instruction";
+ INV, desc="INValidate";
+ PUTX, desc="Replacement message";
+
+ WB_ACK, desc="Writeback ack";
+
+ DMA_READ, desc="DMA Read";
+ DMA_WRITE, desc="DMA Write";
+}
+
+// CoherenceResponseType
+enumeration(CoherenceResponseType, desc="...") {
+ MEMORY_ACK, desc="Ack from memory controller";
+ DATA, desc="Data block for L1 cache in S state";
+ DATA_EXCLUSIVE, desc="Data block for L1 cache in M/E state";
+ MEMORY_DATA, desc="Data block from / to main memory";
+ ACK, desc="Generic invalidate ack";
+ WB_ACK, desc="writeback ack";
+ UNBLOCK, desc="unblock";
+ EXCLUSIVE_UNBLOCK, desc="exclusive unblock";
+ INV, desc="Invalidate from directory";
+}
+
+// RequestMsg
+structure(RequestMsg, desc="...", interface="NetworkMessage") {
+ Address Addr, desc="Physical address for this request";
+ CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)";
+ RubyAccessMode AccessMode, desc="user/supervisor access type";
+ MachineID Requestor , desc="What component request";
+ NetDest Destination, desc="What components receive the request, includes MachineType and num";
+ MessageSizeType MessageSize, desc="size category of the message";
+ DataBlock DataBlk, desc="Data for the cache line (if PUTX)";
+ int Len;
+ bool Dirty, default="false", desc="Dirty bit";
+ PrefetchBit Prefetch, desc="Is this a prefetch request";
+
+ bool functionalRead(Packet *pkt) {
+ // Only PUTX messages contains the data block
+ if (Type == CoherenceRequestType:PUTX) {
+ return testAndRead(Addr, DataBlk, pkt);
+ }
+
+ return false;
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ // No check on message type required since the protocol should
+ // read data from those messages that contain the block
+ return testAndWrite(Addr, DataBlk, pkt);
+ }
+}
+
+// ResponseMsg
+structure(ResponseMsg, desc="...", interface="NetworkMessage") {
+ Address Addr, desc="Physical address for this request";
+ CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)";
+ MachineID Sender, desc="What component sent the data";
+ NetDest Destination, desc="Node to whom the data is sent";
+ DataBlock DataBlk, desc="Data for the cache line";
+ bool Dirty, default="false", desc="Dirty bit";
+ int AckCount, default="0", desc="number of acks in this message";
+ MessageSizeType MessageSize, desc="size category of the message";
+
+ bool functionalRead(Packet *pkt) {
+ // Valid data block is only present in message with following types
+ if (Type == CoherenceResponseType:DATA ||
+ Type == CoherenceResponseType:DATA_EXCLUSIVE ||
+ Type == CoherenceResponseType:MEMORY_DATA) {
+
+ return testAndRead(Addr, DataBlk, pkt);
+ }
+
+ return false;
+ }
+
+ bool functionalWrite(Packet *pkt) {
+ // No check on message type required since the protocol should
+ // read data from those messages that contain the block
+ return testAndWrite(Addr, DataBlk, pkt);
+ }
+}
--- /dev/null
+protocol "MESI_Two_Level";
+include "RubySlicc_interfaces.slicc";
+include "MESI_Two_Level-msg.sm";
+include "MESI_Two_Level-L1cache.sm";
+include "MESI_Two_Level-L2cache.sm";
+include "MESI_Two_Level-dir.sm";
+include "MESI_Two_Level-dma.sm";
Import('*')
all_protocols.extend([
- 'MESI_CMP_directory',
+ 'MESI_Two_Level',
'MI_example',
'MOESI_CMP_directory',
'MOESI_CMP_token',
+++ /dev/null
-[root]
-type=Root
-children=system
-full_system=true
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=LinuxX86System
-children=acpi_description_table_pointer clk_domain cpu0 cpu1 cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl pc physmem piobus ruby smbios_table sys_port_proxy voltage_domain
-acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-cache_line_size=64
-clk_domain=system.clk_domain
-e820_table=system.e820_table
-init_param=0
-intel_mp_pointer=system.intel_mp_pointer
-intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
-load_addr_mask=18446744073709551615
-mem_mode=timing
-mem_ranges=0:134217727
-memories=system.physmem
-num_work_ids=16
-readfile=tests/halt.sh
-smbios_table=system.smbios_table
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.acpi_description_table_pointer]
-type=X86ACPIRSDP
-children=xsdt
-oem_id=
-revision=2
-rsdt=Null
-xsdt=system.acpi_description_table_pointer.xsdt
-
-[system.acpi_description_table_pointer.xsdt]
-type=X86ACPIXSDT
-creator_id=
-creator_revision=0
-entries=
-oem_id=
-oem_revision=0
-oem_table_id=
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=TimingSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu0.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu0.interrupts
-isa=system.cpu0.isa
-itb=system.cpu0.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-switched_out=false
-system=system
-tracer=system.cpu0.tracer
-workload=
-dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
-icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu0.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-
-[system.cpu0.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu0.dtb.walker
-
-[system.cpu0.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[3]
-
-[system.cpu0.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu0.apic_clk_domain
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.piobus.slave[4]
-int_slave=system.piobus.master[18]
-pio=system.piobus.master[17]
-
-[system.cpu0.isa]
-type=X86ISA
-
-[system.cpu0.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu0.itb.walker
-
-[system.cpu0.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl0.sequencer.slave[2]
-
-[system.cpu0.tracer]
-type=ExeTracer
-
-[system.cpu1]
-type=TimingSimpleCPU
-children=apic_clk_domain dtb interrupts isa itb tracer
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=1
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu1.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu1.interrupts
-isa=system.cpu1.isa
-itb=system.cpu1.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-switched_out=false
-system=system
-tracer=system.cpu1.tracer
-workload=
-dcache_port=system.ruby.l1_cntrl1.sequencer.slave[1]
-icache_port=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu1.apic_clk_domain]
-type=DerivedClockDomain
-clk_divider=16
-clk_domain=system.cpu_clk_domain
-
-[system.cpu1.dtb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu1.dtb.walker
-
-[system.cpu1.dtb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[3]
-
-[system.cpu1.interrupts]
-type=X86LocalApic
-clk_domain=system.cpu1.apic_clk_domain
-int_latency=1000
-pio_addr=2305843009213693952
-pio_latency=100000
-system=system
-int_master=system.piobus.slave[5]
-int_slave=system.piobus.master[20]
-pio=system.piobus.master[19]
-
-[system.cpu1.isa]
-type=X86ISA
-
-[system.cpu1.itb]
-type=X86TLB
-children=walker
-size=64
-walker=system.cpu1.itb.walker
-
-[system.cpu1.itb.walker]
-type=X86PagetableWalker
-clk_domain=system.cpu_clk_domain
-num_squash_per_cycle=4
-system=system
-port=system.ruby.l1_cntrl1.sequencer.slave[2]
-
-[system.cpu1.tracer]
-type=ExeTracer
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=500
-voltage_domain=system.voltage_domain
-
-[system.e820_table]
-type=X86E820Table
-children=entries0 entries1 entries2 entries3
-entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
-
-[system.e820_table.entries0]
-type=X86E820Entry
-addr=0
-range_type=1
-size=654336
-
-[system.e820_table.entries1]
-type=X86E820Entry
-addr=654336
-range_type=2
-size=394240
-
-[system.e820_table.entries2]
-type=X86E820Entry
-addr=1048576
-range_type=1
-size=133169152
-
-[system.e820_table.entries3]
-type=X86E820Entry
-addr=4294901760
-range_type=2
-size=65536
-
-[system.intel_mp_pointer]
-type=X86IntelMPFloatingPointer
-default_config=0
-imcr_present=true
-spec_rev=4
-
-[system.intel_mp_table]
-type=X86IntelMPConfigTable
-children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 base_entries33 ext_entries
-base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 system.intel_mp_table.base_entries33
-ext_entries=system.intel_mp_table.ext_entries
-local_apic=4276092928
-oem_id=
-oem_table_addr=0
-oem_table_size=0
-product_id=
-spec_rev=4
-
-[system.intel_mp_table.base_entries00]
-type=X86IntelMPProcessor
-bootstrap=true
-enable=true
-family=0
-feature_flags=0
-local_apic_id=0
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries01]
-type=X86IntelMPProcessor
-bootstrap=false
-enable=true
-family=0
-feature_flags=0
-local_apic_id=1
-local_apic_version=20
-model=0
-stepping=0
-
-[system.intel_mp_table.base_entries02]
-type=X86IntelMPIOAPIC
-address=4273995776
-enable=true
-id=2
-version=17
-
-[system.intel_mp_table.base_entries03]
-type=X86IntelMPBus
-bus_id=0
-bus_type=ISA
-
-[system.intel_mp_table.base_entries04]
-type=X86IntelMPBus
-bus_id=1
-bus_type=PCI
-
-[system.intel_mp_table.base_entries05]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=16
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=1
-source_bus_irq=16
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries06]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries07]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=2
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=0
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries08]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries09]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=1
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=1
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries10]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries11]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=3
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=3
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries12]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries13]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=4
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=4
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries14]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries15]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=5
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=5
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries16]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries17]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=6
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=6
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries18]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries19]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=7
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=7
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries20]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries21]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=8
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=8
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries22]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries23]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=9
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=9
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries24]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries25]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=10
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=10
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries26]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries27]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=11
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=11
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries28]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries29]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=12
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=12
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries30]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries31]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=13
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=13
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries32]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=0
-interrupt_type=ExtInt
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.base_entries33]
-type=X86IntelMPIOIntAssignment
-dest_io_apic_id=2
-dest_io_apic_intin=14
-interrupt_type=INT
-polarity=ConformPolarity
-source_bus_id=0
-source_bus_irq=14
-trigger=ConformTrigger
-
-[system.intel_mp_table.ext_entries]
-type=X86IntelMPBusHierarchy
-bus_id=0
-parent_bus=1
-subtractive_decode=true
-
-[system.intrctrl]
-type=IntrControl
-sys=system
-
-[system.pc]
-type=Pc
-children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
-intrctrl=system.intrctrl
-system=system
-
-[system.pc.behind_pci]
-type=IsaFake
-clk_domain=system.clk_domain
-fake_mem=false
-pio_addr=9223372036854779128
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.piobus.master[11]
-
-[system.pc.com_1]
-type=Uart8250
-children=terminal
-clk_domain=system.clk_domain
-pio_addr=9223372036854776824
-pio_latency=100000
-platform=system.pc
-system=system
-terminal=system.pc.com_1.terminal
-pio=system.piobus.master[12]
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.com_1.terminal]
-type=Terminal
-intr_control=system.intrctrl
-number=0
-output=true
-port=3456
-
-[system.pc.fake_com_2]
-type=IsaFake
-clk_domain=system.clk_domain
-fake_mem=false
-pio_addr=9223372036854776568
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.piobus.master[13]
-
-[system.pc.fake_com_3]
-type=IsaFake
-clk_domain=system.clk_domain
-fake_mem=false
-pio_addr=9223372036854776808
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.piobus.master[14]
-
-[system.pc.fake_com_4]
-type=IsaFake
-clk_domain=system.clk_domain
-fake_mem=false
-pio_addr=9223372036854776552
-pio_latency=100000
-pio_size=8
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.piobus.master[15]
-
-[system.pc.fake_floppy]
-type=IsaFake
-clk_domain=system.clk_domain
-fake_mem=false
-pio_addr=9223372036854776818
-pio_latency=100000
-pio_size=2
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.piobus.master[16]
-
-[system.pc.i_dont_exist]
-type=IsaFake
-clk_domain=system.clk_domain
-fake_mem=false
-pio_addr=9223372036854775936
-pio_latency=100000
-pio_size=1
-ret_bad_addr=false
-ret_data16=65535
-ret_data32=4294967295
-ret_data64=18446744073709551615
-ret_data8=255
-system=system
-update_data=false
-warn_access=
-pio=system.piobus.master[10]
-
-[system.pc.pciconfig]
-type=PciConfigAll
-bus=0
-clk_domain=system.clk_domain
-pio_addr=0
-pio_latency=30000
-platform=system.pc
-size=16777216
-system=system
-pio=system.piobus.default
-
-[system.pc.south_bridge]
-type=SouthBridge
-children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
-cmos=system.pc.south_bridge.cmos
-dma1=system.pc.south_bridge.dma1
-io_apic=system.pc.south_bridge.io_apic
-keyboard=system.pc.south_bridge.keyboard
-pic1=system.pc.south_bridge.pic1
-pic2=system.pc.south_bridge.pic2
-pit=system.pc.south_bridge.pit
-platform=system.pc
-speaker=system.pc.south_bridge.speaker
-
-[system.pc.south_bridge.cmos]
-type=Cmos
-children=int_pin
-clk_domain=system.clk_domain
-int_pin=system.pc.south_bridge.cmos.int_pin
-pio_addr=9223372036854775920
-pio_latency=100000
-system=system
-time=Sun Jan 1 00:00:00 2012
-pio=system.piobus.master[0]
-
-[system.pc.south_bridge.cmos.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.dma1]
-type=I8237
-clk_domain=system.clk_domain
-pio_addr=9223372036854775808
-pio_latency=100000
-system=system
-pio=system.piobus.master[1]
-
-[system.pc.south_bridge.ide]
-type=IdeController
-children=disks0 disks1
-BAR0=496
-BAR0LegacyIO=true
-BAR0Size=8
-BAR1=1012
-BAR1LegacyIO=true
-BAR1Size=3
-BAR2=368
-BAR2LegacyIO=true
-BAR2Size=8
-BAR3=884
-BAR3LegacyIO=true
-BAR3Size=3
-BAR4=1
-BAR4LegacyIO=false
-BAR4Size=16
-BAR5=1
-BAR5LegacyIO=false
-BAR5Size=0
-BIST=0
-CacheLineSize=0
-CardbusCIS=0
-ClassCode=1
-Command=0
-DeviceID=28945
-ExpansionROM=0
-HeaderType=0
-InterruptLine=14
-InterruptPin=1
-LatencyTimer=0
-MaximumLatency=0
-MinimumGrant=0
-ProgIF=128
-Revision=0
-Status=640
-SubClassCode=1
-SubsystemID=0
-SubsystemVendorID=0
-VendorID=32902
-clk_domain=system.clk_domain
-config_latency=20000
-ctrl_offset=0
-disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
-io_shift=0
-pci_bus=0
-pci_dev=4
-pci_func=0
-pio_latency=30000
-platform=system.pc
-system=system
-config=system.piobus.master[3]
-dma=system.piobus.slave[0]
-pio=system.piobus.master[2]
-
-[system.pc.south_bridge.ide.disks0]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks0.image
-
-[system.pc.south_bridge.ide.disks0.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks0.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks0.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
-read_only=true
-
-[system.pc.south_bridge.ide.disks1]
-type=IdeDisk
-children=image
-delay=1000000
-driveID=master
-image=system.pc.south_bridge.ide.disks1.image
-
-[system.pc.south_bridge.ide.disks1.image]
-type=CowDiskImage
-children=child
-child=system.pc.south_bridge.ide.disks1.image.child
-image_file=
-read_only=false
-table_size=65536
-
-[system.pc.south_bridge.ide.disks1.image.child]
-type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
-read_only=true
-
-[system.pc.south_bridge.int_lines0]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines0.sink
-source=system.pc.south_bridge.pic1.output
-
-[system.pc.south_bridge.int_lines0.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=0
-
-[system.pc.south_bridge.int_lines1]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines1.sink
-source=system.pc.south_bridge.pic2.output
-
-[system.pc.south_bridge.int_lines1.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=2
-
-[system.pc.south_bridge.int_lines2]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines2.sink
-source=system.pc.south_bridge.cmos.int_pin
-
-[system.pc.south_bridge.int_lines2.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic2
-number=0
-
-[system.pc.south_bridge.int_lines3]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines3.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines3.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.pic1
-number=0
-
-[system.pc.south_bridge.int_lines4]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines4.sink
-source=system.pc.south_bridge.pit.int_pin
-
-[system.pc.south_bridge.int_lines4.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=2
-
-[system.pc.south_bridge.int_lines5]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines5.sink
-source=system.pc.south_bridge.keyboard.keyboard_int_pin
-
-[system.pc.south_bridge.int_lines5.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=1
-
-[system.pc.south_bridge.int_lines6]
-type=X86IntLine
-children=sink
-sink=system.pc.south_bridge.int_lines6.sink
-source=system.pc.south_bridge.keyboard.mouse_int_pin
-
-[system.pc.south_bridge.int_lines6.sink]
-type=X86IntSinkPin
-device=system.pc.south_bridge.io_apic
-number=12
-
-[system.pc.south_bridge.io_apic]
-type=I82094AA
-apic_id=2
-clk_domain=system.clk_domain
-external_int_pic=system.pc.south_bridge.pic1
-int_latency=1000
-pio_addr=4273995776
-pio_latency=100000
-system=system
-int_master=system.piobus.slave[1]
-pio=system.piobus.master[9]
-
-[system.pc.south_bridge.keyboard]
-type=I8042
-children=keyboard_int_pin mouse_int_pin
-clk_domain=system.clk_domain
-command_port=9223372036854775908
-data_port=9223372036854775904
-keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
-mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
-pio_addr=0
-pio_latency=100000
-system=system
-pio=system.piobus.master[4]
-
-[system.pc.south_bridge.keyboard.keyboard_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.keyboard.mouse_int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic1]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-mode=I8259Master
-output=system.pc.south_bridge.pic1.output
-pio_addr=9223372036854775840
-pio_latency=100000
-slave=system.pc.south_bridge.pic2
-system=system
-pio=system.piobus.master[5]
-
-[system.pc.south_bridge.pic1.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pic2]
-type=I8259
-children=output
-clk_domain=system.clk_domain
-mode=I8259Slave
-output=system.pc.south_bridge.pic2.output
-pio_addr=9223372036854775968
-pio_latency=100000
-slave=Null
-system=system
-pio=system.piobus.master[6]
-
-[system.pc.south_bridge.pic2.output]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.pit]
-type=I8254
-children=int_pin
-clk_domain=system.clk_domain
-int_pin=system.pc.south_bridge.pit.int_pin
-pio_addr=9223372036854775872
-pio_latency=100000
-system=system
-pio=system.piobus.master[7]
-
-[system.pc.south_bridge.pit.int_pin]
-type=X86IntSourcePin
-
-[system.pc.south_bridge.speaker]
-type=PcSpeaker
-clk_domain=system.clk_domain
-i8254=system.pc.south_bridge.pit
-pio_addr=9223372036854775905
-pio_latency=100000
-system=system
-pio=system.piobus.master[8]
-
-[system.physmem]
-type=SimpleDRAM
-activation_limit=4
-addr_mapping=RaBaChCo
-banks_per_rank=8
-burst_length=8
-channels=1
-clk_domain=system.clk_domain
-conf_table_reported=true
-device_bus_width=8
-device_rowbuffer_size=1024
-devices_per_rank=8
-in_addr_map=true
-mem_sched_policy=frfcfs
-null=false
-page_policy=open
-range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-static_backend_latency=10000
-static_frontend_latency=10000
-tBURST=5000
-tCL=13750
-tRCD=13750
-tREFI=7800000
-tRFC=300000
-tRP=13750
-tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_thresh_perc=70
-port=system.piobus.master[21]
-
-[system.piobus]
-type=NoncoherentBus
-clk_domain=system.clk_domain
-header_cycles=1
-use_default_range=true
-width=8
-default=system.pc.pciconfig.pio
-master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.physmem.port
-slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_port system.ruby.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 dma_cntrl0 l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network profiler
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-mem_size=134217728
-no_mem_vec=false
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=500
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=3
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-memBuffer=system.ruby.dir_cntrl0.memBuffer
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_mem_ctrl_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=5
-size=134217728
-use_map=false
-version=0
-
-[system.ruby.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-clk_domain=system.ruby.memctrl_clk_domain
-dimm_bit_0=12
-dimms_per_channel=2
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-ruby_system=system.ruby
-tFaw=0
-version=0
-
-[system.ruby.dma_cntrl0]
-type=DMA_Controller
-children=dma_sequencer
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=4
-dma_sequencer=system.ruby.dma_cntrl0.dma_sequencer
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-request_latency=6
-ruby_system=system.ruby
-transitions_per_cycle=4
-version=0
-
-[system.ruby.dma_cntrl0.dma_sequencer]
-type=DMASequencer
-access_phys_mem=true
-clk_domain=system.ruby.clk_domain
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.pc.south_bridge.ide.dma
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=0
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-to_l2_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-access_phys_mem=true
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl0.L1Dcache
-deadlock_threshold=500000
-icache=system.ruby.l1_cntrl0.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-pio_port=system.piobus.slave[2]
-slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
-
-[system.ruby.l1_cntrl1]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl1.L1Dcache
-L1Icache=system.ruby.l1_cntrl1.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=1
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl1.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl1.sequencer
-to_l2_latency=1
-transitions_per_cycle=4
-version=1
-
-[system.ruby.l1_cntrl1.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=32768
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl1.sequencer]
-type=RubySequencer
-access_phys_mem=true
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl1.L1Dcache
-deadlock_threshold=500000
-icache=system.ruby.l1_cntrl1.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-pio_port=system.piobus.slave[3]
-slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=L2cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=2
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_l1_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=15
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=4194304
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4
-number_of_virtual_networks=10
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5
-ruby_system=system.ruby
-topology=Crossbar
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl1
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l2_cntrl0
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.ext_links3]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers3
-latency=1
-link_id=3
-weight=1
-
-[system.ruby.network.ext_links4]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.dma_cntrl0
-int_node=system.ruby.network.routers4
-latency=1
-link_id=4
-weight=1
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=5
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers5
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=6
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers5
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=7
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers5
-weight=1
-
-[system.ruby.network.int_links3]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=8
-node_a=system.ruby.network.routers3
-node_b=system.ruby.network.routers5
-weight=1
-
-[system.ruby.network.int_links4]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=9
-node_a=system.ruby.network.routers4
-node_b=system.ruby.network.routers5
-weight=1
-
-[system.ruby.network.routers0]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=0
-virt_nets=10
-
-[system.ruby.network.routers1]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=1
-virt_nets=10
-
-[system.ruby.network.routers2]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=2
-virt_nets=10
-
-[system.ruby.network.routers3]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=3
-virt_nets=10
-
-[system.ruby.network.routers4]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=4
-virt_nets=10
-
-[system.ruby.network.routers5]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=5
-virt_nets=10
-
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=2
-ruby_system=system.ruby
-
-[system.smbios_table]
-type=X86SMBiosSMBiosTable
-children=structures
-major_version=2
-minor_version=5
-structures=system.smbios_table.structures
-
-[system.smbios_table.structures]
-type=X86SMBiosBiosInformation
-characteristic_ext_bytes=
-characteristics=
-emb_cont_firmware_major=0
-emb_cont_firmware_minor=0
-major=0
-minor=0
-release_date=06/08/2008
-rom_size=0
-starting_addr_segment=0
-vendor=
-version=
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-access_phys_mem=true
-clk_domain=system.clk_domain
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-voltage=1.000000
-
+++ /dev/null
-
-Profiler Stats
---------------
-Ruby_current_time: 10600871471
-Ruby_start_time: 0
-Ruby_cycles: 10600871471
-
-Busy Controller Counts:
-L1Cache-0:12 L1Cache-1:13
-L2Cache-0:2
-Directory-0:0
-DMA-0:0
-
-Busy Bank Count:0
-
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 152187620 average: 1.00011 | standard deviation: 0.0105957 | 0 152170533 17087 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-latency: [binsize: 16 max: 175 count: 152187619 average: 3.38032 | standard deviation: 3.78105 | 149532617 2479919 181 0 78486 1293 90363 3753 944 61 2 ]
-latency: LD: [binsize: 8 max: 144 count: 14921275 average: 4.75297 | standard deviation: 6.60507 | 13535742 0 1328034 25221 131 0 0 0 0 9977 145 16 20 20925 775 45 44 172 28 ]
-latency: ST: [binsize: 16 max: 175 count: 9491432 average: 4.60863 | standard deviation: 10.6418 | 9141416 224288 30 0 63466 1078 57802 2705 612 33 2 ]
-latency: IFETCH: [binsize: 8 max: 143 count: 126601627 average: 3.11268 | standard deviation: 1.65139 | 125785924 0 800296 97 4 0 0 0 0 3861 27 4 5 11094 188 17 12 98 ]
-latency: RMW_Read: [binsize: 8 max: 143 count: 494285 average: 5.89281 | standard deviation: 8.20937 | 428799 0 43439 20640 6 0 0 0 0 992 21 1 2 363 16 1 1 4 ]
-latency: Locked_RMW_Read: [binsize: 8 max: 140 count: 339500 average: 5.2378 | standard deviation: 6.75071 | 301236 0 27794 10110 10 0 0 0 0 190 1 0 0 152 6 0 0 1 ]
-latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 339500 average: 3 | standard deviation: 0 | 0 0 0 339500 ]
-hit latency: [binsize: 1 max: 3 count: 149532617 average: 3 | standard deviation: 0 | 0 0 0 149532617 ]
-hit latency: LD: [binsize: 1 max: 3 count: 13535742 average: 3 | standard deviation: 0 | 0 0 0 13535742 ]
-hit latency: ST: [binsize: 1 max: 3 count: 9141416 average: 3 | standard deviation: 0 | 0 0 0 9141416 ]
-hit latency: IFETCH: [binsize: 1 max: 3 count: 125785924 average: 3 | standard deviation: 0 | 0 0 0 125785924 ]
-hit latency: RMW_Read: [binsize: 1 max: 3 count: 428799 average: 3 | standard deviation: 0 | 0 0 0 428799 ]
-hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 301236 average: 3 | standard deviation: 0 | 0 0 0 301236 ]
-hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 339500 average: 3 | standard deviation: 0 | 0 0 0 339500 ]
-miss latency: [binsize: 16 max: 175 count: 2655002 average: 24.8002 | standard deviation: 18.7757 | 0 2479919 181 0 78486 1293 90363 3753 944 61 2 ]
-miss latency: LD: [binsize: 8 max: 144 count: 1385533 average: 21.8783 | standard deviation: 12.1052 | 0 0 1328034 25221 131 0 0 0 0 9977 145 16 20 20925 775 45 44 172 28 ]
-miss latency: ST: [binsize: 16 max: 175 count: 350016 average: 46.6216 | standard deviation: 35.1891 | 0 224288 30 0 63466 1078 57802 2705 612 33 2 ]
-miss latency: IFETCH: [binsize: 8 max: 143 count: 815703 average: 20.4881 | standard deviation: 10.9268 | 0 0 800296 97 4 0 0 0 0 3861 27 4 5 11094 188 17 12 98 ]
-miss latency: RMW_Read: [binsize: 8 max: 143 count: 65486 average: 24.8348 | standard deviation: 9.75142 | 0 0 43439 20640 6 0 0 0 0 992 21 1 2 363 16 1 1 4 ]
-miss latency: Locked_RMW_Read: [binsize: 8 max: 140 count: 38264 average: 22.855 | standard deviation: 7.38587 | 0 0 27794 10110 10 0 0 0 0 190 1 0 0 152 6 0 0 1 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 13 count: 10855755 average: 0.221686 | standard deviation: 0.915908 | 10253393 1133 685 941 598385 739 87 93 74 159 8 10 6 42 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6093680 average: 0.377613 | standard deviation: 1.1709 | 5518533 548 185 218 573099 623 85 91 73 159 8 10 6 42 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 8 count: 4681410 average: 0.022308 | standard deviation: 0.296312 | 4654609 478 413 621 25188 96 2 2 1 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 5 count: 80665 average: 0.0133763 | standard deviation: 0.206119 | 80251 107 87 102 98 20 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+++ /dev/null
-warn: add_child('terminal'): child 'terminal' already has parent
-warn: Sockets disabled, not accepting terminal connections
-warn: Reading current count from inactive timer.
-warn: Sockets disabled, not accepting gdb connections
-warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0x8086
-warn: instruction 'wbinvd' unimplemented
-warn: instruction 'wbinvd' unimplemented
-warn: x86 cpuid: unknown family 0x8086
-hack: Assuming logical destinations are 1 << id.
-warn: Tried to clear PCI interrupt 14
-warn: Unknown mouse command 0xe1.
-hack: be nice to actually delete the event here
+++ /dev/null
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Oct 16 2013 01:55:52
-gem5 started Oct 16 2013 01:57:05
-gem5 executing on zizzer
-command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5304492233500 because m5_exit instruction encountered
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 5.300436 # Number of seconds simulated
-sim_ticks 5300435735500 # Number of ticks simulated
-final_tick 5300435735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 137756 # Simulator instruction rate (inst/s)
-host_op_rate 264143 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6834713129 # Simulator tick rate (ticks/s)
-host_mem_usage 828636 # Number of bytes of host memory used
-host_seconds 775.52 # Real time elapsed on the host
-sim_insts 106831806 # Number of instructions simulated
-sim_ops 204847037 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 542427168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 38705697 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 101016 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 45856 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 470385848 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 54943175 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1106827384 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 542427168 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 470385848 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1012813016 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 31534134 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 36447890 # Number of bytes written to this memory
-system.physmem.bytes_written::total 70973144 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 814 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 15245 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 7685 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 67803396 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 6494255 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 12627 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 5732 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 58798231 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9219516 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 142357501 # Number of read requests responded to by this memory
-system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4739560 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 5091370 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 9877668 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 6638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 23009 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 11599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 102336335 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 7302361 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 19058 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 8651 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 88744751 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 10365785 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 208818188 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 102336335 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 88744751 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 191081086 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 564313 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 5949347 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 6876395 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13390058 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 570951 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 23009 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 11602 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 102336335 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 13251709 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 19058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 8651 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 88744751 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 17242180 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 222208246 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 0 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 0 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 0 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 0 # Per bank write bursts
-system.physmem.perBankRdBursts::1 0 # Per bank write bursts
-system.physmem.perBankRdBursts::2 0 # Per bank write bursts
-system.physmem.perBankRdBursts::3 0 # Per bank write bursts
-system.physmem.perBankRdBursts::4 0 # Per bank write bursts
-system.physmem.perBankRdBursts::5 0 # Per bank write bursts
-system.physmem.perBankRdBursts::6 0 # Per bank write bursts
-system.physmem.perBankRdBursts::7 0 # Per bank write bursts
-system.physmem.perBankRdBursts::8 0 # Per bank write bursts
-system.physmem.perBankRdBursts::9 0 # Per bank write bursts
-system.physmem.perBankRdBursts::10 0 # Per bank write bursts
-system.physmem.perBankRdBursts::11 0 # Per bank write bursts
-system.physmem.perBankRdBursts::12 0 # Per bank write bursts
-system.physmem.perBankRdBursts::13 0 # Per bank write bursts
-system.physmem.perBankRdBursts::14 0 # Per bank write bursts
-system.physmem.perBankRdBursts::15 0 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 0 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 0 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
-system.physmem.totQLat 0 # Total ticks spent queuing
-system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 0 # Total ticks spent in databus transfers
-system.physmem.totBankLat 0 # Total ticks spent accessing banks
-system.physmem.avgQLat nan # Average queueing delay per DRAM burst
-system.physmem.avgBankLat nan # Average bank access latency per DRAM burst
-system.physmem.avgBusLat nan # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 0.00 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.00 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 0 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate nan # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap nan # Average gap between requests
-system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined
-system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state
-system.piobus.throughput 386047 # Throughput (bytes/s)
-system.piobus.trans_dist::ReadReq 863424 # Transaction distribution
-system.piobus.trans_dist::ReadResp 863424 # Transaction distribution
-system.piobus.trans_dist::WriteReq 37806 # Transaction distribution
-system.piobus.trans_dist::WriteResp 37806 # Transaction distribution
-system.piobus.trans_dist::MessageReq 1919 # Transaction distribution
-system.piobus.trans_dist::MessageResp 1919 # Transaction distribution
-system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1644 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 5246 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 984 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 14276 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 748688 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1711608 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 5796 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 33204 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 350 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 33292 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 12392 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 5218 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 90852 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 244 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 244 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 250 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 250 # Packet count per connected master and slave (bytes)
-system.piobus.pkt_count::total 1806298 # Packet count per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3288 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 2968 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1968 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 7138 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1497370 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1983945 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3692 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 16602 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 700 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 16646 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6196 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 10433 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 54595 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 488 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 488 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 500 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 500 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.tot_pkt_size::total 2046216 # Cumulative packet size per connected master and slave (bytes)
-system.piobus.data_through_bus 2046216 # Total data (bytes)
-system.piobus.reqLayer0.occupancy 48000 # Layer occupancy (ticks)
-system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks)
-system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer2.occupancy 10168500 # Layer occupancy (ticks)
-system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer3.occupancy 154000 # Layer occupancy (ticks)
-system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer4.occupancy 1061500 # Layer occupancy (ticks)
-system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks)
-system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer6.occupancy 56000 # Layer occupancy (ticks)
-system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer7.occupancy 22164500 # Layer occupancy (ticks)
-system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks)
-system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer9.occupancy 1295000 # Layer occupancy (ticks)
-system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer10.occupancy 41706500 # Layer occupancy (ticks)
-system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer11.occupancy 2500 # Layer occupancy (ticks)
-system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer12.occupancy 23281500 # Layer occupancy (ticks)
-system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
-system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
-system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
-system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer16.occupancy 11000 # Layer occupancy (ticks)
-system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer17.occupancy 470677500 # Layer occupancy (ticks)
-system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer18.occupancy 2359248 # Layer occupancy (ticks)
-system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer19.occupancy 5486500 # Layer occupancy (ticks)
-system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer20.occupancy 2285216 # Layer occupancy (ticks)
-system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.piobus.reqLayer22.occupancy 1083000 # Layer occupancy (ticks)
-system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer0.occupancy 2422464 # Layer occupancy (ticks)
-system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer1.occupancy 1917192500 # Layer occupancy (ticks)
-system.piobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer2.occupancy 72612500 # Layer occupancy (ticks)
-system.piobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer3.occupancy 151500 # Layer occupancy (ticks)
-system.piobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.piobus.respLayer4.occupancy 151500 # Layer occupancy (ticks)
-system.piobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 10730814 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 525933 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11256747 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 67479144 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 324252 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 67803396 # Number of cache demand accesses
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 13015879 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313366 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14329245 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 58306780 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 491451 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 58798231 # Number of cache demand accesses
-system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l2_cntrl0.L2cache.demand_hits 2431660 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 223342 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 2655002 # Number of cache demand accesses
-system.ruby.network.routers0.percent_links_utilized 0.029766
-system.ruby.network.routers0.msg_count.Control::0 850185
-system.ruby.network.routers0.msg_count.Request_Control::0 42201
-system.ruby.network.routers0.msg_count.Response_Data::1 878303
-system.ruby.network.routers0.msg_count.Response_Control::1 503569
-system.ruby.network.routers0.msg_count.Response_Control::2 500391
-system.ruby.network.routers0.msg_count.Writeback_Data::0 294658
-system.ruby.network.routers0.msg_count.Writeback_Data::1 77
-system.ruby.network.routers0.msg_count.Writeback_Control::0 168208
-system.ruby.network.routers0.msg_bytes.Control::0 6801480
-system.ruby.network.routers0.msg_bytes.Request_Control::0 337608
-system.ruby.network.routers0.msg_bytes.Response_Data::1 63237816
-system.ruby.network.routers0.msg_bytes.Response_Control::1 4028552
-system.ruby.network.routers0.msg_bytes.Response_Control::2 4003128
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21215376
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5544
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1345664
-system.ruby.network.routers1.percent_links_utilized 0.057219
-system.ruby.network.routers1.msg_count.Control::0 1804817
-system.ruby.network.routers1.msg_count.Request_Control::0 38464
-system.ruby.network.routers1.msg_count.Response_Data::1 1828188
-system.ruby.network.routers1.msg_count.Response_Control::1 1255906
-system.ruby.network.routers1.msg_count.Response_Control::2 1256121
-system.ruby.network.routers1.msg_count.Writeback_Data::0 279078
-system.ruby.network.routers1.msg_count.Writeback_Data::1 227
-system.ruby.network.routers1.msg_count.Writeback_Control::0 940222
-system.ruby.network.routers1.msg_bytes.Control::0 14438536
-system.ruby.network.routers1.msg_bytes.Request_Control::0 307712
-system.ruby.network.routers1.msg_bytes.Response_Data::1 131629536
-system.ruby.network.routers1.msg_bytes.Response_Control::1 10047248
-system.ruby.network.routers1.msg_bytes.Response_Control::2 10048968
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20093616
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 16344
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7521776
-system.ruby.network.routers2.percent_links_utilized 0.091302
-system.ruby.network.routers2.msg_count.Control::0 2829904
-system.ruby.network.routers2.msg_count.Request_Control::0 78999
-system.ruby.network.routers2.msg_count.Response_Data::1 2881954
-system.ruby.network.routers2.msg_count.Response_Control::1 1837374
-system.ruby.network.routers2.msg_count.Response_Control::2 1756512
-system.ruby.network.routers2.msg_count.Writeback_Data::0 573736
-system.ruby.network.routers2.msg_count.Writeback_Data::1 304
-system.ruby.network.routers2.msg_count.Writeback_Control::0 1108430
-system.ruby.network.routers2.msg_bytes.Control::0 22639232
-system.ruby.network.routers2.msg_bytes.Request_Control::0 631992
-system.ruby.network.routers2.msg_bytes.Response_Data::1 207500688
-system.ruby.network.routers2.msg_bytes.Response_Control::1 14698992
-system.ruby.network.routers2.msg_bytes.Response_Control::2 14052096
-system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41308992
-system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888
-system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867440
-system.ruby.dir_cntrl0.memBuffer.memReq 317877 # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead 175365 # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite 142512 # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh 714764 # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles 943121 # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ 39 # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ 6636 # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls 949796 # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.987936 # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy 931605 # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy 8278 # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 95 # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait 3135 # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.23% 3.23% | 9701 3.05% 6.29% | 9679 3.04% 9.33% | 9712 3.06% 12.39% | 10010 3.15% 15.54% | 9927 3.12% 18.66% | 9854 3.10% 21.76% | 9702 3.05% 24.81% | 9904 3.12% 27.93% | 9752 3.07% 30.99% | 9805 3.08% 34.08% | 9914 3.12% 37.20% | 9948 3.13% 40.33% | 9724 3.06% 43.39% | 9647 3.03% 46.42% | 8750 2.75% 49.17% | 10266 3.23% 52.40% | 9887 3.11% 55.51% | 9844 3.10% 58.61% | 9758 3.07% 61.68% | 10022 3.15% 64.83% | 9879 3.11% 67.94% | 9766 3.07% 71.01% | 9852 3.10% 74.11% | 10073 3.17% 77.28% | 9931 3.12% 80.40% | 10177 3.20% 83.61% | 10769 3.39% 86.99% | 10605 3.34% 90.33% | 10522 3.31% 93.64% | 10506 3.31% 96.95% | 9709 3.05% 100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total 317877 # Number of accesses per bank
-
-system.ruby.network.routers3.percent_links_utilized 0.006727
-system.ruby.network.routers3.msg_count.Control::0 174902
-system.ruby.network.routers3.msg_count.Response_Data::1 273157
-system.ruby.network.routers3.msg_count.Response_Control::1 125035
-system.ruby.network.routers3.msg_count.Writeback_Control::0 47550
-system.ruby.network.routers3.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers3.msg_bytes.Control::0 1399216
-system.ruby.network.routers3.msg_bytes.Response_Data::1 19667304
-system.ruby.network.routers3.msg_bytes.Response_Control::1 1000280
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380400
-system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers4.percent_links_utilized 0.000240
-system.ruby.network.routers4.msg_count.Response_Data::1 814
-system.ruby.network.routers4.msg_count.Writeback_Control::0 47550
-system.ruby.network.routers4.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers4.msg_bytes.Response_Data::1 58608
-system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380400
-system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers5.percent_links_utilized 0.037052
-system.ruby.network.routers5.msg_count.Control::0 2829904
-system.ruby.network.routers5.msg_count.Request_Control::0 80665
-system.ruby.network.routers5.msg_count.Response_Data::1 2931208
-system.ruby.network.routers5.msg_count.Response_Control::1 1860942
-system.ruby.network.routers5.msg_count.Response_Control::2 1756512
-system.ruby.network.routers5.msg_count.Writeback_Data::0 573736
-system.ruby.network.routers5.msg_count.Writeback_Data::1 304
-system.ruby.network.routers5.msg_count.Writeback_Control::0 1155980
-system.ruby.network.routers5.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers5.msg_bytes.Control::0 22639232
-system.ruby.network.routers5.msg_bytes.Request_Control::0 645320
-system.ruby.network.routers5.msg_bytes.Response_Data::1 211046976
-system.ruby.network.routers5.msg_bytes.Response_Control::1 14887536
-system.ruby.network.routers5.msg_bytes.Response_Control::2 14052096
-system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41308992
-system.ruby.network.routers5.msg_bytes.Writeback_Data::1 21888
-system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9247840
-system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.msg_count.Control 8489712
-system.ruby.network.msg_count.Request_Control 240329
-system.ruby.network.msg_count.Response_Data 8793624
-system.ruby.network.msg_count.Response_Control 10852362
-system.ruby.network.msg_count.Writeback_Data 1722120
-system.ruby.network.msg_count.Writeback_Control 3608148
-system.ruby.network.msg_byte.Control 67917696
-system.ruby.network.msg_byte.Request_Control 1922632
-system.ruby.network.msg_byte.Response_Data 633140928
-system.ruby.network.msg_byte.Response_Control 86818896
-system.ruby.network.msg_byte.Writeback_Data 123992640
-system.ruby.network.msg_byte.Writeback_Control 28865184
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.numCycles 10600871471 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 58268800 # Number of instructions committed
-system.cpu0.committedOps 112064452 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 105032474 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu0.num_func_calls 986042 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 9969773 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 105032474 # number of integer instructions
-system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 197859045 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 89264580 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 60358670 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 43636307 # number of times the CC registers were written
-system.cpu0.num_mem_refs 12087584 # number of memory refs
-system.cpu0.num_load_insts 7337910 # Number of load instructions
-system.cpu0.num_store_insts 4749674 # Number of store instructions
-system.cpu0.num_idle_cycles 10090453891.750097 # Number of idle cycles
-system.cpu0.num_busy_cycles 510417579.249904 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.048149 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.951851 # Percentage of idle cycles
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.numCycles 10598039537 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 48563006 # Number of instructions committed
-system.cpu1.committedOps 92782585 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 89102881 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu1.num_func_calls 1756991 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 8282210 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 89102881 # number of integer instructions
-system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 172889449 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 73679026 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 51236507 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 33066238 # number of times the CC registers were written
-system.cpu1.num_mem_refs 14350514 # number of memory refs
-system.cpu1.num_load_insts 9231964 # Number of load instructions
-system.cpu1.num_store_insts 5118550 # Number of store instructions
-system.cpu1.num_idle_cycles 10261752317.862694 # Number of idle cycles
-system.cpu1.num_busy_cycles 336287219.137307 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.031731 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.968269 # Percentage of idle cycles
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.ruby.network.routers0.throttle0.link_utilization 0.038081
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 42201
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 838238
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 487495
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 337608
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 60353136
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3899960
-system.ruby.network.routers0.throttle1.link_utilization 0.021451
-system.ruby.network.routers0.throttle1.msg_count.Control::0 850185
-system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40065
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 16074
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 500391
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 294658
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 77
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 168208
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 6801480
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2884680
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 128592
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4003128
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 21215376
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 5544
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1345664
-system.ruby.network.routers1.throttle0.link_utilization 0.082224
-system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 38464
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1794944
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 1240059
-system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 307712
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 129235968
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 9920472
-system.ruby.network.routers1.throttle1.link_utilization 0.032214
-system.ruby.network.routers1.throttle1.msg_count.Control::0 1804817
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 33244
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 15847
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1256121
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 279078
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 227
-system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 940222
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0 14438536
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 2393568
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 126776
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 10048968
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 20093616
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 16344
-system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7521776
-system.ruby.network.routers2.throttle0.link_utilization 0.059452
-system.ruby.network.routers2.throttle0.msg_count.Control::0 2655002
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 199771
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 120599
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::2 1756512
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::0 573736
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 304
-system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::0 1108430
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0 21240016
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 14383512
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 964792
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::2 14052096
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::0 41308992
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::1 21888
-system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8867440
-system.ruby.network.routers2.throttle1.link_utilization 0.123152
-system.ruby.network.routers2.throttle1.msg_count.Control::0 174902
-system.ruby.network.routers2.throttle1.msg_count.Request_Control::0 78999
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 2682183
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1716775
-system.ruby.network.routers2.throttle1.msg_bytes.Control::0 1399216
-system.ruby.network.routers2.throttle1.msg_bytes.Request_Control::0 631992
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 193117176
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13734200
-system.ruby.network.routers3.throttle0.link_utilization 0.005246
-system.ruby.network.routers3.throttle0.msg_count.Control::0 174902
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 97441
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 12789
-system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 47550
-system.ruby.network.routers3.throttle0.msg_bytes.Control::0 1399216
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 7015752
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 102312
-system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380400
-system.ruby.network.routers3.throttle1.link_utilization 0.008209
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 175716
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 112246
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12651552
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 897968
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers4.throttle0.link_utilization 0.000255
-system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 814
-system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58608
-system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888
-system.ruby.network.routers4.throttle1.link_utilization 0.000224
-system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47550
-system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380400
-system.ruby.network.routers5.throttle0.link_utilization 0.038081
-system.ruby.network.routers5.throttle0.msg_count.Request_Control::0 42201
-system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 838238
-system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 487495
-system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::0 337608
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 60353136
-system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 3899960
-system.ruby.network.routers5.throttle1.link_utilization 0.082224
-system.ruby.network.routers5.throttle1.msg_count.Request_Control::0 38464
-system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 1794944
-system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 1240059
-system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::0 307712
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 129235968
-system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 9920472
-system.ruby.network.routers5.throttle2.link_utilization 0.059452
-system.ruby.network.routers5.throttle2.msg_count.Control::0 2655002
-system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 199771
-system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 120599
-system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1756512
-system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 573736
-system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 304
-system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 1108430
-system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21240016
-system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 14383512
-system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 964792
-system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14052096
-system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 41308992
-system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 21888
-system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 8867440
-system.ruby.network.routers5.throttle3.link_utilization 0.005246
-system.ruby.network.routers5.throttle3.msg_count.Control::0 174902
-system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 97441
-system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12789
-system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0 47550
-system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1399216
-system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 7015752
-system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 102312
-system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380400
-system.ruby.network.routers5.throttle4.link_utilization 0.000255
-system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 814
-system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736
-system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58608
-system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888
-system.ruby.l1_cntrl0.Load | 6084593 40.78% 40.78% | 8836682 59.22% 100.00%
-system.ruby.l1_cntrl0.Load::total 14921275
-
-system.ruby.l1_cntrl0.Ifetch | 67803399 53.56% 53.56% | 58798232 46.44% 100.00%
-system.ruby.l1_cntrl0.Ifetch::total 126601631
-
-system.ruby.l1_cntrl0.Store | 5172154 48.50% 48.50% | 5492563 51.50% 100.00%
-system.ruby.l1_cntrl0.Store::total 10664717
-
-system.ruby.l1_cntrl0.Inv | 16151 50.12% 50.12% | 16074 49.88% 100.00%
-system.ruby.l1_cntrl0.Inv::total 32225
-
-system.ruby.l1_cntrl0.L1_Replacement | 823061 31.64% 31.64% | 1778014 68.36% 100.00%
-system.ruby.l1_cntrl0.L1_Replacement::total 2601075
-
-system.ruby.l1_cntrl0.Fwd_GETX | 12035 51.06% 51.06% | 11536 48.94% 100.00%
-system.ruby.l1_cntrl0.Fwd_GETX::total 23571
-
-system.ruby.l1_cntrl0.Fwd_GETS | 14011 56.35% 56.35% | 10854 43.65% 100.00%
-system.ruby.l1_cntrl0.Fwd_GETS::total 24865
-
-system.ruby.l1_cntrl0.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 4
-
-system.ruby.l1_cntrl0.Data | 735 42.05% 42.05% | 1013 57.95% 100.00%
-system.ruby.l1_cntrl0.Data::total 1748
-
-system.ruby.l1_cntrl0.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00%
-system.ruby.l1_cntrl0.Data_Exclusive::total 1277877
-
-system.ruby.l1_cntrl0.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00%
-system.ruby.l1_cntrl0.DataS_fromL1::total 24869
-
-system.ruby.l1_cntrl0.Data_all_Acks | 576364 43.38% 43.38% | 752324 56.62% 100.00%
-system.ruby.l1_cntrl0.Data_all_Acks::total 1328688
-
-system.ruby.l1_cntrl0.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00%
-system.ruby.l1_cntrl0.Ack::total 21820
-
-system.ruby.l1_cntrl0.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00%
-system.ruby.l1_cntrl0.Ack_all::total 23568
-
-system.ruby.l1_cntrl0.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00%
-system.ruby.l1_cntrl0.WB_Ack::total 1682166
-
-system.ruby.l1_cntrl0.NP.Load | 278296 20.36% 20.36% | 1088636 79.64% 100.00%
-system.ruby.l1_cntrl0.NP.Load::total 1366932
-
-system.ruby.l1_cntrl0.NP.Ifetch | 324154 39.75% 39.75% | 491322 60.25% 100.00%
-system.ruby.l1_cntrl0.NP.Ifetch::total 815476
-
-system.ruby.l1_cntrl0.NP.Store | 221635 52.68% 52.68% | 199080 47.32% 100.00%
-system.ruby.l1_cntrl0.NP.Store::total 420715
-
-system.ruby.l1_cntrl0.NP.Inv | 5298 59.24% 59.24% | 3645 40.76% 100.00%
-system.ruby.l1_cntrl0.NP.Inv::total 8943
-
-system.ruby.l1_cntrl0.I.Load | 8385 45.08% 45.08% | 10216 54.92% 100.00%
-system.ruby.l1_cntrl0.I.Load::total 18601
-
-system.ruby.l1_cntrl0.I.Ifetch | 98 43.17% 43.17% | 129 56.83% 100.00%
-system.ruby.l1_cntrl0.I.Ifetch::total 227
-
-system.ruby.l1_cntrl0.I.Store | 5670 50.49% 50.49% | 5561 49.51% 100.00%
-system.ruby.l1_cntrl0.I.Store::total 11231
-
-system.ruby.l1_cntrl0.I.L1_Replacement | 8735 52.29% 52.29% | 7971 47.71% 100.00%
-system.ruby.l1_cntrl0.I.L1_Replacement::total 16706
-
-system.ruby.l1_cntrl0.S.Load | 550458 51.55% 51.55% | 517421 48.45% 100.00%
-system.ruby.l1_cntrl0.S.Load::total 1067879
-
-system.ruby.l1_cntrl0.S.Ifetch | 67479144 53.65% 53.65% | 58306780 46.35% 100.00%
-system.ruby.l1_cntrl0.S.Ifetch::total 125785924
-
-system.ruby.l1_cntrl0.S.Store | 11947 54.75% 54.75% | 9873 45.25% 100.00%
-system.ruby.l1_cntrl0.S.Store::total 21820
-
-system.ruby.l1_cntrl0.S.Inv | 10719 46.81% 46.81% | 12178 53.19% 100.00%
-system.ruby.l1_cntrl0.S.Inv::total 22897
-
-system.ruby.l1_cntrl0.S.L1_Replacement | 351460 38.96% 38.96% | 550743 61.04% 100.00%
-system.ruby.l1_cntrl0.S.L1_Replacement::total 902203
-
-system.ruby.l1_cntrl0.E.Load | 1120786 29.13% 29.13% | 2726694 70.87% 100.00%
-system.ruby.l1_cntrl0.E.Load::total 3847480
-
-system.ruby.l1_cntrl0.E.Store | 80619 48.39% 48.39% | 85992 51.61% 100.00%
-system.ruby.l1_cntrl0.E.Store::total 166611
-
-system.ruby.l1_cntrl0.E.Inv | 57 70.37% 70.37% | 24 29.63% 100.00%
-system.ruby.l1_cntrl0.E.Inv::total 81
-
-system.ruby.l1_cntrl0.E.L1_Replacement | 168208 15.18% 15.18% | 940222 84.82% 100.00%
-system.ruby.l1_cntrl0.E.L1_Replacement::total 1108430
-
-system.ruby.l1_cntrl0.E.Fwd_GETX | 208 58.92% 58.92% | 145 41.08% 100.00%
-system.ruby.l1_cntrl0.E.Fwd_GETX::total 353
-
-system.ruby.l1_cntrl0.E.Fwd_GETS | 1001 46.45% 46.45% | 1154 53.55% 100.00%
-system.ruby.l1_cntrl0.E.Fwd_GETS::total 2155
-
-system.ruby.l1_cntrl0.M.Load | 4126668 47.87% 47.87% | 4493715 52.13% 100.00%
-system.ruby.l1_cntrl0.M.Load::total 8620383
-
-system.ruby.l1_cntrl0.M.Store | 4852283 48.31% 48.31% | 5192057 51.69% 100.00%
-system.ruby.l1_cntrl0.M.Store::total 10044340
-
-system.ruby.l1_cntrl0.M.Inv | 77 25.33% 25.33% | 227 74.67% 100.00%
-system.ruby.l1_cntrl0.M.Inv::total 304
-
-system.ruby.l1_cntrl0.M.L1_Replacement | 294658 51.36% 51.36% | 279078 48.64% 100.00%
-system.ruby.l1_cntrl0.M.L1_Replacement::total 573736
-
-system.ruby.l1_cntrl0.M.Fwd_GETX | 11827 50.94% 50.94% | 11391 49.06% 100.00%
-system.ruby.l1_cntrl0.M.Fwd_GETX::total 23218
-
-system.ruby.l1_cntrl0.M.Fwd_GETS | 13010 57.29% 57.29% | 9700 42.71% 100.00%
-system.ruby.l1_cntrl0.M.Fwd_GETS::total 22710
-
-system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
-system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4
-
-system.ruby.l1_cntrl0.IS.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00%
-system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1277877
-
-system.ruby.l1_cntrl0.IS.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00%
-system.ruby.l1_cntrl0.IS.DataS_fromL1::total 24869
-
-system.ruby.l1_cntrl0.IS.Data_all_Acks | 349794 38.93% 38.93% | 548696 61.07% 100.00%
-system.ruby.l1_cntrl0.IS.Data_all_Acks::total 898490
-
-system.ruby.l1_cntrl0.IM.Data | 735 42.05% 42.05% | 1013 57.95% 100.00%
-system.ruby.l1_cntrl0.IM.Data::total 1748
-
-system.ruby.l1_cntrl0.IM.Data_all_Acks | 226570 52.67% 52.67% | 203628 47.33% 100.00%
-system.ruby.l1_cntrl0.IM.Data_all_Acks::total 430198
-
-system.ruby.l1_cntrl0.SM.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00%
-system.ruby.l1_cntrl0.SM.Ack::total 21820
-
-system.ruby.l1_cntrl0.SM.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00%
-system.ruby.l1_cntrl0.SM.Ack_all::total 23568
-
-system.ruby.l1_cntrl0.M_I.Ifetch | 3 75.00% 75.00% | 1 25.00% 100.00%
-system.ruby.l1_cntrl0.M_I.Ifetch::total 4
-
-system.ruby.l1_cntrl0.M_I.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00%
-system.ruby.l1_cntrl0.M_I.WB_Ack::total 1682166
-
-system.ruby.l2_cntrl0.L1_GET_INSTR 815703 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETS 1385690 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETX 431947 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_UPGRADE 21820 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_PUTX 1682166 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement 95350 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement_clean 12864 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Data 174902 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Ack 110230 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data 23018 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data_clean 2155 0.00% 0.00%
-system.ruby.l2_cntrl0.Ack 1666 0.00% 0.00%
-system.ruby.l2_cntrl0.Ack_all 6687 0.00% 0.00%
-system.ruby.l2_cntrl0.Unblock 24869 0.00% 0.00%
-system.ruby.l2_cntrl0.Exclusive_Unblock 1731643 0.00% 0.00%
-system.ruby.l2_cntrl0.MEM_Inv 4032 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15306 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETS 32147 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETX 127449 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GET_INSTR 800365 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GETS 82791 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GETX 1783 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_UPGRADE 21820 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L2_Replacement 268 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6335 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.MEM_Inv 3 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GET_INSTR 28 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETS 1245730 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETX 279143 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement 94921 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement_clean 6421 0.00% 0.00%
-system.ruby.l2_cntrl0.M.MEM_Inv 1897 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_GETS 24865 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_GETX 23571 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_PUTX 1682166 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement 161 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement_clean 108 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.MEM_Inv 116 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.Mem_Ack 110230 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.MEM_Inv 1897 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.WB_Data 229 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.Ack_all 48 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.MEM_Inv 116 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.WB_Data 75 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.Ack_all 33 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.Ack 1395 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.Ack_all 6335 0.00% 0.00%
-system.ruby.l2_cntrl0.S_I.Ack 271 0.00% 0.00%
-system.ruby.l2_cntrl0.S_I.Ack_all 271 0.00% 0.00%
-system.ruby.l2_cntrl0.S_I.MEM_Inv 3 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.Mem_Data 32147 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.Mem_Data 15306 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.Mem_Data 127449 0.00% 0.00%
-system.ruby.l2_cntrl0.SS_MB.L1_GETS 119 0.00% 0.00%
-system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 23603 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_GETS 38 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_GETX 1 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1708040 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.WB_Data 22711 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 2155 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.Unblock 3 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IB.WB_Data 3 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_SB.Unblock 24866 0.00% 0.00%
-system.ruby.dma_cntrl0.ReadRequest 814 0.00% 0.00%
-system.ruby.dma_cntrl0.WriteRequest 46736 0.00% 0.00%
-system.ruby.dma_cntrl0.Data 814 0.00% 0.00%
-system.ruby.dma_cntrl0.Ack 46736 0.00% 0.00%
-system.ruby.dma_cntrl0.READY.ReadRequest 814 0.00% 0.00%
-system.ruby.dma_cntrl0.READY.WriteRequest 46736 0.00% 0.00%
-system.ruby.dma_cntrl0.BUSY_RD.Data 814 0.00% 0.00%
-system.ruby.dma_cntrl0.BUSY_WR.Ack 46736 0.00% 0.00%
-system.ruby.dir_cntrl0.Fetch 174902 0.00% 0.00%
-system.ruby.dir_cntrl0.Data 97441 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Data 175365 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Ack 142512 0.00% 0.00%
-system.ruby.dir_cntrl0.DMA_READ 814 0.00% 0.00%
-system.ruby.dir_cntrl0.DMA_WRITE 46736 0.00% 0.00%
-system.ruby.dir_cntrl0.CleanReplacement 12789 0.00% 0.00%
-system.ruby.dir_cntrl0.I.Fetch 174902 0.00% 0.00%
-system.ruby.dir_cntrl0.I.DMA_READ 463 0.00% 0.00%
-system.ruby.dir_cntrl0.I.DMA_WRITE 45071 0.00% 0.00%
-system.ruby.dir_cntrl0.ID.Memory_Data 463 0.00% 0.00%
-system.ruby.dir_cntrl0.ID_W.Memory_Ack 45071 0.00% 0.00%
-system.ruby.dir_cntrl0.M.Data 95425 0.00% 0.00%
-system.ruby.dir_cntrl0.M.DMA_READ 351 0.00% 0.00%
-system.ruby.dir_cntrl0.M.DMA_WRITE 1665 0.00% 0.00%
-system.ruby.dir_cntrl0.M.CleanReplacement 12789 0.00% 0.00%
-system.ruby.dir_cntrl0.IM.Memory_Data 174902 0.00% 0.00%
-system.ruby.dir_cntrl0.MI.Memory_Ack 95425 0.00% 0.00%
-system.ruby.dir_cntrl0.M_DRD.Data 351 0.00% 0.00%
-system.ruby.dir_cntrl0.M_DRDI.Memory_Ack 351 0.00% 0.00%
-system.ruby.dir_cntrl0.M_DWR.Data 1665 0.00% 0.00%
-system.ruby.dir_cntrl0.M_DWRI.Memory_Ack 1665 0.00% 0.00%
-
----------- End Simulation Statistics ----------
+++ /dev/null
-Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009\r
-Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-BIOS-provided physical RAM map:\r
- BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
- BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
- BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
- BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
-end_pfn_map = 1048576\r
-kernel direct mapping tables up to 100000000 @ 8000-d000\r
-DMI 2.5 present.\r
-Zone PFN ranges:\r
- DMA 0 -> 4096\r
- DMA32 4096 -> 1048576\r
- Normal 1048576 -> 1048576\r
-early_node_map[2] active PFN ranges\r
- 0: 0 -> 159\r
- 0: 256 -> 32768\r
-Intel MultiProcessor Specification v1.4\r
-MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
-Processor #0 (Bootup-CPU)\r
-Processor #1\r
-I/O APIC #2 at 0xFEC00000.\r
-Setting APIC routing to flat\r
-Processors: 2\r
-Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)\r
-PERCPU: Allocating 34160 bytes of per cpu data\r
-Built 1 zonelists. Total pages: 30615\r
-Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
-Initializing CPU#0\r
-PID hash table entries: 512 (order: 9, 4096 bytes)\r
-Marking TSC unstable due to TSCs unsynchronized\r
-time.c: Detected 2000.000 MHz processor.\r
-Console: colour dummy device 80x25\r
-console handover: boot [earlyser0] -> real [ttyS0]\r
-Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
-Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
-Checking aperture...\r
-Memory: 122004k/131072k available (3699k kernel code, 8516k reserved, 1767k data, 248k init)\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-Mount-cache hash table entries: 256\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-Freeing SMP alternatives: 34k freed\r
-Using local APIC timer interrupts.\r
-result 7812500\r
-Detected 7.812 MHz APIC timer.\r
-Booting processor 1/2 APIC 0x1\r
-Initializing CPU#1\r
-Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
-CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
-CPU: L2 Cache: 1024K (64 bytes/line)\r
-Fake M5 x86_64 CPU stepping 01\r
-Brought up 2 CPUs\r
-migration_cost=11\r
-NET: Registered protocol family 16\r
-PCI: Using configuration type 1\r
-SCSI subsystem initialized\r
-usbcore: registered new interface driver usbfs\r
-usbcore: registered new interface driver hub\r
-usbcore: registered new device driver usb\r
-PCI: Probing PCI hardware\r
-PCI-GART: No AMD northbridge found.\r
-NET: Registered protocol family 2\r
-IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
-TCP established hash table entries: 4096 (order: 4, 98304 bytes)\r
-TCP bind hash table entries: 4096 (order: 4, 65536 bytes)\r
-TCP: Hash tables configured (established 4096 bind 4096)\r
-TCP reno registered\r
-Total HugeTLB memory allocated, 0\r
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
-io scheduler noop registered\r
-io scheduler deadline registered\r
-io scheduler cfq registered (default)\r
-Real Time Clock Driver v1.12ac\r
-Linux agpgart interface v0.102 (c) Dave Jones\r
-Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
-serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
-floppy0: no floppy controllers found\r
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
-loop: module loaded\r
-Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
-Copyright (c) 1999-2006 Intel Corporation.\r
-e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
-e100: Copyright(c) 1999-2006 Intel Corporation\r
-forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
-tun: Universal TUN/TAP device driver, 1.6\r
-tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
-netconsole: not configured, aborting\r
-Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
-ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
-PIIX4: IDE controller at PCI slot 0000:00:04.0\r
-PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
-PIIX4: chipset revision 0\r
-PIIX4: not 100% native mode: will probe irqs later\r
- ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
- ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
-hda: M5 IDE Disk, ATA DISK drive\r
-hdb: M5 IDE Disk, ATA DISK drive\r
-ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
-hda: max request size: 128KiB\r
-hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
- hda: hda1\r
-hdb: max request size: 128KiB\r
-hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
- hdb: unknown partition table\r
-megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
-megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
-megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
-Fusion MPT base driver 3.04.04\r
-Copyright (c) 1999-2007 LSI Logic Corporation\r
-Fusion MPT SPI Host driver 3.04.04\r
-Fusion MPT SAS Host driver 3.04.04\r
-ieee1394: raw1394: /dev/raw1394 device initialized\r
-USB Universal Host Controller Interface driver v3.0\r
-usbcore: registered new interface driver usblp\r
-drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
-Initializing USB Mass Storage driver...\r
-usbcore: registered new interface driver usb-storage\r
-USB Mass Storage support registered.\r
-serio: i8042 KBD port at 0x60,0x64 irq 1\r
-serio: i8042 AUX port at 0x60,0x64 irq 12\r
-mice: PS/2 mouse device common for all mice\r
-input: AT Translated Set 2 keyboard as /class/input/input0\r
-device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
-usbcore: registered new interface driver usbhid\r
-drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
-oprofile: using timer interrupt.\r
-TCP cubic registered\r
-NET: Registered protocol family 1\r
-NET: Registered protocol family 10\r
-IPv6 over IPv4 tunneling driver\r
-input: PS/2 Generic Mouse as /class/input/input1\r
-NET: Registered protocol family 17\r
-EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
-VFS: Mounted root (ext2 filesystem).\r
-Freeing unused kernel memory: 248k freed\r
-\rINIT: version 2.86 booting\r\r
-mounting filesystems...\r
-loading script...\r
--- /dev/null
+[root]
+type=Root
+children=system
+full_system=true
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=LinuxX86System
+children=acpi_description_table_pointer clk_domain cpu0 cpu1 cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl pc physmem piobus ruby smbios_table sys_port_proxy voltage_domain
+acpi_description_table_pointer=system.acpi_description_table_pointer
+boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
+cache_line_size=64
+clk_domain=system.clk_domain
+e820_table=system.e820_table
+init_param=0
+intel_mp_pointer=system.intel_mp_pointer
+intel_mp_table=system.intel_mp_table
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+load_addr_mask=18446744073709551615
+mem_mode=timing
+mem_ranges=0:134217727
+memories=system.physmem
+num_work_ids=16
+readfile=tests/halt.sh
+smbios_table=system.smbios_table
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.slave[0]
+
+[system.acpi_description_table_pointer]
+type=X86ACPIRSDP
+children=xsdt
+oem_id=
+revision=2
+rsdt=Null
+xsdt=system.acpi_description_table_pointer.xsdt
+
+[system.acpi_description_table_pointer.xsdt]
+type=X86ACPIXSDT
+creator_id=
+creator_revision=0
+entries=
+oem_id=
+oem_revision=0
+oem_table_id=
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=TimingSimpleCPU
+children=apic_clk_domain dtb interrupts isa itb tracer
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu0.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
+itb=system.cpu0.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu0.tracer
+workload=
+dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
+icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
+
+[system.cpu0.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
+[system.cpu0.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu0.dtb.walker
+
+[system.cpu0.dtb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[3]
+
+[system.cpu0.interrupts]
+type=X86LocalApic
+clk_domain=system.cpu0.apic_clk_domain
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=100000
+system=system
+int_master=system.piobus.slave[4]
+int_slave=system.piobus.master[18]
+pio=system.piobus.master[17]
+
+[system.cpu0.isa]
+type=X86ISA
+
+[system.cpu0.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu0.itb.walker
+
+[system.cpu0.itb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[2]
+
+[system.cpu0.tracer]
+type=ExeTracer
+
+[system.cpu1]
+type=TimingSimpleCPU
+children=apic_clk_domain dtb interrupts isa itb tracer
+checker=Null
+clk_domain=system.cpu_clk_domain
+cpu_id=1
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu1.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
+itb=system.cpu1.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu1.tracer
+workload=
+dcache_port=system.ruby.l1_cntrl1.sequencer.slave[1]
+icache_port=system.ruby.l1_cntrl1.sequencer.slave[0]
+
+[system.cpu1.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
+[system.cpu1.dtb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu1.dtb.walker
+
+[system.cpu1.dtb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[3]
+
+[system.cpu1.interrupts]
+type=X86LocalApic
+clk_domain=system.cpu1.apic_clk_domain
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=100000
+system=system
+int_master=system.piobus.slave[5]
+int_slave=system.piobus.master[20]
+pio=system.piobus.master[19]
+
+[system.cpu1.isa]
+type=X86ISA
+
+[system.cpu1.itb]
+type=X86TLB
+children=walker
+size=64
+walker=system.cpu1.itb.walker
+
+[system.cpu1.itb.walker]
+type=X86PagetableWalker
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[2]
+
+[system.cpu1.tracer]
+type=ExeTracer
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
+[system.e820_table]
+type=X86E820Table
+children=entries0 entries1 entries2 entries3
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2 system.e820_table.entries3
+
+[system.e820_table.entries0]
+type=X86E820Entry
+addr=0
+range_type=1
+size=654336
+
+[system.e820_table.entries1]
+type=X86E820Entry
+addr=654336
+range_type=2
+size=394240
+
+[system.e820_table.entries2]
+type=X86E820Entry
+addr=1048576
+range_type=1
+size=133169152
+
+[system.e820_table.entries3]
+type=X86E820Entry
+addr=4294901760
+range_type=2
+size=65536
+
+[system.intel_mp_pointer]
+type=X86IntelMPFloatingPointer
+default_config=0
+imcr_present=true
+spec_rev=4
+
+[system.intel_mp_table]
+type=X86IntelMPConfigTable
+children=base_entries00 base_entries01 base_entries02 base_entries03 base_entries04 base_entries05 base_entries06 base_entries07 base_entries08 base_entries09 base_entries10 base_entries11 base_entries12 base_entries13 base_entries14 base_entries15 base_entries16 base_entries17 base_entries18 base_entries19 base_entries20 base_entries21 base_entries22 base_entries23 base_entries24 base_entries25 base_entries26 base_entries27 base_entries28 base_entries29 base_entries30 base_entries31 base_entries32 base_entries33 ext_entries
+base_entries=system.intel_mp_table.base_entries00 system.intel_mp_table.base_entries01 system.intel_mp_table.base_entries02 system.intel_mp_table.base_entries03 system.intel_mp_table.base_entries04 system.intel_mp_table.base_entries05 system.intel_mp_table.base_entries06 system.intel_mp_table.base_entries07 system.intel_mp_table.base_entries08 system.intel_mp_table.base_entries09 system.intel_mp_table.base_entries10 system.intel_mp_table.base_entries11 system.intel_mp_table.base_entries12 system.intel_mp_table.base_entries13 system.intel_mp_table.base_entries14 system.intel_mp_table.base_entries15 system.intel_mp_table.base_entries16 system.intel_mp_table.base_entries17 system.intel_mp_table.base_entries18 system.intel_mp_table.base_entries19 system.intel_mp_table.base_entries20 system.intel_mp_table.base_entries21 system.intel_mp_table.base_entries22 system.intel_mp_table.base_entries23 system.intel_mp_table.base_entries24 system.intel_mp_table.base_entries25 system.intel_mp_table.base_entries26 system.intel_mp_table.base_entries27 system.intel_mp_table.base_entries28 system.intel_mp_table.base_entries29 system.intel_mp_table.base_entries30 system.intel_mp_table.base_entries31 system.intel_mp_table.base_entries32 system.intel_mp_table.base_entries33
+ext_entries=system.intel_mp_table.ext_entries
+local_apic=4276092928
+oem_id=
+oem_table_addr=0
+oem_table_size=0
+product_id=
+spec_rev=4
+
+[system.intel_mp_table.base_entries00]
+type=X86IntelMPProcessor
+bootstrap=true
+enable=true
+family=0
+feature_flags=0
+local_apic_id=0
+local_apic_version=20
+model=0
+stepping=0
+
+[system.intel_mp_table.base_entries01]
+type=X86IntelMPProcessor
+bootstrap=false
+enable=true
+family=0
+feature_flags=0
+local_apic_id=1
+local_apic_version=20
+model=0
+stepping=0
+
+[system.intel_mp_table.base_entries02]
+type=X86IntelMPIOAPIC
+address=4273995776
+enable=true
+id=2
+version=17
+
+[system.intel_mp_table.base_entries03]
+type=X86IntelMPBus
+bus_id=0
+bus_type=ISA
+
+[system.intel_mp_table.base_entries04]
+type=X86IntelMPBus
+bus_id=1
+bus_type=PCI
+
+[system.intel_mp_table.base_entries05]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=16
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=1
+source_bus_irq=16
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries06]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries07]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=2
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=0
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries08]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries09]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=1
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=1
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries10]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries11]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=3
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=3
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries12]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries13]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=4
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=4
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries14]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries15]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=5
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=5
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries16]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries17]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=6
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=6
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries18]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries19]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=7
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=7
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries20]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries21]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=8
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=8
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries22]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries23]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=9
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=9
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries24]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries25]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=10
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=10
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries26]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries27]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=11
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=11
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries28]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries29]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=12
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=12
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries30]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries31]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=13
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=13
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries32]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=0
+interrupt_type=ExtInt
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.base_entries33]
+type=X86IntelMPIOIntAssignment
+dest_io_apic_id=2
+dest_io_apic_intin=14
+interrupt_type=INT
+polarity=ConformPolarity
+source_bus_id=0
+source_bus_irq=14
+trigger=ConformTrigger
+
+[system.intel_mp_table.ext_entries]
+type=X86IntelMPBusHierarchy
+bus_id=0
+parent_bus=1
+subtractive_decode=true
+
+[system.intrctrl]
+type=IntrControl
+sys=system
+
+[system.pc]
+type=Pc
+children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist pciconfig south_bridge terminal
+intrctrl=system.intrctrl
+system=system
+
+[system.pc.behind_pci]
+type=IsaFake
+clk_domain=system.clk_domain
+fake_mem=false
+pio_addr=9223372036854779128
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.piobus.master[11]
+
+[system.pc.com_1]
+type=Uart8250
+children=terminal
+clk_domain=system.clk_domain
+pio_addr=9223372036854776824
+pio_latency=100000
+platform=system.pc
+system=system
+terminal=system.pc.com_1.terminal
+pio=system.piobus.master[12]
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.com_1.terminal]
+type=Terminal
+intr_control=system.intrctrl
+number=0
+output=true
+port=3456
+
+[system.pc.fake_com_2]
+type=IsaFake
+clk_domain=system.clk_domain
+fake_mem=false
+pio_addr=9223372036854776568
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.piobus.master[13]
+
+[system.pc.fake_com_3]
+type=IsaFake
+clk_domain=system.clk_domain
+fake_mem=false
+pio_addr=9223372036854776808
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.piobus.master[14]
+
+[system.pc.fake_com_4]
+type=IsaFake
+clk_domain=system.clk_domain
+fake_mem=false
+pio_addr=9223372036854776552
+pio_latency=100000
+pio_size=8
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.piobus.master[15]
+
+[system.pc.fake_floppy]
+type=IsaFake
+clk_domain=system.clk_domain
+fake_mem=false
+pio_addr=9223372036854776818
+pio_latency=100000
+pio_size=2
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.piobus.master[16]
+
+[system.pc.i_dont_exist]
+type=IsaFake
+clk_domain=system.clk_domain
+fake_mem=false
+pio_addr=9223372036854775936
+pio_latency=100000
+pio_size=1
+ret_bad_addr=false
+ret_data16=65535
+ret_data32=4294967295
+ret_data64=18446744073709551615
+ret_data8=255
+system=system
+update_data=false
+warn_access=
+pio=system.piobus.master[10]
+
+[system.pc.pciconfig]
+type=PciConfigAll
+bus=0
+clk_domain=system.clk_domain
+pio_addr=0
+pio_latency=30000
+platform=system.pc
+size=16777216
+system=system
+pio=system.piobus.default
+
+[system.pc.south_bridge]
+type=SouthBridge
+children=cmos dma1 ide int_lines0 int_lines1 int_lines2 int_lines3 int_lines4 int_lines5 int_lines6 io_apic keyboard pic1 pic2 pit speaker
+cmos=system.pc.south_bridge.cmos
+dma1=system.pc.south_bridge.dma1
+io_apic=system.pc.south_bridge.io_apic
+keyboard=system.pc.south_bridge.keyboard
+pic1=system.pc.south_bridge.pic1
+pic2=system.pc.south_bridge.pic2
+pit=system.pc.south_bridge.pit
+platform=system.pc
+speaker=system.pc.south_bridge.speaker
+
+[system.pc.south_bridge.cmos]
+type=Cmos
+children=int_pin
+clk_domain=system.clk_domain
+int_pin=system.pc.south_bridge.cmos.int_pin
+pio_addr=9223372036854775920
+pio_latency=100000
+system=system
+time=Sun Jan 1 00:00:00 2012
+pio=system.piobus.master[0]
+
+[system.pc.south_bridge.cmos.int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.dma1]
+type=I8237
+clk_domain=system.clk_domain
+pio_addr=9223372036854775808
+pio_latency=100000
+system=system
+pio=system.piobus.master[1]
+
+[system.pc.south_bridge.ide]
+type=IdeController
+children=disks0 disks1
+BAR0=496
+BAR0LegacyIO=true
+BAR0Size=8
+BAR1=1012
+BAR1LegacyIO=true
+BAR1Size=3
+BAR2=368
+BAR2LegacyIO=true
+BAR2Size=8
+BAR3=884
+BAR3LegacyIO=true
+BAR3Size=3
+BAR4=1
+BAR4LegacyIO=false
+BAR4Size=16
+BAR5=1
+BAR5LegacyIO=false
+BAR5Size=0
+BIST=0
+CacheLineSize=0
+CardbusCIS=0
+ClassCode=1
+Command=0
+DeviceID=28945
+ExpansionROM=0
+HeaderType=0
+InterruptLine=14
+InterruptPin=1
+LatencyTimer=0
+MaximumLatency=0
+MinimumGrant=0
+ProgIF=128
+Revision=0
+Status=640
+SubClassCode=1
+SubsystemID=0
+SubsystemVendorID=0
+VendorID=32902
+clk_domain=system.clk_domain
+config_latency=20000
+ctrl_offset=0
+disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
+io_shift=0
+pci_bus=0
+pci_dev=4
+pci_func=0
+pio_latency=30000
+platform=system.pc
+system=system
+config=system.piobus.master[3]
+dma=system.piobus.slave[0]
+pio=system.piobus.master[2]
+
+[system.pc.south_bridge.ide.disks0]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks0.image
+
+[system.pc.south_bridge.ide.disks0.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks0.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks0.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-x86.img
+read_only=true
+
+[system.pc.south_bridge.ide.disks1]
+type=IdeDisk
+children=image
+delay=1000000
+driveID=master
+image=system.pc.south_bridge.ide.disks1.image
+
+[system.pc.south_bridge.ide.disks1.image]
+type=CowDiskImage
+children=child
+child=system.pc.south_bridge.ide.disks1.image.child
+image_file=
+read_only=false
+table_size=65536
+
+[system.pc.south_bridge.ide.disks1.image.child]
+type=RawDiskImage
+image_file=/dist/m5/system/disks/linux-bigswap2.img
+read_only=true
+
+[system.pc.south_bridge.int_lines0]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines0.sink
+source=system.pc.south_bridge.pic1.output
+
+[system.pc.south_bridge.int_lines0.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=0
+
+[system.pc.south_bridge.int_lines1]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines1.sink
+source=system.pc.south_bridge.pic2.output
+
+[system.pc.south_bridge.int_lines1.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=2
+
+[system.pc.south_bridge.int_lines2]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines2.sink
+source=system.pc.south_bridge.cmos.int_pin
+
+[system.pc.south_bridge.int_lines2.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic2
+number=0
+
+[system.pc.south_bridge.int_lines3]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines3.sink
+source=system.pc.south_bridge.pit.int_pin
+
+[system.pc.south_bridge.int_lines3.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.pic1
+number=0
+
+[system.pc.south_bridge.int_lines4]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines4.sink
+source=system.pc.south_bridge.pit.int_pin
+
+[system.pc.south_bridge.int_lines4.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=2
+
+[system.pc.south_bridge.int_lines5]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines5.sink
+source=system.pc.south_bridge.keyboard.keyboard_int_pin
+
+[system.pc.south_bridge.int_lines5.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=1
+
+[system.pc.south_bridge.int_lines6]
+type=X86IntLine
+children=sink
+sink=system.pc.south_bridge.int_lines6.sink
+source=system.pc.south_bridge.keyboard.mouse_int_pin
+
+[system.pc.south_bridge.int_lines6.sink]
+type=X86IntSinkPin
+device=system.pc.south_bridge.io_apic
+number=12
+
+[system.pc.south_bridge.io_apic]
+type=I82094AA
+apic_id=2
+clk_domain=system.clk_domain
+external_int_pic=system.pc.south_bridge.pic1
+int_latency=1000
+pio_addr=4273995776
+pio_latency=100000
+system=system
+int_master=system.piobus.slave[1]
+pio=system.piobus.master[9]
+
+[system.pc.south_bridge.keyboard]
+type=I8042
+children=keyboard_int_pin mouse_int_pin
+clk_domain=system.clk_domain
+command_port=9223372036854775908
+data_port=9223372036854775904
+keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
+mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
+pio_addr=0
+pio_latency=100000
+system=system
+pio=system.piobus.master[4]
+
+[system.pc.south_bridge.keyboard.keyboard_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.keyboard.mouse_int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.pic1]
+type=I8259
+children=output
+clk_domain=system.clk_domain
+mode=I8259Master
+output=system.pc.south_bridge.pic1.output
+pio_addr=9223372036854775840
+pio_latency=100000
+slave=system.pc.south_bridge.pic2
+system=system
+pio=system.piobus.master[5]
+
+[system.pc.south_bridge.pic1.output]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.pic2]
+type=I8259
+children=output
+clk_domain=system.clk_domain
+mode=I8259Slave
+output=system.pc.south_bridge.pic2.output
+pio_addr=9223372036854775968
+pio_latency=100000
+slave=Null
+system=system
+pio=system.piobus.master[6]
+
+[system.pc.south_bridge.pic2.output]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.pit]
+type=I8254
+children=int_pin
+clk_domain=system.clk_domain
+int_pin=system.pc.south_bridge.pit.int_pin
+pio_addr=9223372036854775872
+pio_latency=100000
+system=system
+pio=system.piobus.master[7]
+
+[system.pc.south_bridge.pit.int_pin]
+type=X86IntSourcePin
+
+[system.pc.south_bridge.speaker]
+type=PcSpeaker
+clk_domain=system.clk_domain
+i8254=system.pc.south_bridge.pit
+pio_addr=9223372036854775905
+pio_latency=100000
+system=system
+pio=system.piobus.master[8]
+
+[system.physmem]
+type=SimpleDRAM
+activation_limit=4
+addr_mapping=RaBaChCo
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
+in_addr_map=true
+mem_sched_policy=frfcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tWTR=7500
+tXAW=40000
+write_buffer_size=32
+write_thresh_perc=70
+port=system.piobus.master[21]
+
+[system.piobus]
+type=NoncoherentBus
+clk_domain=system.clk_domain
+header_cycles=1
+use_default_range=true
+width=8
+default=system.pc.pciconfig.pio
+master=system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.physmem.port
+slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.ruby.l1_cntrl0.sequencer.pio_port system.ruby.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master
+
+[system.ruby]
+type=RubySystem
+children=clk_domain dir_cntrl0 dma_cntrl0 l1_cntrl0 l1_cntrl1 l2_cntrl0 memctrl_clk_domain network profiler
+block_size_bytes=64
+clk_domain=system.ruby.clk_domain
+mem_size=134217728
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
+[system.ruby.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=3
+directory=system.ruby.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.ruby.dir_cntrl0.memBuffer
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_mem_ctrl_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=5
+size=134217728
+use_map=false
+version=0
+
+[system.ruby.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+clk_domain=system.ruby.memctrl_clk_domain
+dimm_bit_0=12
+dimms_per_channel=2
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+ruby_system=system.ruby
+tFaw=0
+version=0
+
+[system.ruby.dma_cntrl0]
+type=DMA_Controller
+children=dma_sequencer
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=4
+dma_sequencer=system.ruby.dma_cntrl0.dma_sequencer
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+request_latency=6
+ruby_system=system.ruby
+transitions_per_cycle=4
+version=0
+
+[system.ruby.dma_cntrl0.dma_sequencer]
+type=DMASequencer
+access_phys_mem=true
+clk_domain=system.ruby.clk_domain
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.pc.south_bridge.ide.dma
+
+[system.ruby.l1_cntrl0]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl0.L1Dcache
+L1Icache=system.ruby.l1_cntrl0.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=0
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl0.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl0.sequencer
+to_l2_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.l1_cntrl0.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=32768
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=32768
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=true
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl0.L1Dcache
+deadlock_threshold=500000
+icache=system.ruby.l1_cntrl0.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+pio_port=system.piobus.slave[2]
+slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+
+[system.ruby.l1_cntrl1]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl1.L1Dcache
+L1Icache=system.ruby.l1_cntrl1.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=1
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl1.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl1.sequencer
+to_l2_latency=1
+transitions_per_cycle=4
+version=1
+
+[system.ruby.l1_cntrl1.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=32768
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl1.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=32768
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl1.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl1.sequencer]
+type=RubySequencer
+access_phys_mem=true
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl1.L1Dcache
+deadlock_threshold=500000
+icache=system.ruby.l1_cntrl1.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=1
+pio_port=system.piobus.slave[3]
+slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+
+[system.ruby.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cache
+L2cache=system.ruby.l2_cntrl0.L2cache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=2
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_l1_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.l2_cntrl0.L2cache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=15
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=4194304
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
+[system.ruby.network]
+type=SimpleNetwork
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5
+adaptive_routing=false
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+control_msg_size=8
+endpoint_bandwidth=1000
+ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4
+number_of_virtual_networks=10
+routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3 system.ruby.network.routers4 system.ruby.network.routers5
+ruby_system=system.ruby
+topology=Crossbar
+
+[system.ruby.network.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl0
+int_node=system.ruby.network.routers0
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl1
+int_node=system.ruby.network.routers1
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l2_cntrl0
+int_node=system.ruby.network.routers2
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.ext_links3]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.dir_cntrl0
+int_node=system.ruby.network.routers3
+latency=1
+link_id=3
+weight=1
+
+[system.ruby.network.ext_links4]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.dma_cntrl0
+int_node=system.ruby.network.routers4
+latency=1
+link_id=4
+weight=1
+
+[system.ruby.network.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=5
+node_a=system.ruby.network.routers0
+node_b=system.ruby.network.routers5
+weight=1
+
+[system.ruby.network.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=6
+node_a=system.ruby.network.routers1
+node_b=system.ruby.network.routers5
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=7
+node_a=system.ruby.network.routers2
+node_b=system.ruby.network.routers5
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=8
+node_a=system.ruby.network.routers3
+node_b=system.ruby.network.routers5
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=9
+node_a=system.ruby.network.routers4
+node_b=system.ruby.network.routers5
+weight=1
+
+[system.ruby.network.routers0]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=0
+virt_nets=10
+
+[system.ruby.network.routers1]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=1
+virt_nets=10
+
+[system.ruby.network.routers2]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=2
+virt_nets=10
+
+[system.ruby.network.routers3]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=3
+virt_nets=10
+
+[system.ruby.network.routers4]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=4
+virt_nets=10
+
+[system.ruby.network.routers5]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=5
+virt_nets=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=2
+ruby_system=system.ruby
+
+[system.smbios_table]
+type=X86SMBiosSMBiosTable
+children=structures
+major_version=2
+minor_version=5
+structures=system.smbios_table.structures
+
+[system.smbios_table.structures]
+type=X86SMBiosBiosInformation
+characteristic_ext_bytes=
+characteristics=
+emb_cont_firmware_major=0
+emb_cont_firmware_minor=0
+major=0
+minor=0
+release_date=06/08/2008
+rom_size=0
+starting_addr_segment=0
+vendor=
+version=
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+clk_domain=system.clk_domain
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.system_port
+
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
--- /dev/null
+
+Profiler Stats
+--------------
+Ruby_current_time: 10600871471
+Ruby_start_time: 0
+Ruby_cycles: 10600871471
+
+Busy Controller Counts:
+L1Cache-0:12 L1Cache-1:13
+L2Cache-0:2
+Directory-0:0
+DMA-0:0
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 152187620 average: 1.00011 | standard deviation: 0.0105957 | 0 152170533 17087 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+latency: [binsize: 16 max: 175 count: 152187619 average: 3.38032 | standard deviation: 3.78105 | 149532617 2479919 181 0 78486 1293 90363 3753 944 61 2 ]
+latency: LD: [binsize: 8 max: 144 count: 14921275 average: 4.75297 | standard deviation: 6.60507 | 13535742 0 1328034 25221 131 0 0 0 0 9977 145 16 20 20925 775 45 44 172 28 ]
+latency: ST: [binsize: 16 max: 175 count: 9491432 average: 4.60863 | standard deviation: 10.6418 | 9141416 224288 30 0 63466 1078 57802 2705 612 33 2 ]
+latency: IFETCH: [binsize: 8 max: 143 count: 126601627 average: 3.11268 | standard deviation: 1.65139 | 125785924 0 800296 97 4 0 0 0 0 3861 27 4 5 11094 188 17 12 98 ]
+latency: RMW_Read: [binsize: 8 max: 143 count: 494285 average: 5.89281 | standard deviation: 8.20937 | 428799 0 43439 20640 6 0 0 0 0 992 21 1 2 363 16 1 1 4 ]
+latency: Locked_RMW_Read: [binsize: 8 max: 140 count: 339500 average: 5.2378 | standard deviation: 6.75071 | 301236 0 27794 10110 10 0 0 0 0 190 1 0 0 152 6 0 0 1 ]
+latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 339500 average: 3 | standard deviation: 0 | 0 0 0 339500 ]
+hit latency: [binsize: 1 max: 3 count: 149532617 average: 3 | standard deviation: 0 | 0 0 0 149532617 ]
+hit latency: LD: [binsize: 1 max: 3 count: 13535742 average: 3 | standard deviation: 0 | 0 0 0 13535742 ]
+hit latency: ST: [binsize: 1 max: 3 count: 9141416 average: 3 | standard deviation: 0 | 0 0 0 9141416 ]
+hit latency: IFETCH: [binsize: 1 max: 3 count: 125785924 average: 3 | standard deviation: 0 | 0 0 0 125785924 ]
+hit latency: RMW_Read: [binsize: 1 max: 3 count: 428799 average: 3 | standard deviation: 0 | 0 0 0 428799 ]
+hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 301236 average: 3 | standard deviation: 0 | 0 0 0 301236 ]
+hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 339500 average: 3 | standard deviation: 0 | 0 0 0 339500 ]
+miss latency: [binsize: 16 max: 175 count: 2655002 average: 24.8002 | standard deviation: 18.7757 | 0 2479919 181 0 78486 1293 90363 3753 944 61 2 ]
+miss latency: LD: [binsize: 8 max: 144 count: 1385533 average: 21.8783 | standard deviation: 12.1052 | 0 0 1328034 25221 131 0 0 0 0 9977 145 16 20 20925 775 45 44 172 28 ]
+miss latency: ST: [binsize: 16 max: 175 count: 350016 average: 46.6216 | standard deviation: 35.1891 | 0 224288 30 0 63466 1078 57802 2705 612 33 2 ]
+miss latency: IFETCH: [binsize: 8 max: 143 count: 815703 average: 20.4881 | standard deviation: 10.9268 | 0 0 800296 97 4 0 0 0 0 3861 27 4 5 11094 188 17 12 98 ]
+miss latency: RMW_Read: [binsize: 8 max: 143 count: 65486 average: 24.8348 | standard deviation: 9.75142 | 0 0 43439 20640 6 0 0 0 0 992 21 1 2 363 16 1 1 4 ]
+miss latency: Locked_RMW_Read: [binsize: 8 max: 140 count: 38264 average: 22.855 | standard deviation: 7.38587 | 0 0 27794 10110 10 0 0 0 0 190 1 0 0 152 6 0 0 1 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 13 count: 10855755 average: 0.221686 | standard deviation: 0.915908 | 10253393 1133 685 941 598385 739 87 93 74 159 8 10 6 42 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6093680 average: 0.377613 | standard deviation: 1.1709 | 5518533 548 185 218 573099 623 85 91 73 159 8 10 6 42 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 8 count: 4681410 average: 0.022308 | standard deviation: 0.296312 | 4654609 478 413 621 25188 96 2 2 1 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 5 count: 80665 average: 0.0133763 | standard deviation: 0.206119 | 80251 107 87 102 98 20 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- /dev/null
+warn: add_child('terminal'): child 'terminal' already has parent
+warn: Sockets disabled, not accepting terminal connections
+warn: Reading current count from inactive timer.
+warn: Sockets disabled, not accepting gdb connections
+warn: Don't know what interrupt to clear for console.
+warn: x86 cpuid: unknown family 0x8086
+warn: instruction 'wbinvd' unimplemented
+warn: instruction 'wbinvd' unimplemented
+warn: x86 cpuid: unknown family 0x8086
+hack: Assuming logical destinations are 1 << id.
+warn: Tried to clear PCI interrupt 14
+warn: Unknown mouse command 0xe1.
+hack: be nice to actually delete the event here
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Oct 16 2013 01:55:52
+gem5 started Oct 16 2013 01:57:05
+gem5 executing on zizzer
+command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
+Global frequency set at 1000000000000 ticks per second
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+ 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 5304492233500 because m5_exit instruction encountered
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 5.300436 # Number of seconds simulated
+sim_ticks 5300435735500 # Number of ticks simulated
+final_tick 5300435735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 137756 # Simulator instruction rate (inst/s)
+host_op_rate 264143 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6834713129 # Simulator tick rate (ticks/s)
+host_mem_usage 828636 # Number of bytes of host memory used
+host_seconds 775.52 # Real time elapsed on the host
+sim_insts 106831806 # Number of instructions simulated
+sim_ops 204847037 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 542427168 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 38705697 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 101016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 45856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 470385848 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 54943175 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1106827384 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 542427168 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 470385848 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1012813016 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 31534134 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 36447890 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70973144 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 814 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 15245 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 7685 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 67803396 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 6494255 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 12627 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 5732 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 58798231 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9219516 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 142357501 # Number of read requests responded to by this memory
+system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4739560 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 5091370 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 9877668 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 6638 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 23009 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 11599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 102336335 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 7302361 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 19058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 8651 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 88744751 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 10365785 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 208818188 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 102336335 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 88744751 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 191081086 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 564313 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 5949347 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 6876395 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 13390058 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 570951 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 23009 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 11602 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 102336335 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13251709 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 19058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 8651 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 88744751 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 17242180 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 222208246 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 0 # Number of read requests accepted
+system.physmem.writeReqs 0 # Number of write requests accepted
+system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 0 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
+system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 0 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 0 # Per bank write bursts
+system.physmem.perBankRdBursts::1 0 # Per bank write bursts
+system.physmem.perBankRdBursts::2 0 # Per bank write bursts
+system.physmem.perBankRdBursts::3 0 # Per bank write bursts
+system.physmem.perBankRdBursts::4 0 # Per bank write bursts
+system.physmem.perBankRdBursts::5 0 # Per bank write bursts
+system.physmem.perBankRdBursts::6 0 # Per bank write bursts
+system.physmem.perBankRdBursts::7 0 # Per bank write bursts
+system.physmem.perBankRdBursts::8 0 # Per bank write bursts
+system.physmem.perBankRdBursts::9 0 # Per bank write bursts
+system.physmem.perBankRdBursts::10 0 # Per bank write bursts
+system.physmem.perBankRdBursts::11 0 # Per bank write bursts
+system.physmem.perBankRdBursts::12 0 # Per bank write bursts
+system.physmem.perBankRdBursts::13 0 # Per bank write bursts
+system.physmem.perBankRdBursts::14 0 # Per bank write bursts
+system.physmem.perBankRdBursts::15 0 # Per bank write bursts
+system.physmem.perBankWrBursts::0 0 # Per bank write bursts
+system.physmem.perBankWrBursts::1 0 # Per bank write bursts
+system.physmem.perBankWrBursts::2 0 # Per bank write bursts
+system.physmem.perBankWrBursts::3 0 # Per bank write bursts
+system.physmem.perBankWrBursts::4 0 # Per bank write bursts
+system.physmem.perBankWrBursts::5 0 # Per bank write bursts
+system.physmem.perBankWrBursts::6 0 # Per bank write bursts
+system.physmem.perBankWrBursts::7 0 # Per bank write bursts
+system.physmem.perBankWrBursts::8 0 # Per bank write bursts
+system.physmem.perBankWrBursts::9 0 # Per bank write bursts
+system.physmem.perBankWrBursts::10 0 # Per bank write bursts
+system.physmem.perBankWrBursts::11 0 # Per bank write bursts
+system.physmem.perBankWrBursts::12 0 # Per bank write bursts
+system.physmem.perBankWrBursts::13 0 # Per bank write bursts
+system.physmem.perBankWrBursts::14 0 # Per bank write bursts
+system.physmem.perBankWrBursts::15 0 # Per bank write bursts
+system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
+system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
+system.physmem.totGap 0 # Total gap between requests
+system.physmem.readPktSize::0 0 # Read request sizes (log2)
+system.physmem.readPktSize::1 0 # Read request sizes (log2)
+system.physmem.readPktSize::2 0 # Read request sizes (log2)
+system.physmem.readPktSize::3 0 # Read request sizes (log2)
+system.physmem.readPktSize::4 0 # Read request sizes (log2)
+system.physmem.readPktSize::5 0 # Read request sizes (log2)
+system.physmem.readPktSize::6 0 # Read request sizes (log2)
+system.physmem.writePktSize::0 0 # Write request sizes (log2)
+system.physmem.writePktSize::1 0 # Write request sizes (log2)
+system.physmem.writePktSize::2 0 # Write request sizes (log2)
+system.physmem.writePktSize::3 0 # Write request sizes (log2)
+system.physmem.writePktSize::4 0 # Write request sizes (log2)
+system.physmem.writePktSize::5 0 # Write request sizes (log2)
+system.physmem.writePktSize::6 0 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
+system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation
+system.physmem.totQLat 0 # Total ticks spent queuing
+system.physmem.totMemAccLat 0 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 0 # Total ticks spent in databus transfers
+system.physmem.totBankLat 0 # Total ticks spent accessing banks
+system.physmem.avgQLat nan # Average queueing delay per DRAM burst
+system.physmem.avgBankLat nan # Average bank access latency per DRAM burst
+system.physmem.avgBusLat nan # Average bus latency per DRAM burst
+system.physmem.avgMemAccLat nan # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 0.00 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 0.00 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
+system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
+system.physmem.busUtil 0.00 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
+system.physmem.readRowHits 0 # Number of row buffer hits during reads
+system.physmem.writeRowHits 0 # Number of row buffer hits during writes
+system.physmem.readRowHitRate nan # Row buffer hit rate for reads
+system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
+system.physmem.avgGap nan # Average gap between requests
+system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined
+system.physmem.prechargeAllPercent 0.00 # Percentage of time for which DRAM has all the banks in precharge state
+system.piobus.throughput 386047 # Throughput (bytes/s)
+system.piobus.trans_dist::ReadReq 863424 # Transaction distribution
+system.piobus.trans_dist::ReadResp 863424 # Transaction distribution
+system.piobus.trans_dist::WriteReq 37806 # Transaction distribution
+system.piobus.trans_dist::WriteResp 37806 # Transaction distribution
+system.piobus.trans_dist::MessageReq 1919 # Transaction distribution
+system.piobus.trans_dist::MessageResp 1919 # Transaction distribution
+system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 1700 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 1644 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 5246 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 938970 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 984 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 14276 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 748688 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl0.sequencer-pio-port::total 1711608 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 5796 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 33204 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 350 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 33292 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 12392 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 5218 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.ruby.l1_cntrl1.sequencer-pio-port::total 90852 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 244 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu0.interrupts.int_master::total 244 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 250 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count_system.cpu1.interrupts.int_master::total 250 # Packet count per connected master and slave (bytes)
+system.piobus.pkt_count::total 1806298 # Packet count per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu0.interrupts.int_slave 3400 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.cpu1.interrupts.int_slave 3288 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide.pio 2968 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.speaker.pio 469485 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 1968 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.com_1.pio 7138 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.cpu0.interrupts.pio 1497370 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer-pio-port::total 1983945 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide.pio 3692 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.pit.pio 16602 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.south_bridge.io_apic.pio 700 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.i_dont_exist.pio 16646 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.com_1.pio 6196 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::system.cpu1.interrupts.pio 10433 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer-pio-port::total 54595 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::system.cpu1.interrupts.int_slave 488 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu0.interrupts.int_master::total 488 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::system.cpu0.interrupts.int_slave 500 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size_system.cpu1.interrupts.int_master::total 500 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.tot_pkt_size::total 2046216 # Cumulative packet size per connected master and slave (bytes)
+system.piobus.data_through_bus 2046216 # Total data (bytes)
+system.piobus.reqLayer0.occupancy 48000 # Layer occupancy (ticks)
+system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks)
+system.piobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer2.occupancy 10168500 # Layer occupancy (ticks)
+system.piobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer3.occupancy 154000 # Layer occupancy (ticks)
+system.piobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer4.occupancy 1061500 # Layer occupancy (ticks)
+system.piobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks)
+system.piobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer6.occupancy 56000 # Layer occupancy (ticks)
+system.piobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer7.occupancy 22164500 # Layer occupancy (ticks)
+system.piobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer8.occupancy 586857000 # Layer occupancy (ticks)
+system.piobus.reqLayer8.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer9.occupancy 1295000 # Layer occupancy (ticks)
+system.piobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer10.occupancy 41706500 # Layer occupancy (ticks)
+system.piobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer11.occupancy 2500 # Layer occupancy (ticks)
+system.piobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer12.occupancy 23281500 # Layer occupancy (ticks)
+system.piobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
+system.piobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
+system.piobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
+system.piobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer16.occupancy 11000 # Layer occupancy (ticks)
+system.piobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer17.occupancy 470677500 # Layer occupancy (ticks)
+system.piobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer18.occupancy 2359248 # Layer occupancy (ticks)
+system.piobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer19.occupancy 5486500 # Layer occupancy (ticks)
+system.piobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer20.occupancy 2285216 # Layer occupancy (ticks)
+system.piobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.piobus.reqLayer22.occupancy 1083000 # Layer occupancy (ticks)
+system.piobus.reqLayer22.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer0.occupancy 2422464 # Layer occupancy (ticks)
+system.piobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer1.occupancy 1917192500 # Layer occupancy (ticks)
+system.piobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer2.occupancy 72612500 # Layer occupancy (ticks)
+system.piobus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer3.occupancy 151500 # Layer occupancy (ticks)
+system.piobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.piobus.respLayer4.occupancy 151500 # Layer occupancy (ticks)
+system.piobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 10730814 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 525933 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11256747 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 67479144 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 324252 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 67803396 # Number of cache demand accesses
+system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 13015879 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313366 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14329245 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits 58306780 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses 491451 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses 58798231 # Number of cache demand accesses
+system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l2_cntrl0.L2cache.demand_hits 2431660 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 223342 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 2655002 # Number of cache demand accesses
+system.ruby.network.routers0.percent_links_utilized 0.029766
+system.ruby.network.routers0.msg_count.Control::0 850185
+system.ruby.network.routers0.msg_count.Request_Control::0 42201
+system.ruby.network.routers0.msg_count.Response_Data::1 878303
+system.ruby.network.routers0.msg_count.Response_Control::1 503569
+system.ruby.network.routers0.msg_count.Response_Control::2 500391
+system.ruby.network.routers0.msg_count.Writeback_Data::0 294658
+system.ruby.network.routers0.msg_count.Writeback_Data::1 77
+system.ruby.network.routers0.msg_count.Writeback_Control::0 168208
+system.ruby.network.routers0.msg_bytes.Control::0 6801480
+system.ruby.network.routers0.msg_bytes.Request_Control::0 337608
+system.ruby.network.routers0.msg_bytes.Response_Data::1 63237816
+system.ruby.network.routers0.msg_bytes.Response_Control::1 4028552
+system.ruby.network.routers0.msg_bytes.Response_Control::2 4003128
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21215376
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5544
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1345664
+system.ruby.network.routers1.percent_links_utilized 0.057219
+system.ruby.network.routers1.msg_count.Control::0 1804817
+system.ruby.network.routers1.msg_count.Request_Control::0 38464
+system.ruby.network.routers1.msg_count.Response_Data::1 1828188
+system.ruby.network.routers1.msg_count.Response_Control::1 1255906
+system.ruby.network.routers1.msg_count.Response_Control::2 1256121
+system.ruby.network.routers1.msg_count.Writeback_Data::0 279078
+system.ruby.network.routers1.msg_count.Writeback_Data::1 227
+system.ruby.network.routers1.msg_count.Writeback_Control::0 940222
+system.ruby.network.routers1.msg_bytes.Control::0 14438536
+system.ruby.network.routers1.msg_bytes.Request_Control::0 307712
+system.ruby.network.routers1.msg_bytes.Response_Data::1 131629536
+system.ruby.network.routers1.msg_bytes.Response_Control::1 10047248
+system.ruby.network.routers1.msg_bytes.Response_Control::2 10048968
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20093616
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1 16344
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7521776
+system.ruby.network.routers2.percent_links_utilized 0.091302
+system.ruby.network.routers2.msg_count.Control::0 2829904
+system.ruby.network.routers2.msg_count.Request_Control::0 78999
+system.ruby.network.routers2.msg_count.Response_Data::1 2881954
+system.ruby.network.routers2.msg_count.Response_Control::1 1837374
+system.ruby.network.routers2.msg_count.Response_Control::2 1756512
+system.ruby.network.routers2.msg_count.Writeback_Data::0 573736
+system.ruby.network.routers2.msg_count.Writeback_Data::1 304
+system.ruby.network.routers2.msg_count.Writeback_Control::0 1108430
+system.ruby.network.routers2.msg_bytes.Control::0 22639232
+system.ruby.network.routers2.msg_bytes.Request_Control::0 631992
+system.ruby.network.routers2.msg_bytes.Response_Data::1 207500688
+system.ruby.network.routers2.msg_bytes.Response_Control::1 14698992
+system.ruby.network.routers2.msg_bytes.Response_Control::2 14052096
+system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41308992
+system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888
+system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867440
+system.ruby.dir_cntrl0.memBuffer.memReq 317877 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 175365 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 142512 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 714764 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 943121 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ 39 # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ 6636 # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 949796 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.987936 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 931605 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 8278 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 95 # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait 3135 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.23% 3.23% | 9701 3.05% 6.29% | 9679 3.04% 9.33% | 9712 3.06% 12.39% | 10010 3.15% 15.54% | 9927 3.12% 18.66% | 9854 3.10% 21.76% | 9702 3.05% 24.81% | 9904 3.12% 27.93% | 9752 3.07% 30.99% | 9805 3.08% 34.08% | 9914 3.12% 37.20% | 9948 3.13% 40.33% | 9724 3.06% 43.39% | 9647 3.03% 46.42% | 8750 2.75% 49.17% | 10266 3.23% 52.40% | 9887 3.11% 55.51% | 9844 3.10% 58.61% | 9758 3.07% 61.68% | 10022 3.15% 64.83% | 9879 3.11% 67.94% | 9766 3.07% 71.01% | 9852 3.10% 74.11% | 10073 3.17% 77.28% | 9931 3.12% 80.40% | 10177 3.20% 83.61% | 10769 3.39% 86.99% | 10605 3.34% 90.33% | 10522 3.31% 93.64% | 10506 3.31% 96.95% | 9709 3.05% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 317877 # Number of accesses per bank
+
+system.ruby.network.routers3.percent_links_utilized 0.006727
+system.ruby.network.routers3.msg_count.Control::0 174902
+system.ruby.network.routers3.msg_count.Response_Data::1 273157
+system.ruby.network.routers3.msg_count.Response_Control::1 125035
+system.ruby.network.routers3.msg_count.Writeback_Control::0 47550
+system.ruby.network.routers3.msg_count.Writeback_Control::1 46736
+system.ruby.network.routers3.msg_bytes.Control::0 1399216
+system.ruby.network.routers3.msg_bytes.Response_Data::1 19667304
+system.ruby.network.routers3.msg_bytes.Response_Control::1 1000280
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380400
+system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888
+system.ruby.network.routers4.percent_links_utilized 0.000240
+system.ruby.network.routers4.msg_count.Response_Data::1 814
+system.ruby.network.routers4.msg_count.Writeback_Control::0 47550
+system.ruby.network.routers4.msg_count.Writeback_Control::1 46736
+system.ruby.network.routers4.msg_bytes.Response_Data::1 58608
+system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380400
+system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888
+system.ruby.network.routers5.percent_links_utilized 0.037052
+system.ruby.network.routers5.msg_count.Control::0 2829904
+system.ruby.network.routers5.msg_count.Request_Control::0 80665
+system.ruby.network.routers5.msg_count.Response_Data::1 2931208
+system.ruby.network.routers5.msg_count.Response_Control::1 1860942
+system.ruby.network.routers5.msg_count.Response_Control::2 1756512
+system.ruby.network.routers5.msg_count.Writeback_Data::0 573736
+system.ruby.network.routers5.msg_count.Writeback_Data::1 304
+system.ruby.network.routers5.msg_count.Writeback_Control::0 1155980
+system.ruby.network.routers5.msg_count.Writeback_Control::1 46736
+system.ruby.network.routers5.msg_bytes.Control::0 22639232
+system.ruby.network.routers5.msg_bytes.Request_Control::0 645320
+system.ruby.network.routers5.msg_bytes.Response_Data::1 211046976
+system.ruby.network.routers5.msg_bytes.Response_Control::1 14887536
+system.ruby.network.routers5.msg_bytes.Response_Control::2 14052096
+system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41308992
+system.ruby.network.routers5.msg_bytes.Writeback_Data::1 21888
+system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9247840
+system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888
+system.ruby.network.msg_count.Control 8489712
+system.ruby.network.msg_count.Request_Control 240329
+system.ruby.network.msg_count.Response_Data 8793624
+system.ruby.network.msg_count.Response_Control 10852362
+system.ruby.network.msg_count.Writeback_Data 1722120
+system.ruby.network.msg_count.Writeback_Control 3608148
+system.ruby.network.msg_byte.Control 67917696
+system.ruby.network.msg_byte.Request_Control 1922632
+system.ruby.network.msg_byte.Response_Data 633140928
+system.ruby.network.msg_byte.Response_Control 86818896
+system.ruby.network.msg_byte.Writeback_Data 123992640
+system.ruby.network.msg_byte.Writeback_Control 28865184
+system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_bytes 2987008 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs 813 # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
+system.cpu0.numCycles 10600871471 # number of cpu cycles simulated
+system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.committedInsts 58268800 # Number of instructions committed
+system.cpu0.committedOps 112064452 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 105032474 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu0.num_func_calls 986042 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 9969773 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 105032474 # number of integer instructions
+system.cpu0.num_fp_insts 0 # number of float instructions
+system.cpu0.num_int_register_reads 197859045 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 89264580 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 60358670 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 43636307 # number of times the CC registers were written
+system.cpu0.num_mem_refs 12087584 # number of memory refs
+system.cpu0.num_load_insts 7337910 # Number of load instructions
+system.cpu0.num_store_insts 4749674 # Number of store instructions
+system.cpu0.num_idle_cycles 10090453891.750097 # Number of idle cycles
+system.cpu0.num_busy_cycles 510417579.249904 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.048149 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.951851 # Percentage of idle cycles
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu1.numCycles 10598039537 # number of cpu cycles simulated
+system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.committedInsts 48563006 # Number of instructions committed
+system.cpu1.committedOps 92782585 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 89102881 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
+system.cpu1.num_func_calls 1756991 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 8282210 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 89102881 # number of integer instructions
+system.cpu1.num_fp_insts 0 # number of float instructions
+system.cpu1.num_int_register_reads 172889449 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 73679026 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 51236507 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 33066238 # number of times the CC registers were written
+system.cpu1.num_mem_refs 14350514 # number of memory refs
+system.cpu1.num_load_insts 9231964 # Number of load instructions
+system.cpu1.num_store_insts 5118550 # Number of store instructions
+system.cpu1.num_idle_cycles 10261752317.862694 # Number of idle cycles
+system.cpu1.num_busy_cycles 336287219.137307 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.031731 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.968269 # Percentage of idle cycles
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.ruby.network.routers0.throttle0.link_utilization 0.038081
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 42201
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+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3899960
+system.ruby.network.routers0.throttle1.link_utilization 0.021451
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+system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40065
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 16074
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 500391
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+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 77
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+system.ruby.network.routers0.throttle1.msg_bytes.Control::0 6801480
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+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4003128
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+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 5544
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 1345664
+system.ruby.network.routers1.throttle0.link_utilization 0.082224
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+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 9920472
+system.ruby.network.routers1.throttle1.link_utilization 0.032214
+system.ruby.network.routers1.throttle1.msg_count.Control::0 1804817
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 33244
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 15847
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1256121
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+system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 227
+system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 940222
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+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 126776
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+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 16344
+system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7521776
+system.ruby.network.routers2.throttle0.link_utilization 0.059452
+system.ruby.network.routers2.throttle0.msg_count.Control::0 2655002
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+system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::1 304
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+system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::0 8867440
+system.ruby.network.routers2.throttle1.link_utilization 0.123152
+system.ruby.network.routers2.throttle1.msg_count.Control::0 174902
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+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 13734200
+system.ruby.network.routers3.throttle0.link_utilization 0.005246
+system.ruby.network.routers3.throttle0.msg_count.Control::0 174902
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 97441
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 12789
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+system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 380400
+system.ruby.network.routers3.throttle1.link_utilization 0.008209
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 175716
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 112246
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+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 897968
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888
+system.ruby.network.routers4.throttle0.link_utilization 0.000255
+system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 814
+system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736
+system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58608
+system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888
+system.ruby.network.routers4.throttle1.link_utilization 0.000224
+system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47550
+system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380400
+system.ruby.network.routers5.throttle0.link_utilization 0.038081
+system.ruby.network.routers5.throttle0.msg_count.Request_Control::0 42201
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+system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 3899960
+system.ruby.network.routers5.throttle1.link_utilization 0.082224
+system.ruby.network.routers5.throttle1.msg_count.Request_Control::0 38464
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+system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 1240059
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+system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 129235968
+system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 9920472
+system.ruby.network.routers5.throttle2.link_utilization 0.059452
+system.ruby.network.routers5.throttle2.msg_count.Control::0 2655002
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+system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 120599
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+system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 1108430
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+system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 8867440
+system.ruby.network.routers5.throttle3.link_utilization 0.005246
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+system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 97441
+system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12789
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+system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380400
+system.ruby.network.routers5.throttle4.link_utilization 0.000255
+system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 814
+system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736
+system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58608
+system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888
+system.ruby.l1_cntrl0.Load | 6084593 40.78% 40.78% | 8836682 59.22% 100.00%
+system.ruby.l1_cntrl0.Load::total 14921275
+
+system.ruby.l1_cntrl0.Ifetch | 67803399 53.56% 53.56% | 58798232 46.44% 100.00%
+system.ruby.l1_cntrl0.Ifetch::total 126601631
+
+system.ruby.l1_cntrl0.Store | 5172154 48.50% 48.50% | 5492563 51.50% 100.00%
+system.ruby.l1_cntrl0.Store::total 10664717
+
+system.ruby.l1_cntrl0.Inv | 16151 50.12% 50.12% | 16074 49.88% 100.00%
+system.ruby.l1_cntrl0.Inv::total 32225
+
+system.ruby.l1_cntrl0.L1_Replacement | 823061 31.64% 31.64% | 1778014 68.36% 100.00%
+system.ruby.l1_cntrl0.L1_Replacement::total 2601075
+
+system.ruby.l1_cntrl0.Fwd_GETX | 12035 51.06% 51.06% | 11536 48.94% 100.00%
+system.ruby.l1_cntrl0.Fwd_GETX::total 23571
+
+system.ruby.l1_cntrl0.Fwd_GETS | 14011 56.35% 56.35% | 10854 43.65% 100.00%
+system.ruby.l1_cntrl0.Fwd_GETS::total 24865
+
+system.ruby.l1_cntrl0.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 4
+
+system.ruby.l1_cntrl0.Data | 735 42.05% 42.05% | 1013 57.95% 100.00%
+system.ruby.l1_cntrl0.Data::total 1748
+
+system.ruby.l1_cntrl0.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00%
+system.ruby.l1_cntrl0.Data_Exclusive::total 1277877
+
+system.ruby.l1_cntrl0.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00%
+system.ruby.l1_cntrl0.DataS_fromL1::total 24869
+
+system.ruby.l1_cntrl0.Data_all_Acks | 576364 43.38% 43.38% | 752324 56.62% 100.00%
+system.ruby.l1_cntrl0.Data_all_Acks::total 1328688
+
+system.ruby.l1_cntrl0.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00%
+system.ruby.l1_cntrl0.Ack::total 21820
+
+system.ruby.l1_cntrl0.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00%
+system.ruby.l1_cntrl0.Ack_all::total 23568
+
+system.ruby.l1_cntrl0.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00%
+system.ruby.l1_cntrl0.WB_Ack::total 1682166
+
+system.ruby.l1_cntrl0.NP.Load | 278296 20.36% 20.36% | 1088636 79.64% 100.00%
+system.ruby.l1_cntrl0.NP.Load::total 1366932
+
+system.ruby.l1_cntrl0.NP.Ifetch | 324154 39.75% 39.75% | 491322 60.25% 100.00%
+system.ruby.l1_cntrl0.NP.Ifetch::total 815476
+
+system.ruby.l1_cntrl0.NP.Store | 221635 52.68% 52.68% | 199080 47.32% 100.00%
+system.ruby.l1_cntrl0.NP.Store::total 420715
+
+system.ruby.l1_cntrl0.NP.Inv | 5298 59.24% 59.24% | 3645 40.76% 100.00%
+system.ruby.l1_cntrl0.NP.Inv::total 8943
+
+system.ruby.l1_cntrl0.I.Load | 8385 45.08% 45.08% | 10216 54.92% 100.00%
+system.ruby.l1_cntrl0.I.Load::total 18601
+
+system.ruby.l1_cntrl0.I.Ifetch | 98 43.17% 43.17% | 129 56.83% 100.00%
+system.ruby.l1_cntrl0.I.Ifetch::total 227
+
+system.ruby.l1_cntrl0.I.Store | 5670 50.49% 50.49% | 5561 49.51% 100.00%
+system.ruby.l1_cntrl0.I.Store::total 11231
+
+system.ruby.l1_cntrl0.I.L1_Replacement | 8735 52.29% 52.29% | 7971 47.71% 100.00%
+system.ruby.l1_cntrl0.I.L1_Replacement::total 16706
+
+system.ruby.l1_cntrl0.S.Load | 550458 51.55% 51.55% | 517421 48.45% 100.00%
+system.ruby.l1_cntrl0.S.Load::total 1067879
+
+system.ruby.l1_cntrl0.S.Ifetch | 67479144 53.65% 53.65% | 58306780 46.35% 100.00%
+system.ruby.l1_cntrl0.S.Ifetch::total 125785924
+
+system.ruby.l1_cntrl0.S.Store | 11947 54.75% 54.75% | 9873 45.25% 100.00%
+system.ruby.l1_cntrl0.S.Store::total 21820
+
+system.ruby.l1_cntrl0.S.Inv | 10719 46.81% 46.81% | 12178 53.19% 100.00%
+system.ruby.l1_cntrl0.S.Inv::total 22897
+
+system.ruby.l1_cntrl0.S.L1_Replacement | 351460 38.96% 38.96% | 550743 61.04% 100.00%
+system.ruby.l1_cntrl0.S.L1_Replacement::total 902203
+
+system.ruby.l1_cntrl0.E.Load | 1120786 29.13% 29.13% | 2726694 70.87% 100.00%
+system.ruby.l1_cntrl0.E.Load::total 3847480
+
+system.ruby.l1_cntrl0.E.Store | 80619 48.39% 48.39% | 85992 51.61% 100.00%
+system.ruby.l1_cntrl0.E.Store::total 166611
+
+system.ruby.l1_cntrl0.E.Inv | 57 70.37% 70.37% | 24 29.63% 100.00%
+system.ruby.l1_cntrl0.E.Inv::total 81
+
+system.ruby.l1_cntrl0.E.L1_Replacement | 168208 15.18% 15.18% | 940222 84.82% 100.00%
+system.ruby.l1_cntrl0.E.L1_Replacement::total 1108430
+
+system.ruby.l1_cntrl0.E.Fwd_GETX | 208 58.92% 58.92% | 145 41.08% 100.00%
+system.ruby.l1_cntrl0.E.Fwd_GETX::total 353
+
+system.ruby.l1_cntrl0.E.Fwd_GETS | 1001 46.45% 46.45% | 1154 53.55% 100.00%
+system.ruby.l1_cntrl0.E.Fwd_GETS::total 2155
+
+system.ruby.l1_cntrl0.M.Load | 4126668 47.87% 47.87% | 4493715 52.13% 100.00%
+system.ruby.l1_cntrl0.M.Load::total 8620383
+
+system.ruby.l1_cntrl0.M.Store | 4852283 48.31% 48.31% | 5192057 51.69% 100.00%
+system.ruby.l1_cntrl0.M.Store::total 10044340
+
+system.ruby.l1_cntrl0.M.Inv | 77 25.33% 25.33% | 227 74.67% 100.00%
+system.ruby.l1_cntrl0.M.Inv::total 304
+
+system.ruby.l1_cntrl0.M.L1_Replacement | 294658 51.36% 51.36% | 279078 48.64% 100.00%
+system.ruby.l1_cntrl0.M.L1_Replacement::total 573736
+
+system.ruby.l1_cntrl0.M.Fwd_GETX | 11827 50.94% 50.94% | 11391 49.06% 100.00%
+system.ruby.l1_cntrl0.M.Fwd_GETX::total 23218
+
+system.ruby.l1_cntrl0.M.Fwd_GETS | 13010 57.29% 57.29% | 9700 42.71% 100.00%
+system.ruby.l1_cntrl0.M.Fwd_GETS::total 22710
+
+system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4
+
+system.ruby.l1_cntrl0.IS.Data_Exclusive | 250285 19.59% 19.59% | 1027592 80.41% 100.00%
+system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1277877
+
+system.ruby.l1_cntrl0.IS.DataS_fromL1 | 10854 43.64% 43.64% | 14015 56.36% 100.00%
+system.ruby.l1_cntrl0.IS.DataS_fromL1::total 24869
+
+system.ruby.l1_cntrl0.IS.Data_all_Acks | 349794 38.93% 38.93% | 548696 61.07% 100.00%
+system.ruby.l1_cntrl0.IS.Data_all_Acks::total 898490
+
+system.ruby.l1_cntrl0.IM.Data | 735 42.05% 42.05% | 1013 57.95% 100.00%
+system.ruby.l1_cntrl0.IM.Data::total 1748
+
+system.ruby.l1_cntrl0.IM.Data_all_Acks | 226570 52.67% 52.67% | 203628 47.33% 100.00%
+system.ruby.l1_cntrl0.IM.Data_all_Acks::total 430198
+
+system.ruby.l1_cntrl0.SM.Ack | 11947 54.75% 54.75% | 9873 45.25% 100.00%
+system.ruby.l1_cntrl0.SM.Ack::total 21820
+
+system.ruby.l1_cntrl0.SM.Ack_all | 12682 53.81% 53.81% | 10886 46.19% 100.00%
+system.ruby.l1_cntrl0.SM.Ack_all::total 23568
+
+system.ruby.l1_cntrl0.M_I.Ifetch | 3 75.00% 75.00% | 1 25.00% 100.00%
+system.ruby.l1_cntrl0.M_I.Ifetch::total 4
+
+system.ruby.l1_cntrl0.M_I.WB_Ack | 462866 27.52% 27.52% | 1219300 72.48% 100.00%
+system.ruby.l1_cntrl0.M_I.WB_Ack::total 1682166
+
+system.ruby.l2_cntrl0.L1_GET_INSTR 815703 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETS 1385690 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETX 431947 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_UPGRADE 21820 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX 1682166 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement 95350 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement_clean 12864 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Data 174902 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Ack 110230 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data 23018 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data_clean 2155 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack 1666 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack_all 6687 0.00% 0.00%
+system.ruby.l2_cntrl0.Unblock 24869 0.00% 0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock 1731643 0.00% 0.00%
+system.ruby.l2_cntrl0.MEM_Inv 4032 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GET_INSTR 15306 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS 32147 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX 127449 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GET_INSTR 800365 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GETS 82791 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GETX 1783 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_UPGRADE 21820 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement 268 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement_clean 6335 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.MEM_Inv 3 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GET_INSTR 28 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETS 1245730 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETX 279143 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement 94921 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement_clean 6421 0.00% 0.00%
+system.ruby.l2_cntrl0.M.MEM_Inv 1897 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_GETS 24865 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_GETX 23571 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_PUTX 1682166 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement 161 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement_clean 108 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.MEM_Inv 116 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.Mem_Ack 110230 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.MEM_Inv 1897 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.WB_Data 229 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.Ack_all 48 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.MEM_Inv 116 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data 75 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.Ack_all 33 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack 1395 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack_all 6335 0.00% 0.00%
+system.ruby.l2_cntrl0.S_I.Ack 271 0.00% 0.00%
+system.ruby.l2_cntrl0.S_I.Ack_all 271 0.00% 0.00%
+system.ruby.l2_cntrl0.S_I.MEM_Inv 3 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.Mem_Data 32147 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.Mem_Data 15306 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.Mem_Data 127449 0.00% 0.00%
+system.ruby.l2_cntrl0.SS_MB.L1_GETS 119 0.00% 0.00%
+system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 23603 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_GETS 38 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_GETX 1 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1708040 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.WB_Data 22711 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 2155 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.Unblock 3 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IB.WB_Data 3 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_SB.Unblock 24866 0.00% 0.00%
+system.ruby.dma_cntrl0.ReadRequest 814 0.00% 0.00%
+system.ruby.dma_cntrl0.WriteRequest 46736 0.00% 0.00%
+system.ruby.dma_cntrl0.Data 814 0.00% 0.00%
+system.ruby.dma_cntrl0.Ack 46736 0.00% 0.00%
+system.ruby.dma_cntrl0.READY.ReadRequest 814 0.00% 0.00%
+system.ruby.dma_cntrl0.READY.WriteRequest 46736 0.00% 0.00%
+system.ruby.dma_cntrl0.BUSY_RD.Data 814 0.00% 0.00%
+system.ruby.dma_cntrl0.BUSY_WR.Ack 46736 0.00% 0.00%
+system.ruby.dir_cntrl0.Fetch 174902 0.00% 0.00%
+system.ruby.dir_cntrl0.Data 97441 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Data 175365 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Ack 142512 0.00% 0.00%
+system.ruby.dir_cntrl0.DMA_READ 814 0.00% 0.00%
+system.ruby.dir_cntrl0.DMA_WRITE 46736 0.00% 0.00%
+system.ruby.dir_cntrl0.CleanReplacement 12789 0.00% 0.00%
+system.ruby.dir_cntrl0.I.Fetch 174902 0.00% 0.00%
+system.ruby.dir_cntrl0.I.DMA_READ 463 0.00% 0.00%
+system.ruby.dir_cntrl0.I.DMA_WRITE 45071 0.00% 0.00%
+system.ruby.dir_cntrl0.ID.Memory_Data 463 0.00% 0.00%
+system.ruby.dir_cntrl0.ID_W.Memory_Ack 45071 0.00% 0.00%
+system.ruby.dir_cntrl0.M.Data 95425 0.00% 0.00%
+system.ruby.dir_cntrl0.M.DMA_READ 351 0.00% 0.00%
+system.ruby.dir_cntrl0.M.DMA_WRITE 1665 0.00% 0.00%
+system.ruby.dir_cntrl0.M.CleanReplacement 12789 0.00% 0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data 174902 0.00% 0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack 95425 0.00% 0.00%
+system.ruby.dir_cntrl0.M_DRD.Data 351 0.00% 0.00%
+system.ruby.dir_cntrl0.M_DRDI.Memory_Ack 351 0.00% 0.00%
+system.ruby.dir_cntrl0.M_DWR.Data 1665 0.00% 0.00%
+system.ruby.dir_cntrl0.M_DWRI.Memory_Ack 1665 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
--- /dev/null
+Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009\r
+Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
+BIOS-provided physical RAM map:\r
+ BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)\r
+ BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)\r
+ BIOS-e820: 0000000000100000 - 0000000008000000 (usable)\r
+ BIOS-e820: 00000000ffff0000 - 0000000100000000 (reserved)\r
+end_pfn_map = 1048576\r
+kernel direct mapping tables up to 100000000 @ 8000-d000\r
+DMI 2.5 present.\r
+Zone PFN ranges:\r
+ DMA 0 -> 4096\r
+ DMA32 4096 -> 1048576\r
+ Normal 1048576 -> 1048576\r
+early_node_map[2] active PFN ranges\r
+ 0: 0 -> 159\r
+ 0: 256 -> 32768\r
+Intel MultiProcessor Specification v1.4\r
+MPTABLE: OEM ID: MPTABLE: Product ID: MPTABLE: APIC at: 0xFEE00000\r
+Processor #0 (Bootup-CPU)\r
+Processor #1\r
+I/O APIC #2 at 0xFEC00000.\r
+Setting APIC routing to flat\r
+Processors: 2\r
+Allocating PCI resources starting at 10000000 (gap: 8000000:f7ff0000)\r
+PERCPU: Allocating 34160 bytes of per cpu data\r
+Built 1 zonelists. Total pages: 30615\r
+Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
+Initializing CPU#0\r
+PID hash table entries: 512 (order: 9, 4096 bytes)\r
+Marking TSC unstable due to TSCs unsynchronized\r
+time.c: Detected 2000.000 MHz processor.\r
+Console: colour dummy device 80x25\r
+console handover: boot [earlyser0] -> real [ttyS0]\r
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
+Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)\r
+Checking aperture...\r
+Memory: 122004k/131072k available (3699k kernel code, 8516k reserved, 1767k data, 248k init)\r
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
+Mount-cache hash table entries: 256\r
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
+CPU: L2 Cache: 1024K (64 bytes/line)\r
+Freeing SMP alternatives: 34k freed\r
+Using local APIC timer interrupts.\r
+result 7812500\r
+Detected 7.812 MHz APIC timer.\r
+Booting processor 1/2 APIC 0x1\r
+Initializing CPU#1\r
+Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset\r
+CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)\r
+CPU: L2 Cache: 1024K (64 bytes/line)\r
+Fake M5 x86_64 CPU stepping 01\r
+Brought up 2 CPUs\r
+migration_cost=11\r
+NET: Registered protocol family 16\r
+PCI: Using configuration type 1\r
+SCSI subsystem initialized\r
+usbcore: registered new interface driver usbfs\r
+usbcore: registered new interface driver hub\r
+usbcore: registered new device driver usb\r
+PCI: Probing PCI hardware\r
+PCI-GART: No AMD northbridge found.\r
+NET: Registered protocol family 2\r
+IP route cache hash table entries: 1024 (order: 1, 8192 bytes)\r
+TCP established hash table entries: 4096 (order: 4, 98304 bytes)\r
+TCP bind hash table entries: 4096 (order: 4, 65536 bytes)\r
+TCP: Hash tables configured (established 4096 bind 4096)\r
+TCP reno registered\r
+Total HugeTLB memory allocated, 0\r
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\r
+io scheduler noop registered\r
+io scheduler deadline registered\r
+io scheduler cfq registered (default)\r
+Real Time Clock Driver v1.12ac\r
+Linux agpgart interface v0.102 (c) Dave Jones\r
+Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled\r
+serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 8250\r
+floppy0: no floppy controllers found\r
+RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize\r
+loop: module loaded\r
+Intel(R) PRO/1000 Network Driver - version 7.3.20-k2\r
+Copyright (c) 1999-2006 Intel Corporation.\r
+e100: Intel(R) PRO/100 Network Driver, 3.5.17-k4-NAPI\r
+e100: Copyright(c) 1999-2006 Intel Corporation\r
+forcedeth.c: Reverse Engineered nForce ethernet driver. Version 0.60.\r
+tun: Universal TUN/TAP device driver, 1.6\r
+tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>\r
+netconsole: not configured, aborting\r
+Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2\r
+ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx\r
+PIIX4: IDE controller at PCI slot 0000:00:04.0\r
+PCI: Enabling device 0000:00:04.0 (0000 -> 0001)\r
+PIIX4: chipset revision 0\r
+PIIX4: not 100% native mode: will probe irqs later\r
+ ide0: BM-DMA at 0x1000-0x1007, BIOS settings: hda:DMA, hdb:DMA\r
+ ide1: BM-DMA at 0x1008-0x100f, BIOS settings: hdc:DMA, hdd:DMA\r
+hda: M5 IDE Disk, ATA DISK drive\r
+hdb: M5 IDE Disk, ATA DISK drive\r
+ide0 at 0x1f0-0x1f7,0x3f6 on irq 14\r
+hda: max request size: 128KiB\r
+hda: 1048320 sectors (536 MB), CHS=1040/16/63, UDMA(33)\r
+ hda: hda1\r
+hdb: max request size: 128KiB\r
+hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33)\r
+ hdb: unknown partition table\r
+megaraid cmm: 2.20.2.7 (Release Date: Sun Jul 16 00:01:03 EST 2006)\r
+megaraid: 2.20.5.1 (Release Date: Thu Nov 16 15:32:35 EST 2006)\r
+megasas: 00.00.03.10-rc5 Thu May 17 10:09:32 PDT 2007\r
+Fusion MPT base driver 3.04.04\r
+Copyright (c) 1999-2007 LSI Logic Corporation\r
+Fusion MPT SPI Host driver 3.04.04\r
+Fusion MPT SAS Host driver 3.04.04\r
+ieee1394: raw1394: /dev/raw1394 device initialized\r
+USB Universal Host Controller Interface driver v3.0\r
+usbcore: registered new interface driver usblp\r
+drivers/usb/class/usblp.c: v0.13: USB Printer Device Class driver\r
+Initializing USB Mass Storage driver...\r
+usbcore: registered new interface driver usb-storage\r
+USB Mass Storage support registered.\r
+serio: i8042 KBD port at 0x60,0x64 irq 1\r
+serio: i8042 AUX port at 0x60,0x64 irq 12\r
+mice: PS/2 mouse device common for all mice\r
+input: AT Translated Set 2 keyboard as /class/input/input0\r
+device-mapper: ioctl: 4.11.0-ioctl (2006-10-12) initialised: dm-devel@redhat.com\r
+usbcore: registered new interface driver usbhid\r
+drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver\r
+oprofile: using timer interrupt.\r
+TCP cubic registered\r
+NET: Registered protocol family 1\r
+NET: Registered protocol family 10\r
+IPv6 over IPv4 tunneling driver\r
+input: PS/2 Generic Mouse as /class/input/input1\r
+NET: Registered protocol family 17\r
+EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended\r
+VFS: Mounted root (ext2 filesystem).\r
+Freeing unused kernel memory: 248k freed\r
+\rINIT: version 2.86 booting\r\r
+mounting filesystems...\r
+loading script...\r
+++ /dev/null
-[root]
-type=Root
-children=system
-full_system=false
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-init_param=0
-kernel=
-load_addr_mask=1099511627775
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=clk_domain dtb interrupts isa itb tracer workload
-checker=Null
-clk_domain=system.cpu.clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
-icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.cpu.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-
-[system.cpu.isa]
-type=AlphaISA
-
-[system.cpu.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-in_addr_map=true
-latency=30
-latency_var=0
-null=true
-range=0:134217727
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-mem_size=268435456
-no_mem_vec=false
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=2
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-memBuffer=system.ruby.dir_cntrl0.memBuffer
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_mem_ctrl_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=5
-size=268435456
-use_map=false
-version=0
-
-[system.ruby.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-clk_domain=system.ruby.memctrl_clk_domain
-dimm_bit_0=12
-dimms_per_channel=2
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-ruby_system=system.ruby
-tFaw=0
-version=0
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=0
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-to_l2_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl0.L1Dcache
-deadlock_threshold=500000
-icache=system.ruby.l1_cntrl0.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=L2cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=1
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_l1_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=15
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
-number_of_virtual_networks=10
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
-ruby_system=system.ruby
-topology=Crossbar
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l2_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.routers0]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=0
-virt_nets=10
-
-[system.ruby.network.routers1]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=1
-virt_nets=10
-
-[system.ruby.network.routers2]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=2
-virt_nets=10
-
-[system.ruby.network.routers3]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=3
-virt_nets=10
-
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-access_phys_mem=true
-clk_domain=system.clk_domain
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-voltage=1.000000
-
+++ /dev/null
-
-Profiler Stats
---------------
-Ruby_current_time: 138616
-Ruby_start_time: 0
-Ruby_cycles: 138616
-
-Busy Controller Counts:
-L1Cache-0:0
-L2Cache-0:0
-Directory-0:0
-
-
-Busy Bank Count:0
-
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-latency: [binsize: 8 max: 113 count: 8448 average: 15.4081 | standard deviation: 27.0652 | 6958 0 30 0 0 0 0 0 0 1354 91 2 4 8 1 ]
-latency: LD: [binsize: 8 max: 113 count: 1183 average: 37.6889 | standard deviation: 35.8062 | 600 0 13 0 0 0 0 0 0 529 34 0 2 4 1 ]
-latency: ST: [binsize: 8 max: 110 count: 865 average: 20.5237 | standard deviation: 31.2331 | 649 0 12 0 0 0 0 0 0 161 38 1 0 4 ]
-latency: IFETCH: [binsize: 8 max: 98 count: 6400 average: 10.5983 | standard deviation: 21.9085 | 5709 0 5 0 0 0 0 0 0 664 19 1 2 ]
-hit latency: [binsize: 1 max: 3 count: 6958 average: 3 | standard deviation: 0 | 0 0 0 6958 ]
-hit latency: LD: [binsize: 1 max: 3 count: 600 average: 3 | standard deviation: 0 | 0 0 0 600 ]
-hit latency: ST: [binsize: 1 max: 3 count: 649 average: 3 | standard deviation: 0 | 0 0 0 649 ]
-hit latency: IFETCH: [binsize: 1 max: 3 count: 5709 average: 3 | standard deviation: 0 | 0 0 0 5709 ]
-miss latency: [binsize: 8 max: 113 count: 1490 average: 73.3517 | standard deviation: 8.74134 | 0 0 30 0 0 0 0 0 0 1354 91 2 4 8 1 ]
-miss latency: LD: [binsize: 8 max: 113 count: 583 average: 73.3894 | standard deviation: 9.3046 | 0 0 13 0 0 0 0 0 0 529 34 0 2 4 1 ]
-miss latency: ST: [binsize: 8 max: 110 count: 216 average: 73.1759 | standard deviation: 14.4245 | 0 0 12 0 0 0 0 0 0 161 38 1 0 4 ]
-miss latency: IFETCH: [binsize: 8 max: 98 count: 691 average: 73.3748 | standard deviation: 5.19866 | 0 0 5 0 0 0 0 0 0 664 19 1 2 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 4 count: 9645 average: 0.0601348 | standard deviation: 0.486866 | 9500 0 0 0 145 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 2725 average: 0.212844 | standard deviation: 0.898073 | 2580 0 0 0 145 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+++ /dev/null
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: Sockets disabled, not accepting gdb connections
-hack: be nice to actually delete the event here
+++ /dev/null
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:12
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 138616 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000139 # Number of seconds simulated
-sim_ticks 138616 # Number of ticks simulated
-final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 22697 # Simulator instruction rate (inst/s)
-host_op_rate 22696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 492296 # Simulator tick rate (ticks/s)
-host_mem_usage 169832 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
-sim_insts 6390 # Number of instructions simulated
-sim_ops 6390 # Number of ops (including micro ops) simulated
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers0.percent_links_utilized 3.776801
-system.ruby.network.routers0.msg_count.Control::0 1490
-system.ruby.network.routers0.msg_count.Request_Control::0 1041
-system.ruby.network.routers0.msg_count.Response_Data::1 1490
-system.ruby.network.routers0.msg_count.Response_Control::1 1336
-system.ruby.network.routers0.msg_count.Response_Control::2 799
-system.ruby.network.routers0.msg_count.Writeback_Data::0 145
-system.ruby.network.routers0.msg_count.Writeback_Data::1 141
-system.ruby.network.routers0.msg_count.Writeback_Control::0 291
-system.ruby.network.routers0.msg_bytes.Control::0 11920
-system.ruby.network.routers0.msg_bytes.Request_Control::0 8328
-system.ruby.network.routers0.msg_bytes.Response_Data::1 107280
-system.ruby.network.routers0.msg_bytes.Response_Control::1 10688
-system.ruby.network.routers0.msg_bytes.Response_Control::2 6392
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328
-system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized 7.333389
-system.ruby.network.routers1.msg_count.Control::0 2950
-system.ruby.network.routers1.msg_count.Request_Control::0 1041
-system.ruby.network.routers1.msg_count.Response_Data::1 3227
-system.ruby.network.routers1.msg_count.Response_Control::1 3963
-system.ruby.network.routers1.msg_count.Response_Control::2 799
-system.ruby.network.routers1.msg_count.Writeback_Data::0 145
-system.ruby.network.routers1.msg_count.Writeback_Data::1 141
-system.ruby.network.routers1.msg_count.Writeback_Control::0 291
-system.ruby.network.routers1.msg_bytes.Control::0 23600
-system.ruby.network.routers1.msg_bytes.Request_Control::0 8328
-system.ruby.network.routers1.msg_bytes.Response_Data::1 232344
-system.ruby.network.routers1.msg_bytes.Response_Control::1 31704
-system.ruby.network.routers1.msg_bytes.Response_Control::2 6392
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328
-system.ruby.dir_cntrl0.memBuffer.memReq 1737 # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead 1460 # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite 277 # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh 963 # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles 343 # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls 343 # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.197467 # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy 166 # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy 149 # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait 24 # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount | 92 5.30% 5.30% | 21 1.21% 6.51% | 45 2.59% 9.10% | 54 3.11% 12.20% | 57 3.28% 15.49% | 174 10.02% 25.50% | 48 2.76% 28.27% | 18 1.04% 29.30% | 19 1.09% 30.40% | 22 1.27% 31.66% | 35 2.01% 33.68% | 37 2.13% 35.81% | 56 3.22% 39.03% | 59 3.40% 42.43% | 44 2.53% 44.96% | 36 2.07% 47.04% | 41 2.36% 49.40% | 24 1.38% 50.78% | 22 1.27% 52.04% | 28 1.61% 53.66% | 32 1.84% 55.50% | 48 2.76% 58.26% | 122 7.02% 65.28% | 36 2.07% 67.36% | 32 1.84% 69.20% | 25 1.44% 70.64% | 35 2.01% 72.65% | 96 5.53% 78.18% | 114 6.56% 84.74% | 185 10.65% 95.39% | 19 1.09% 96.49% | 61 3.51% 100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1737 # Number of accesses per bank
-
-system.ruby.network.routers2.percent_links_utilized 3.556588
-system.ruby.network.routers2.msg_count.Control::0 1460
-system.ruby.network.routers2.msg_count.Response_Data::1 1737
-system.ruby.network.routers2.msg_count.Response_Control::1 2627
-system.ruby.network.routers2.msg_bytes.Control::0 11680
-system.ruby.network.routers2.msg_bytes.Response_Data::1 125064
-system.ruby.network.routers2.msg_bytes.Response_Control::1 21016
-system.ruby.network.routers3.percent_links_utilized 4.888926
-system.ruby.network.routers3.msg_count.Control::0 2950
-system.ruby.network.routers3.msg_count.Request_Control::0 1041
-system.ruby.network.routers3.msg_count.Response_Data::1 3227
-system.ruby.network.routers3.msg_count.Response_Control::1 3963
-system.ruby.network.routers3.msg_count.Response_Control::2 799
-system.ruby.network.routers3.msg_count.Writeback_Data::0 145
-system.ruby.network.routers3.msg_count.Writeback_Data::1 141
-system.ruby.network.routers3.msg_count.Writeback_Control::0 291
-system.ruby.network.routers3.msg_bytes.Control::0 23600
-system.ruby.network.routers3.msg_bytes.Request_Control::0 8328
-system.ruby.network.routers3.msg_bytes.Response_Data::1 232344
-system.ruby.network.routers3.msg_bytes.Response_Control::1 31704
-system.ruby.network.routers3.msg_bytes.Response_Control::2 6392
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.msg_count.Control 8850
-system.ruby.network.msg_count.Request_Control 3123
-system.ruby.network.msg_count.Response_Data 9681
-system.ruby.network.msg_count.Response_Control 14286
-system.ruby.network.msg_count.Writeback_Data 858
-system.ruby.network.msg_count.Writeback_Control 873
-system.ruby.network.msg_byte.Control 70800
-system.ruby.network.msg_byte.Request_Control 24984
-system.ruby.network.msg_byte.Response_Data 697032
-system.ruby.network.msg_byte.Response_Control 114288
-system.ruby.network.msg_byte.Writeback_Data 61776
-system.ruby.network.msg_byte.Writeback_Control 6984
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1183 # DTB read hits
-system.cpu.dtb.read_misses 7 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1190 # DTB read accesses
-system.cpu.dtb.write_hits 865 # DTB write hits
-system.cpu.dtb.write_misses 3 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 868 # DTB write accesses
-system.cpu.dtb.data_hits 2048 # DTB hits
-system.cpu.dtb.data_misses 10 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2058 # DTB accesses
-system.cpu.itb.fetch_hits 6401 # ITB hits
-system.cpu.itb.fetch_misses 17 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 6418 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 138616 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 6390 # Number of instructions committed
-system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
-system.cpu.num_func_calls 251 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
-system.cpu.num_int_insts 6317 # number of integer instructions
-system.cpu.num_fp_insts 10 # number of float instructions
-system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
-system.cpu.num_mem_refs 2058 # number of memory refs
-system.cpu.num_load_insts 1190 # Number of load instructions
-system.cpu.num_store_insts 868 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 138616 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.ruby.network.routers0.throttle0.link_utilization 5.369871
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 1041
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 8328
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488
-system.ruby.network.routers0.throttle1.link_utilization 2.183731
-system.ruby.network.routers0.throttle1.msg_count.Control::0 1490
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 145
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 141
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 291
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11920
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 7200
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6392
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers1.throttle0.link_utilization 7.447192
-system.ruby.network.routers1.throttle0.msg_count.Control::0 1490
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 799
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 145
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 141
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 291
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11920
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105120
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18816
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6392
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers1.throttle1.link_utilization 7.219585
-system.ruby.network.routers1.throttle1.msg_count.Control::0 1460
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::0 1041
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1611
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::0 8328
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888
-system.ruby.network.routers2.throttle0.link_utilization 1.849714
-system.ruby.network.routers2.throttle0.msg_count.Control::0 1460
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400
-system.ruby.network.routers2.throttle1.link_utilization 5.263462
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616
-system.ruby.network.routers3.throttle0.link_utilization 5.369871
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::0 1041
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::0 8328
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488
-system.ruby.network.routers3.throttle1.link_utilization 7.447192
-system.ruby.network.routers3.throttle1.msg_count.Control::0 1490
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 799
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 145
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 141
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 291
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11920
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105120
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18816
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6392
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328
-system.ruby.network.routers3.throttle2.link_utilization 1.849714
-system.ruby.network.routers3.throttle2.msg_count.Control::0 1460
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
-system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11680
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 19944
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9400
-system.ruby.l1_cntrl0.Load 1183 0.00% 0.00%
-system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00%
-system.ruby.l1_cntrl0.Store 865 0.00% 0.00%
-system.ruby.l1_cntrl0.Inv 1041 0.00% 0.00%
-system.ruby.l1_cntrl0.L1_Replacement 1354 0.00% 0.00%
-system.ruby.l1_cntrl0.Data_Exclusive 583 0.00% 0.00%
-system.ruby.l1_cntrl0.Data_all_Acks 907 0.00% 0.00%
-system.ruby.l1_cntrl0.WB_Ack 436 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Load 525 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Ifetch 646 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Store 191 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Inv 356 0.00% 0.00%
-system.ruby.l1_cntrl0.I.Load 58 0.00% 0.00%
-system.ruby.l1_cntrl0.I.Ifetch 45 0.00% 0.00%
-system.ruby.l1_cntrl0.I.Store 25 0.00% 0.00%
-system.ruby.l1_cntrl0.I.L1_Replacement 556 0.00% 0.00%
-system.ruby.l1_cntrl0.S.Ifetch 5709 0.00% 0.00%
-system.ruby.l1_cntrl0.S.Inv 325 0.00% 0.00%
-system.ruby.l1_cntrl0.S.L1_Replacement 362 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Load 452 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Store 71 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Inv 219 0.00% 0.00%
-system.ruby.l1_cntrl0.E.L1_Replacement 291 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Load 148 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Store 578 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Inv 141 0.00% 0.00%
-system.ruby.l1_cntrl0.M.L1_Replacement 145 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.Data_Exclusive 583 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.Data_all_Acks 691 0.00% 0.00%
-system.ruby.l1_cntrl0.IM.Data_all_Acks 216 0.00% 0.00%
-system.ruby.l1_cntrl0.M_I.WB_Ack 436 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GET_INSTR 691 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETS 583 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETX 216 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_PUTX 436 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement 142 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement_clean 1310 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Data 1460 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Ack 1452 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data 141 0.00% 0.00%
-system.ruby.l2_cntrl0.Ack_all 900 0.00% 0.00%
-system.ruby.l2_cntrl0.Exclusive_Unblock 799 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GET_INSTR 686 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETS 570 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETX 204 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GET_INSTR 5 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L2_Replacement_clean 681 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETS 13 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETX 12 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement 134 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement_clean 277 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_PUTX 436 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement 8 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement_clean 352 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.Mem_Ack 1452 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.WB_Data 6 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.WB_Data 135 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.Ack_all 217 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.Ack_all 681 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.Mem_Data 570 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.Mem_Data 686 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.Mem_Data 204 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 799 0.00% 0.00%
-system.ruby.dir_cntrl0.Fetch 1460 0.00% 0.00%
-system.ruby.dir_cntrl0.Data 277 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Data 1460 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Ack 277 0.00% 0.00%
-system.ruby.dir_cntrl0.CleanReplacement 1175 0.00% 0.00%
-system.ruby.dir_cntrl0.I.Fetch 1460 0.00% 0.00%
-system.ruby.dir_cntrl0.M.Data 277 0.00% 0.00%
-system.ruby.dir_cntrl0.M.CleanReplacement 1175 0.00% 0.00%
-system.ruby.dir_cntrl0.IM.Memory_Data 1460 0.00% 0.00%
-system.ruby.dir_cntrl0.MI.Memory_Ack 277 0.00% 0.00%
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=timing
+mem_ranges=0:268435455
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=clk_domain dtb interrupts isa itb tracer workload
+checker=Null
+clk_domain=system.cpu.clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
+icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
+
+[system.cpu.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.isa]
+type=AlphaISA
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=0.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+in_addr_map=true
+latency=30
+latency_var=0
+null=true
+range=0:134217727
+
+[system.ruby]
+type=RubySystem
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+block_size_bytes=64
+clk_domain=system.ruby.clk_domain
+mem_size=268435456
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.ruby.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=2
+directory=system.ruby.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.ruby.dir_cntrl0.memBuffer
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_mem_ctrl_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=5
+size=268435456
+use_map=false
+version=0
+
+[system.ruby.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+clk_domain=system.ruby.memctrl_clk_domain
+dimm_bit_0=12
+dimms_per_channel=2
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+ruby_system=system.ruby
+tFaw=0
+version=0
+
+[system.ruby.l1_cntrl0]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl0.L1Dcache
+L1Icache=system.ruby.l1_cntrl0.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=0
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl0.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl0.sequencer
+to_l2_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.l1_cntrl0.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl0.L1Dcache
+deadlock_threshold=500000
+icache=system.ruby.l1_cntrl0.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cache
+L2cache=system.ruby.l2_cntrl0.L2cache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=1
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_l1_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.l2_cntrl0.L2cache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=15
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=512
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
+[system.ruby.network]
+type=SimpleNetwork
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+adaptive_routing=false
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+control_msg_size=8
+endpoint_bandwidth=1000
+ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+number_of_virtual_networks=10
+routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
+ruby_system=system.ruby
+topology=Crossbar
+
+[system.ruby.network.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl0
+int_node=system.ruby.network.routers0
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l2_cntrl0
+int_node=system.ruby.network.routers1
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.dir_cntrl0
+int_node=system.ruby.network.routers2
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=3
+node_a=system.ruby.network.routers0
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=4
+node_a=system.ruby.network.routers1
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=5
+node_a=system.ruby.network.routers2
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.routers0]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=0
+virt_nets=10
+
+[system.ruby.network.routers1]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=1
+virt_nets=10
+
+[system.ruby.network.routers2]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=2
+virt_nets=10
+
+[system.ruby.network.routers3]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=3
+virt_nets=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+clk_domain=system.clk_domain
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.system_port
+
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
--- /dev/null
+
+Profiler Stats
+--------------
+Ruby_current_time: 138616
+Ruby_start_time: 0
+Ruby_cycles: 138616
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8449 average: 1 | standard deviation: 0 | 0 8449 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+latency: [binsize: 8 max: 113 count: 8448 average: 15.4081 | standard deviation: 27.0652 | 6958 0 30 0 0 0 0 0 0 1354 91 2 4 8 1 ]
+latency: LD: [binsize: 8 max: 113 count: 1183 average: 37.6889 | standard deviation: 35.8062 | 600 0 13 0 0 0 0 0 0 529 34 0 2 4 1 ]
+latency: ST: [binsize: 8 max: 110 count: 865 average: 20.5237 | standard deviation: 31.2331 | 649 0 12 0 0 0 0 0 0 161 38 1 0 4 ]
+latency: IFETCH: [binsize: 8 max: 98 count: 6400 average: 10.5983 | standard deviation: 21.9085 | 5709 0 5 0 0 0 0 0 0 664 19 1 2 ]
+hit latency: [binsize: 1 max: 3 count: 6958 average: 3 | standard deviation: 0 | 0 0 0 6958 ]
+hit latency: LD: [binsize: 1 max: 3 count: 600 average: 3 | standard deviation: 0 | 0 0 0 600 ]
+hit latency: ST: [binsize: 1 max: 3 count: 649 average: 3 | standard deviation: 0 | 0 0 0 649 ]
+hit latency: IFETCH: [binsize: 1 max: 3 count: 5709 average: 3 | standard deviation: 0 | 0 0 0 5709 ]
+miss latency: [binsize: 8 max: 113 count: 1490 average: 73.3517 | standard deviation: 8.74134 | 0 0 30 0 0 0 0 0 0 1354 91 2 4 8 1 ]
+miss latency: LD: [binsize: 8 max: 113 count: 583 average: 73.3894 | standard deviation: 9.3046 | 0 0 13 0 0 0 0 0 0 529 34 0 2 4 1 ]
+miss latency: ST: [binsize: 8 max: 110 count: 216 average: 73.1759 | standard deviation: 14.4245 | 0 0 12 0 0 0 0 0 0 161 38 1 0 4 ]
+miss latency: IFETCH: [binsize: 8 max: 98 count: 691 average: 73.3748 | standard deviation: 5.19866 | 0 0 5 0 0 0 0 0 0 664 19 1 2 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 4 count: 9645 average: 0.0601348 | standard deviation: 0.486866 | 9500 0 0 0 145 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 2725 average: 0.212844 | standard deviation: 0.898073 | 2580 0 0 0 145 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 5879 average: 0 | standard deviation: 0 | 5879 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- /dev/null
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: Sockets disabled, not accepting gdb connections
+hack: be nice to actually delete the event here
--- /dev/null
+Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:12
+gem5 executing on zizzer
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 138616 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000139 # Number of seconds simulated
+sim_ticks 138616 # Number of ticks simulated
+final_tick 138616 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 22697 # Simulator instruction rate (inst/s)
+host_op_rate 22696 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 492296 # Simulator tick rate (ticks/s)
+host_mem_usage 169832 # Number of bytes of host memory used
+host_seconds 0.28 # Real time elapsed on the host
+sim_insts 6390 # Number of instructions simulated
+sim_ops 6390 # Number of ops (including micro ops) simulated
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 1249 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 799 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2048 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 5709 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 691 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 6400 # Number of cache demand accesses
+system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.network.routers0.percent_links_utilized 3.776801
+system.ruby.network.routers0.msg_count.Control::0 1490
+system.ruby.network.routers0.msg_count.Request_Control::0 1041
+system.ruby.network.routers0.msg_count.Response_Data::1 1490
+system.ruby.network.routers0.msg_count.Response_Control::1 1336
+system.ruby.network.routers0.msg_count.Response_Control::2 799
+system.ruby.network.routers0.msg_count.Writeback_Data::0 145
+system.ruby.network.routers0.msg_count.Writeback_Data::1 141
+system.ruby.network.routers0.msg_count.Writeback_Control::0 291
+system.ruby.network.routers0.msg_bytes.Control::0 11920
+system.ruby.network.routers0.msg_bytes.Request_Control::0 8328
+system.ruby.network.routers0.msg_bytes.Response_Data::1 107280
+system.ruby.network.routers0.msg_bytes.Response_Control::1 10688
+system.ruby.network.routers0.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2328
+system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 1460 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 1490 # Number of cache demand accesses
+system.ruby.network.routers1.percent_links_utilized 7.333389
+system.ruby.network.routers1.msg_count.Control::0 2950
+system.ruby.network.routers1.msg_count.Request_Control::0 1041
+system.ruby.network.routers1.msg_count.Response_Data::1 3227
+system.ruby.network.routers1.msg_count.Response_Control::1 3963
+system.ruby.network.routers1.msg_count.Response_Control::2 799
+system.ruby.network.routers1.msg_count.Writeback_Data::0 145
+system.ruby.network.routers1.msg_count.Writeback_Data::1 141
+system.ruby.network.routers1.msg_count.Writeback_Control::0 291
+system.ruby.network.routers1.msg_bytes.Control::0 23600
+system.ruby.network.routers1.msg_bytes.Request_Control::0 8328
+system.ruby.network.routers1.msg_bytes.Response_Data::1 232344
+system.ruby.network.routers1.msg_bytes.Response_Control::1 31704
+system.ruby.network.routers1.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2328
+system.ruby.dir_cntrl0.memBuffer.memReq 1737 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 1460 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 277 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 963 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 343 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 343 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.197467 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 166 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 149 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4 # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait 24 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 92 5.30% 5.30% | 21 1.21% 6.51% | 45 2.59% 9.10% | 54 3.11% 12.20% | 57 3.28% 15.49% | 174 10.02% 25.50% | 48 2.76% 28.27% | 18 1.04% 29.30% | 19 1.09% 30.40% | 22 1.27% 31.66% | 35 2.01% 33.68% | 37 2.13% 35.81% | 56 3.22% 39.03% | 59 3.40% 42.43% | 44 2.53% 44.96% | 36 2.07% 47.04% | 41 2.36% 49.40% | 24 1.38% 50.78% | 22 1.27% 52.04% | 28 1.61% 53.66% | 32 1.84% 55.50% | 48 2.76% 58.26% | 122 7.02% 65.28% | 36 2.07% 67.36% | 32 1.84% 69.20% | 25 1.44% 70.64% | 35 2.01% 72.65% | 96 5.53% 78.18% | 114 6.56% 84.74% | 185 10.65% 95.39% | 19 1.09% 96.49% | 61 3.51% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1737 # Number of accesses per bank
+
+system.ruby.network.routers2.percent_links_utilized 3.556588
+system.ruby.network.routers2.msg_count.Control::0 1460
+system.ruby.network.routers2.msg_count.Response_Data::1 1737
+system.ruby.network.routers2.msg_count.Response_Control::1 2627
+system.ruby.network.routers2.msg_bytes.Control::0 11680
+system.ruby.network.routers2.msg_bytes.Response_Data::1 125064
+system.ruby.network.routers2.msg_bytes.Response_Control::1 21016
+system.ruby.network.routers3.percent_links_utilized 4.888926
+system.ruby.network.routers3.msg_count.Control::0 2950
+system.ruby.network.routers3.msg_count.Request_Control::0 1041
+system.ruby.network.routers3.msg_count.Response_Data::1 3227
+system.ruby.network.routers3.msg_count.Response_Control::1 3963
+system.ruby.network.routers3.msg_count.Response_Control::2 799
+system.ruby.network.routers3.msg_count.Writeback_Data::0 145
+system.ruby.network.routers3.msg_count.Writeback_Data::1 141
+system.ruby.network.routers3.msg_count.Writeback_Control::0 291
+system.ruby.network.routers3.msg_bytes.Control::0 23600
+system.ruby.network.routers3.msg_bytes.Request_Control::0 8328
+system.ruby.network.routers3.msg_bytes.Response_Data::1 232344
+system.ruby.network.routers3.msg_bytes.Response_Control::1 31704
+system.ruby.network.routers3.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2328
+system.ruby.network.msg_count.Control 8850
+system.ruby.network.msg_count.Request_Control 3123
+system.ruby.network.msg_count.Response_Data 9681
+system.ruby.network.msg_count.Response_Control 14286
+system.ruby.network.msg_count.Writeback_Data 858
+system.ruby.network.msg_count.Writeback_Control 873
+system.ruby.network.msg_byte.Control 70800
+system.ruby.network.msg_byte.Request_Control 24984
+system.ruby.network.msg_byte.Response_Data 697032
+system.ruby.network.msg_byte.Response_Control 114288
+system.ruby.network.msg_byte.Writeback_Data 61776
+system.ruby.network.msg_byte.Writeback_Control 6984
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 1183 # DTB read hits
+system.cpu.dtb.read_misses 7 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 1190 # DTB read accesses
+system.cpu.dtb.write_hits 865 # DTB write hits
+system.cpu.dtb.write_misses 3 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 868 # DTB write accesses
+system.cpu.dtb.data_hits 2048 # DTB hits
+system.cpu.dtb.data_misses 10 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 2058 # DTB accesses
+system.cpu.itb.fetch_hits 6401 # ITB hits
+system.cpu.itb.fetch_misses 17 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 6418 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 17 # Number of system calls
+system.cpu.numCycles 138616 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 6390 # Number of instructions committed
+system.cpu.committedOps 6390 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 6317 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
+system.cpu.num_func_calls 251 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 749 # number of instructions that are conditional controls
+system.cpu.num_int_insts 6317 # number of integer instructions
+system.cpu.num_fp_insts 10 # number of float instructions
+system.cpu.num_int_register_reads 8285 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4568 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
+system.cpu.num_mem_refs 2058 # number of memory refs
+system.cpu.num_load_insts 1190 # Number of load instructions
+system.cpu.num_store_insts 868 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 138616 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.ruby.network.routers0.throttle0.link_utilization 5.369871
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 1041
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1490
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 436
+system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 8328
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107280
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3488
+system.ruby.network.routers0.throttle1.link_utilization 2.183731
+system.ruby.network.routers0.throttle1.msg_count.Control::0 1490
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 799
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 145
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 141
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 291
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0 11920
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 7200
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2328
+system.ruby.network.routers1.throttle0.link_utilization 7.447192
+system.ruby.network.routers1.throttle0.msg_count.Control::0 1490
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1460
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2352
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 799
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 145
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 141
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 291
+system.ruby.network.routers1.throttle0.msg_bytes.Control::0 11920
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 105120
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 18816
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2328
+system.ruby.network.routers1.throttle1.link_utilization 7.219585
+system.ruby.network.routers1.throttle1.msg_count.Control::0 1460
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::0 1041
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1767
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 1611
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11680
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::0 8328
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127224
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12888
+system.ruby.network.routers2.throttle0.link_utilization 1.849714
+system.ruby.network.routers2.throttle0.msg_count.Control::0 1460
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1175
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11680
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9400
+system.ruby.network.routers2.throttle1.link_utilization 5.263462
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1460
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1452
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105120
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11616
+system.ruby.network.routers3.throttle0.link_utilization 5.369871
+system.ruby.network.routers3.throttle0.msg_count.Request_Control::0 1041
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1490
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 436
+system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::0 8328
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107280
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3488
+system.ruby.network.routers3.throttle1.link_utilization 7.447192
+system.ruby.network.routers3.throttle1.msg_count.Control::0 1490
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1460
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2352
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 799
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 145
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 141
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 291
+system.ruby.network.routers3.throttle1.msg_bytes.Control::0 11920
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 105120
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 18816
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6392
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2328
+system.ruby.network.routers3.throttle2.link_utilization 1.849714
+system.ruby.network.routers3.throttle2.msg_count.Control::0 1460
+system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
+system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1175
+system.ruby.network.routers3.throttle2.msg_bytes.Control::0 11680
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 19944
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 9400
+system.ruby.l1_cntrl0.Load 1183 0.00% 0.00%
+system.ruby.l1_cntrl0.Ifetch 6400 0.00% 0.00%
+system.ruby.l1_cntrl0.Store 865 0.00% 0.00%
+system.ruby.l1_cntrl0.Inv 1041 0.00% 0.00%
+system.ruby.l1_cntrl0.L1_Replacement 1354 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_Exclusive 583 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_all_Acks 907 0.00% 0.00%
+system.ruby.l1_cntrl0.WB_Ack 436 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Load 525 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Ifetch 646 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Store 191 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Inv 356 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Load 58 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Ifetch 45 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Store 25 0.00% 0.00%
+system.ruby.l1_cntrl0.I.L1_Replacement 556 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Ifetch 5709 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Inv 325 0.00% 0.00%
+system.ruby.l1_cntrl0.S.L1_Replacement 362 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Load 452 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Store 71 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Inv 219 0.00% 0.00%
+system.ruby.l1_cntrl0.E.L1_Replacement 291 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Load 148 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Store 578 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Inv 141 0.00% 0.00%
+system.ruby.l1_cntrl0.M.L1_Replacement 145 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_Exclusive 583 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_all_Acks 691 0.00% 0.00%
+system.ruby.l1_cntrl0.IM.Data_all_Acks 216 0.00% 0.00%
+system.ruby.l1_cntrl0.M_I.WB_Ack 436 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GET_INSTR 691 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETS 583 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETX 216 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX 436 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement 142 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement_clean 1310 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Data 1460 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Ack 1452 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data 141 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack_all 900 0.00% 0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock 799 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GET_INSTR 686 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS 570 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX 204 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GET_INSTR 5 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement_clean 681 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETS 13 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETX 12 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement 134 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement_clean 277 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_PUTX 436 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement 8 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement_clean 352 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.Mem_Ack 1452 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.WB_Data 6 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data 135 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.Ack_all 217 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack_all 681 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.Mem_Data 570 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.Mem_Data 686 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.Mem_Data 204 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 799 0.00% 0.00%
+system.ruby.dir_cntrl0.Fetch 1460 0.00% 0.00%
+system.ruby.dir_cntrl0.Data 277 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Data 1460 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Ack 277 0.00% 0.00%
+system.ruby.dir_cntrl0.CleanReplacement 1175 0.00% 0.00%
+system.ruby.dir_cntrl0.I.Fetch 1460 0.00% 0.00%
+system.ruby.dir_cntrl0.M.Data 277 0.00% 0.00%
+system.ruby.dir_cntrl0.M.CleanReplacement 1175 0.00% 0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data 1460 0.00% 0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack 277 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-full_system=false
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-init_param=0
-kernel=
-load_addr_mask=1099511627775
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=TimingSimpleCPU
-children=clk_domain dtb interrupts isa itb tracer workload
-checker=Null
-clk_domain=system.cpu.clk_domain
-cpu_id=0
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-switched_out=false
-system=system
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
-icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.cpu.dtb]
-type=AlphaTLB
-size=64
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
-
-[system.cpu.isa]
-type=AlphaISA
-
-[system.cpu.itb]
-type=AlphaTLB
-size=48
-
-[system.cpu.tracer]
-type=ExeTracer
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=hello
-cwd=
-egid=100
-env=
-errout=cerr
-euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
-gid=100
-input=cin
-max_stack_size=67108864
-output=cout
-pid=100
-ppid=99
-simpoint=0
-system=system
-uid=100
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-in_addr_map=true
-latency=30
-latency_var=0
-null=true
-range=0:134217727
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-mem_size=268435456
-no_mem_vec=false
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=2
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-memBuffer=system.ruby.dir_cntrl0.memBuffer
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_mem_ctrl_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=5
-size=268435456
-use_map=false
-version=0
-
-[system.ruby.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-clk_domain=system.ruby.memctrl_clk_domain
-dimm_bit_0=12
-dimms_per_channel=2
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-ruby_system=system.ruby
-tFaw=0
-version=0
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=0
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-to_l2_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl0.L1Dcache
-deadlock_threshold=500000
-icache=system.ruby.l1_cntrl0.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.cpu.icache_port system.cpu.dcache_port
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=L2cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=1
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_l1_latency=1
-transitions_per_cycle=4
-version=0
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=15
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
-number_of_virtual_networks=10
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
-ruby_system=system.ruby
-topology=Crossbar
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l2_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.routers0]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=0
-virt_nets=10
-
-[system.ruby.network.routers1]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=1
-virt_nets=10
-
-[system.ruby.network.routers2]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=2
-virt_nets=10
-
-[system.ruby.network.routers3]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=3
-virt_nets=10
-
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-access_phys_mem=true
-clk_domain=system.clk_domain
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-voltage=1.000000
-
+++ /dev/null
-
-Profiler Stats
---------------
-Ruby_current_time: 52548
-Ruby_start_time: 0
-Ruby_cycles: 52548
-
-Busy Controller Counts:
-L1Cache-0:0
-L2Cache-0:0
-Directory-0:0
-
-
-Busy Bank Count:0
-
-sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-latency: [binsize: 8 max: 116 count: 3294 average: 14.9526 | standard deviation: 26.5342 | 2722 0 25 0 0 0 0 0 0 520 21 3 0 2 1 ]
-latency: LD: [binsize: 8 max: 116 count: 415 average: 36.6627 | standard deviation: 35.6119 | 211 0 12 0 0 0 0 0 0 181 8 1 0 1 1 ]
-latency: ST: [binsize: 8 max: 106 count: 294 average: 18.9456 | standard deviation: 29.8676 | 226 0 4 0 0 0 0 0 0 59 4 0 0 1 ]
-latency: IFETCH: [binsize: 8 max: 89 count: 2585 average: 11.0132 | standard deviation: 22.3578 | 2285 0 9 0 0 0 0 0 0 280 9 2 ]
-hit latency: [binsize: 1 max: 3 count: 2722 average: 3 | standard deviation: 0 | 0 0 0 2722 ]
-hit latency: LD: [binsize: 1 max: 3 count: 211 average: 3 | standard deviation: 0 | 0 0 0 211 ]
-hit latency: ST: [binsize: 1 max: 3 count: 226 average: 3 | standard deviation: 0 | 0 0 0 226 ]
-hit latency: IFETCH: [binsize: 1 max: 3 count: 2285 average: 3 | standard deviation: 0 | 0 0 0 2285 ]
-miss latency: [binsize: 8 max: 116 count: 572 average: 71.8322 | standard deviation: 11.764 | 0 0 25 0 0 0 0 0 0 520 21 3 0 2 1 ]
-miss latency: LD: [binsize: 8 max: 116 count: 204 average: 71.4804 | standard deviation: 13.7953 | 0 0 12 0 0 0 0 0 0 181 8 1 0 1 1 ]
-miss latency: ST: [binsize: 8 max: 106 count: 68 average: 71.9412 | standard deviation: 13.8941 | 0 0 4 0 0 0 0 0 0 59 4 0 0 1 ]
-miss latency: IFETCH: [binsize: 8 max: 89 count: 300 average: 72.0467 | standard deviation: 9.57561 | 0 0 9 0 0 0 0 0 0 280 9 2 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 1 max: 4 count: 3612 average: 0.0498339 | standard deviation: 0.444044 | 3567 0 0 0 45 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 968 average: 0.18595 | standard deviation: 0.842879 | 923 0 0 0 45 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 2213 average: 0 | standard deviation: 0 | 2213 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+++ /dev/null
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: Sockets disabled, not accepting gdb connections
-warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
-hack: be nice to actually delete the event here
+++ /dev/null
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:13
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Hello world!
-Exiting @ tick 52575 because target called exit()
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000053 # Number of seconds simulated
-sim_ticks 52548 # Number of ticks simulated
-final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 24906 # Simulator instruction rate (inst/s)
-host_op_rate 24901 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 507678 # Simulator tick rate (ticks/s)
-host_mem_usage 168520 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
-sim_insts 2577 # Number of instructions simulated
-sim_ops 2577 # Number of ops (including micro ops) simulated
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers0.percent_links_utilized 3.786062
-system.ruby.network.routers0.msg_count.Control::0 572
-system.ruby.network.routers0.msg_count.Request_Control::0 431
-system.ruby.network.routers0.msg_count.Response_Data::1 572
-system.ruby.network.routers0.msg_count.Response_Control::1 493
-system.ruby.network.routers0.msg_count.Response_Control::2 272
-system.ruby.network.routers0.msg_count.Writeback_Data::0 45
-system.ruby.network.routers0.msg_count.Writeback_Data::1 62
-system.ruby.network.routers0.msg_count.Writeback_Control::0 79
-system.ruby.network.routers0.msg_bytes.Control::0 4576
-system.ruby.network.routers0.msg_bytes.Request_Control::0 3448
-system.ruby.network.routers0.msg_bytes.Response_Data::1 41184
-system.ruby.network.routers0.msg_bytes.Response_Control::1 3944
-system.ruby.network.routers0.msg_bytes.Response_Control::2 2176
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632
-system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized 7.293332
-system.ruby.network.routers1.msg_count.Control::0 1119
-system.ruby.network.routers1.msg_count.Request_Control::0 431
-system.ruby.network.routers1.msg_count.Response_Data::1 1222
-system.ruby.network.routers1.msg_count.Response_Control::1 1468
-system.ruby.network.routers1.msg_count.Response_Control::2 272
-system.ruby.network.routers1.msg_count.Writeback_Data::0 45
-system.ruby.network.routers1.msg_count.Writeback_Data::1 62
-system.ruby.network.routers1.msg_count.Writeback_Control::0 79
-system.ruby.network.routers1.msg_bytes.Control::0 8952
-system.ruby.network.routers1.msg_bytes.Request_Control::0 3448
-system.ruby.network.routers1.msg_bytes.Response_Data::1 87984
-system.ruby.network.routers1.msg_bytes.Response_Control::1 11744
-system.ruby.network.routers1.msg_bytes.Response_Control::2 2176
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632
-system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles 120 # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls 120 # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.184615 # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy 61 # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy 51 # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memArbWait 8 # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount | 26 4.00% 4.00% | 14 2.15% 6.15% | 0 0.00% 6.15% | 49 7.54% 13.69% | 21 3.23% 16.92% | 21 3.23% 20.15% | 42 6.46% 26.62% | 25 3.85% 30.46% | 6 0.92% 31.38% | 4 0.62% 32.00% | 7 1.08% 33.08% | 4 0.62% 33.69% | 24 3.69% 37.38% | 42 6.46% 43.85% | 26 4.00% 47.85% | 3 0.46% 48.31% | 5 0.77% 49.08% | 7 1.08% 50.15% | 7 1.08% 51.23% | 18 2.77% 54.00% | 10 1.54% 55.54% | 29 4.46% 60.00% | 15 2.31% 62.31% | 50 7.69% 70.00% | 19 2.92% 72.92% | 5 0.77% 73.69% | 6 0.92% 74.62% | 16 2.46% 77.08% | 14 2.15% 79.23% | 24 3.69% 82.92% | 19 2.92% 85.85% | 92 14.15% 100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total 650 # Number of accesses per bank
-
-system.ruby.network.routers2.percent_links_utilized 3.507270
-system.ruby.network.routers2.msg_count.Control::0 547
-system.ruby.network.routers2.msg_count.Response_Data::1 650
-system.ruby.network.routers2.msg_count.Response_Control::1 975
-system.ruby.network.routers2.msg_bytes.Control::0 4376
-system.ruby.network.routers2.msg_bytes.Response_Data::1 46800
-system.ruby.network.routers2.msg_bytes.Response_Control::1 7800
-system.ruby.network.routers3.percent_links_utilized 4.862221
-system.ruby.network.routers3.msg_count.Control::0 1119
-system.ruby.network.routers3.msg_count.Request_Control::0 431
-system.ruby.network.routers3.msg_count.Response_Data::1 1222
-system.ruby.network.routers3.msg_count.Response_Control::1 1468
-system.ruby.network.routers3.msg_count.Response_Control::2 272
-system.ruby.network.routers3.msg_count.Writeback_Data::0 45
-system.ruby.network.routers3.msg_count.Writeback_Data::1 62
-system.ruby.network.routers3.msg_count.Writeback_Control::0 79
-system.ruby.network.routers3.msg_bytes.Control::0 8952
-system.ruby.network.routers3.msg_bytes.Request_Control::0 3448
-system.ruby.network.routers3.msg_bytes.Response_Data::1 87984
-system.ruby.network.routers3.msg_bytes.Response_Control::1 11744
-system.ruby.network.routers3.msg_bytes.Response_Control::2 2176
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632
-system.ruby.network.msg_count.Control 3357
-system.ruby.network.msg_count.Request_Control 1293
-system.ruby.network.msg_count.Response_Data 3666
-system.ruby.network.msg_count.Response_Control 5220
-system.ruby.network.msg_count.Writeback_Data 321
-system.ruby.network.msg_count.Writeback_Control 237
-system.ruby.network.msg_byte.Control 26856
-system.ruby.network.msg_byte.Request_Control 10344
-system.ruby.network.msg_byte.Response_Data 263952
-system.ruby.network.msg_byte.Response_Control 41760
-system.ruby.network.msg_byte.Writeback_Data 23112
-system.ruby.network.msg_byte.Writeback_Control 1896
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 415 # DTB read hits
-system.cpu.dtb.read_misses 4 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 419 # DTB read accesses
-system.cpu.dtb.write_hits 294 # DTB write hits
-system.cpu.dtb.write_misses 4 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 298 # DTB write accesses
-system.cpu.dtb.data_hits 709 # DTB hits
-system.cpu.dtb.data_misses 8 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 717 # DTB accesses
-system.cpu.itb.fetch_hits 2586 # ITB hits
-system.cpu.itb.fetch_misses 11 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2597 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 52548 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 2577 # Number of instructions committed
-system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
-system.cpu.num_func_calls 140 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
-system.cpu.num_int_insts 2375 # number of integer instructions
-system.cpu.num_fp_insts 6 # number of float instructions
-system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 717 # number of memory refs
-system.cpu.num_load_insts 419 # Number of load instructions
-system.cpu.num_store_insts 298 # Number of store instructions
-system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 52548 # Number of busy cycles
-system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.ruby.network.routers0.throttle0.link_utilization 5.426467
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 431
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 3448
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992
-system.ruby.network.routers0.throttle1.link_utilization 2.145657
-system.ruby.network.routers0.throttle1.msg_count.Control::0 572
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 45
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 62
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 79
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 4576
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 2952
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 2176
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers1.throttle0.link_utilization 7.342810
-system.ruby.network.routers1.throttle0.msg_count.Control::0 572
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 272
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 45
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 62
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 79
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0 4576
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 39384
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7264
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 2176
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers1.throttle1.link_utilization 7.243853
-system.ruby.network.routers1.throttle1.msg_count.Control::0 547
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::0 431
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 560
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::0 3448
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480
-system.ruby.network.routers2.throttle0.link_utilization 1.817386
-system.ruby.network.routers2.throttle0.msg_count.Control::0 547
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488
-system.ruby.network.routers2.throttle1.link_utilization 5.197153
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312
-system.ruby.network.routers3.throttle0.link_utilization 5.426467
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::0 431
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::0 3448
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992
-system.ruby.network.routers3.throttle1.link_utilization 7.342810
-system.ruby.network.routers3.throttle1.msg_count.Control::0 572
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 272
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 45
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 62
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 79
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0 4576
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 39384
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7264
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 2176
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers3.throttle2.link_utilization 1.817386
-system.ruby.network.routers3.throttle2.msg_count.Control::0 547
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103
-system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0 4376
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 7416
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 3488
-system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
-system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
-system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
-system.ruby.l1_cntrl0.Inv 431 0.00% 0.00%
-system.ruby.l1_cntrl0.L1_Replacement 502 0.00% 0.00%
-system.ruby.l1_cntrl0.Data_Exclusive 204 0.00% 0.00%
-system.ruby.l1_cntrl0.Data_all_Acks 368 0.00% 0.00%
-system.ruby.l1_cntrl0.WB_Ack 124 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Inv 162 0.00% 0.00%
-system.ruby.l1_cntrl0.I.Load 22 0.00% 0.00%
-system.ruby.l1_cntrl0.I.Ifetch 30 0.00% 0.00%
-system.ruby.l1_cntrl0.I.Store 10 0.00% 0.00%
-system.ruby.l1_cntrl0.I.L1_Replacement 206 0.00% 0.00%
-system.ruby.l1_cntrl0.S.Ifetch 2285 0.00% 0.00%
-system.ruby.l1_cntrl0.S.Inv 124 0.00% 0.00%
-system.ruby.l1_cntrl0.S.L1_Replacement 172 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Load 140 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Store 41 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Inv 83 0.00% 0.00%
-system.ruby.l1_cntrl0.E.L1_Replacement 79 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Load 71 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Store 185 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Inv 62 0.00% 0.00%
-system.ruby.l1_cntrl0.M.L1_Replacement 45 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.Data_Exclusive 204 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.Data_all_Acks 300 0.00% 0.00%
-system.ruby.l1_cntrl0.IM.Data_all_Acks 68 0.00% 0.00%
-system.ruby.l1_cntrl0.M_I.WB_Ack 124 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GET_INSTR 300 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETS 204 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETX 68 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_PUTX 124 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement 43 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement_clean 496 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Data 547 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Ack 539 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data 62 0.00% 0.00%
-system.ruby.l2_cntrl0.Ack_all 369 0.00% 0.00%
-system.ruby.l2_cntrl0.Exclusive_Unblock 272 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GET_INSTR 291 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETS 192 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETX 64 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GET_INSTR 9 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L2_Replacement_clean 286 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETS 12 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETX 4 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement 39 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement_clean 69 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_PUTX 124 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement 4 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement_clean 141 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.Mem_Ack 539 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.WB_Data 2 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.WB_Data 60 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.Ack_all 81 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.Ack_all 286 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.Mem_Data 192 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.Mem_Data 291 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.Mem_Data 64 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 272 0.00% 0.00%
-system.ruby.dir_cntrl0.Fetch 547 0.00% 0.00%
-system.ruby.dir_cntrl0.Data 103 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Data 547 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Ack 103 0.00% 0.00%
-system.ruby.dir_cntrl0.CleanReplacement 436 0.00% 0.00%
-system.ruby.dir_cntrl0.I.Fetch 547 0.00% 0.00%
-system.ruby.dir_cntrl0.M.Data 103 0.00% 0.00%
-system.ruby.dir_cntrl0.M.CleanReplacement 436 0.00% 0.00%
-system.ruby.dir_cntrl0.IM.Memory_Data 547 0.00% 0.00%
-system.ruby.dir_cntrl0.MI.Memory_Ack 103 0.00% 0.00%
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=clk_domain cpu physmem ruby sys_port_proxy voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=timing
+mem_ranges=0:268435455
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.cpu]
+type=TimingSimpleCPU
+children=clk_domain dtb interrupts isa itb tracer workload
+checker=Null
+clk_domain=system.cpu.clk_domain
+cpu_id=0
+do_checkpoint_insts=true
+do_quiesce=true
+do_statistics_insts=true
+dtb=system.cpu.dtb
+function_trace=false
+function_trace_start=0
+interrupts=system.cpu.interrupts
+isa=system.cpu.isa
+itb=system.cpu.itb
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+numThreads=1
+profile=0
+progress_interval=0
+simpoint_start_insts=
+switched_out=false
+system=system
+tracer=system.cpu.tracer
+workload=system.cpu.workload
+dcache_port=system.ruby.l1_cntrl0.sequencer.slave[1]
+icache_port=system.ruby.l1_cntrl0.sequencer.slave[0]
+
+[system.cpu.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.cpu.dtb]
+type=AlphaTLB
+size=64
+
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
+[system.cpu.isa]
+type=AlphaISA
+
+[system.cpu.itb]
+type=AlphaTLB
+size=48
+
+[system.cpu.tracer]
+type=ExeTracer
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=hello
+cwd=
+egid=100
+env=
+errout=cerr
+euid=100
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+gid=100
+input=cin
+max_stack_size=67108864
+output=cout
+pid=100
+ppid=99
+simpoint=0
+system=system
+uid=100
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=0.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+in_addr_map=true
+latency=30
+latency_var=0
+null=true
+range=0:134217727
+
+[system.ruby]
+type=RubySystem
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+block_size_bytes=64
+clk_domain=system.ruby.clk_domain
+mem_size=268435456
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.ruby.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=2
+directory=system.ruby.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.ruby.dir_cntrl0.memBuffer
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_mem_ctrl_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=5
+size=268435456
+use_map=false
+version=0
+
+[system.ruby.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+clk_domain=system.ruby.memctrl_clk_domain
+dimm_bit_0=12
+dimms_per_channel=2
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+ruby_system=system.ruby
+tFaw=0
+version=0
+
+[system.ruby.l1_cntrl0]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl0.L1Dcache
+L1Icache=system.ruby.l1_cntrl0.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=0
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl0.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl0.sequencer
+to_l2_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.l1_cntrl0.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl0.L1Dcache
+deadlock_threshold=500000
+icache=system.ruby.l1_cntrl0.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.cpu.icache_port system.cpu.dcache_port
+
+[system.ruby.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cache
+L2cache=system.ruby.l2_cntrl0.L2cache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=1
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_l1_latency=1
+transitions_per_cycle=4
+version=0
+
+[system.ruby.l2_cntrl0.L2cache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=15
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=512
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
+[system.ruby.network]
+type=SimpleNetwork
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+adaptive_routing=false
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+control_msg_size=8
+endpoint_bandwidth=1000
+ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+number_of_virtual_networks=10
+routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
+ruby_system=system.ruby
+topology=Crossbar
+
+[system.ruby.network.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl0
+int_node=system.ruby.network.routers0
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l2_cntrl0
+int_node=system.ruby.network.routers1
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.dir_cntrl0
+int_node=system.ruby.network.routers2
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=3
+node_a=system.ruby.network.routers0
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=4
+node_a=system.ruby.network.routers1
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=5
+node_a=system.ruby.network.routers2
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.routers0]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=0
+virt_nets=10
+
+[system.ruby.network.routers1]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=1
+virt_nets=10
+
+[system.ruby.network.routers2]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=2
+virt_nets=10
+
+[system.ruby.network.routers3]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=3
+virt_nets=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+clk_domain=system.clk_domain
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.system_port
+
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
--- /dev/null
+
+Profiler Stats
+--------------
+Ruby_current_time: 52548
+Ruby_start_time: 0
+Ruby_cycles: 52548
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 1 count: 3295 average: 1 | standard deviation: 0 | 0 3295 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+latency: [binsize: 8 max: 116 count: 3294 average: 14.9526 | standard deviation: 26.5342 | 2722 0 25 0 0 0 0 0 0 520 21 3 0 2 1 ]
+latency: LD: [binsize: 8 max: 116 count: 415 average: 36.6627 | standard deviation: 35.6119 | 211 0 12 0 0 0 0 0 0 181 8 1 0 1 1 ]
+latency: ST: [binsize: 8 max: 106 count: 294 average: 18.9456 | standard deviation: 29.8676 | 226 0 4 0 0 0 0 0 0 59 4 0 0 1 ]
+latency: IFETCH: [binsize: 8 max: 89 count: 2585 average: 11.0132 | standard deviation: 22.3578 | 2285 0 9 0 0 0 0 0 0 280 9 2 ]
+hit latency: [binsize: 1 max: 3 count: 2722 average: 3 | standard deviation: 0 | 0 0 0 2722 ]
+hit latency: LD: [binsize: 1 max: 3 count: 211 average: 3 | standard deviation: 0 | 0 0 0 211 ]
+hit latency: ST: [binsize: 1 max: 3 count: 226 average: 3 | standard deviation: 0 | 0 0 0 226 ]
+hit latency: IFETCH: [binsize: 1 max: 3 count: 2285 average: 3 | standard deviation: 0 | 0 0 0 2285 ]
+miss latency: [binsize: 8 max: 116 count: 572 average: 71.8322 | standard deviation: 11.764 | 0 0 25 0 0 0 0 0 0 520 21 3 0 2 1 ]
+miss latency: LD: [binsize: 8 max: 116 count: 204 average: 71.4804 | standard deviation: 13.7953 | 0 0 12 0 0 0 0 0 0 181 8 1 0 1 1 ]
+miss latency: ST: [binsize: 8 max: 106 count: 68 average: 71.9412 | standard deviation: 13.8941 | 0 0 4 0 0 0 0 0 0 59 4 0 0 1 ]
+miss latency: IFETCH: [binsize: 8 max: 89 count: 300 average: 72.0467 | standard deviation: 9.57561 | 0 0 9 0 0 0 0 0 0 280 9 2 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 4 count: 3612 average: 0.0498339 | standard deviation: 0.444044 | 3567 0 0 0 45 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 4 count: 968 average: 0.18595 | standard deviation: 0.842879 | 923 0 0 0 45 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 2213 average: 0 | standard deviation: 0 | 2213 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- /dev/null
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: Sockets disabled, not accepting gdb connections
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+hack: be nice to actually delete the event here
--- /dev/null
+Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:13
+gem5 executing on zizzer
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+Hello world!
+Exiting @ tick 52575 because target called exit()
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000053 # Number of seconds simulated
+sim_ticks 52548 # Number of ticks simulated
+final_tick 52548 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_inst_rate 24906 # Simulator instruction rate (inst/s)
+host_op_rate 24901 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 507678 # Simulator tick rate (ticks/s)
+host_mem_usage 168520 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 2285 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 300 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
+system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.network.routers0.percent_links_utilized 3.786062
+system.ruby.network.routers0.msg_count.Control::0 572
+system.ruby.network.routers0.msg_count.Request_Control::0 431
+system.ruby.network.routers0.msg_count.Response_Data::1 572
+system.ruby.network.routers0.msg_count.Response_Control::1 493
+system.ruby.network.routers0.msg_count.Response_Control::2 272
+system.ruby.network.routers0.msg_count.Writeback_Data::0 45
+system.ruby.network.routers0.msg_count.Writeback_Data::1 62
+system.ruby.network.routers0.msg_count.Writeback_Control::0 79
+system.ruby.network.routers0.msg_bytes.Control::0 4576
+system.ruby.network.routers0.msg_bytes.Request_Control::0 3448
+system.ruby.network.routers0.msg_bytes.Response_Data::1 41184
+system.ruby.network.routers0.msg_bytes.Response_Control::1 3944
+system.ruby.network.routers0.msg_bytes.Response_Control::2 2176
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632
+system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses
+system.ruby.network.routers1.percent_links_utilized 7.293332
+system.ruby.network.routers1.msg_count.Control::0 1119
+system.ruby.network.routers1.msg_count.Request_Control::0 431
+system.ruby.network.routers1.msg_count.Response_Data::1 1222
+system.ruby.network.routers1.msg_count.Response_Control::1 1468
+system.ruby.network.routers1.msg_count.Response_Control::2 272
+system.ruby.network.routers1.msg_count.Writeback_Data::0 45
+system.ruby.network.routers1.msg_count.Writeback_Data::1 62
+system.ruby.network.routers1.msg_count.Writeback_Control::0 79
+system.ruby.network.routers1.msg_bytes.Control::0 8952
+system.ruby.network.routers1.msg_bytes.Request_Control::0 3448
+system.ruby.network.routers1.msg_bytes.Response_Data::1 87984
+system.ruby.network.routers1.msg_bytes.Response_Control::1 11744
+system.ruby.network.routers1.msg_bytes.Response_Control::2 2176
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632
+system.ruby.dir_cntrl0.memBuffer.memReq 650 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 547 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 103 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 365 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 120 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 120 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.184615 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 61 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 51 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memArbWait 8 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 26 4.00% 4.00% | 14 2.15% 6.15% | 0 0.00% 6.15% | 49 7.54% 13.69% | 21 3.23% 16.92% | 21 3.23% 20.15% | 42 6.46% 26.62% | 25 3.85% 30.46% | 6 0.92% 31.38% | 4 0.62% 32.00% | 7 1.08% 33.08% | 4 0.62% 33.69% | 24 3.69% 37.38% | 42 6.46% 43.85% | 26 4.00% 47.85% | 3 0.46% 48.31% | 5 0.77% 49.08% | 7 1.08% 50.15% | 7 1.08% 51.23% | 18 2.77% 54.00% | 10 1.54% 55.54% | 29 4.46% 60.00% | 15 2.31% 62.31% | 50 7.69% 70.00% | 19 2.92% 72.92% | 5 0.77% 73.69% | 6 0.92% 74.62% | 16 2.46% 77.08% | 14 2.15% 79.23% | 24 3.69% 82.92% | 19 2.92% 85.85% | 92 14.15% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 650 # Number of accesses per bank
+
+system.ruby.network.routers2.percent_links_utilized 3.507270
+system.ruby.network.routers2.msg_count.Control::0 547
+system.ruby.network.routers2.msg_count.Response_Data::1 650
+system.ruby.network.routers2.msg_count.Response_Control::1 975
+system.ruby.network.routers2.msg_bytes.Control::0 4376
+system.ruby.network.routers2.msg_bytes.Response_Data::1 46800
+system.ruby.network.routers2.msg_bytes.Response_Control::1 7800
+system.ruby.network.routers3.percent_links_utilized 4.862221
+system.ruby.network.routers3.msg_count.Control::0 1119
+system.ruby.network.routers3.msg_count.Request_Control::0 431
+system.ruby.network.routers3.msg_count.Response_Data::1 1222
+system.ruby.network.routers3.msg_count.Response_Control::1 1468
+system.ruby.network.routers3.msg_count.Response_Control::2 272
+system.ruby.network.routers3.msg_count.Writeback_Data::0 45
+system.ruby.network.routers3.msg_count.Writeback_Data::1 62
+system.ruby.network.routers3.msg_count.Writeback_Control::0 79
+system.ruby.network.routers3.msg_bytes.Control::0 8952
+system.ruby.network.routers3.msg_bytes.Request_Control::0 3448
+system.ruby.network.routers3.msg_bytes.Response_Data::1 87984
+system.ruby.network.routers3.msg_bytes.Response_Control::1 11744
+system.ruby.network.routers3.msg_bytes.Response_Control::2 2176
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632
+system.ruby.network.msg_count.Control 3357
+system.ruby.network.msg_count.Request_Control 1293
+system.ruby.network.msg_count.Response_Data 3666
+system.ruby.network.msg_count.Response_Control 5220
+system.ruby.network.msg_count.Writeback_Data 321
+system.ruby.network.msg_count.Writeback_Control 237
+system.ruby.network.msg_byte.Control 26856
+system.ruby.network.msg_byte.Request_Control 10344
+system.ruby.network.msg_byte.Response_Data 263952
+system.ruby.network.msg_byte.Response_Control 41760
+system.ruby.network.msg_byte.Writeback_Data 23112
+system.ruby.network.msg_byte.Writeback_Control 1896
+system.cpu.dtb.fetch_hits 0 # ITB hits
+system.cpu.dtb.fetch_misses 0 # ITB misses
+system.cpu.dtb.fetch_acv 0 # ITB acv
+system.cpu.dtb.fetch_accesses 0 # ITB accesses
+system.cpu.dtb.read_hits 415 # DTB read hits
+system.cpu.dtb.read_misses 4 # DTB read misses
+system.cpu.dtb.read_acv 0 # DTB read access violations
+system.cpu.dtb.read_accesses 419 # DTB read accesses
+system.cpu.dtb.write_hits 294 # DTB write hits
+system.cpu.dtb.write_misses 4 # DTB write misses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_accesses 298 # DTB write accesses
+system.cpu.dtb.data_hits 709 # DTB hits
+system.cpu.dtb.data_misses 8 # DTB misses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_accesses 717 # DTB accesses
+system.cpu.itb.fetch_hits 2586 # ITB hits
+system.cpu.itb.fetch_misses 11 # ITB misses
+system.cpu.itb.fetch_acv 0 # ITB acv
+system.cpu.itb.fetch_accesses 2597 # ITB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_acv 0 # DTB read access violations
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_acv 0 # DTB write access violations
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.data_hits 0 # DTB hits
+system.cpu.itb.data_misses 0 # DTB misses
+system.cpu.itb.data_acv 0 # DTB access violations
+system.cpu.itb.data_accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 4 # Number of system calls
+system.cpu.numCycles 52548 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
+system.cpu.num_func_calls 140 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 238 # number of instructions that are conditional controls
+system.cpu.num_int_insts 2375 # number of integer instructions
+system.cpu.num_fp_insts 6 # number of float instructions
+system.cpu.num_int_register_reads 2998 # number of times the integer registers were read
+system.cpu.num_int_register_writes 1768 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 6 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
+system.cpu.num_mem_refs 717 # number of memory refs
+system.cpu.num_load_insts 419 # Number of load instructions
+system.cpu.num_store_insts 298 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 52548 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.ruby.network.routers0.throttle0.link_utilization 5.426467
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 431
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124
+system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 3448
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992
+system.ruby.network.routers0.throttle1.link_utilization 2.145657
+system.ruby.network.routers0.throttle1.msg_count.Control::0 572
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 45
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 62
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 79
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0 4576
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 2952
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 2176
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632
+system.ruby.network.routers1.throttle0.link_utilization 7.342810
+system.ruby.network.routers1.throttle0.msg_count.Control::0 572
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 272
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 45
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 62
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 79
+system.ruby.network.routers1.throttle0.msg_bytes.Control::0 4576
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 39384
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7264
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 2176
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632
+system.ruby.network.routers1.throttle1.link_utilization 7.243853
+system.ruby.network.routers1.throttle1.msg_count.Control::0 547
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::0 431
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 560
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::0 3448
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480
+system.ruby.network.routers2.throttle0.link_utilization 1.817386
+system.ruby.network.routers2.throttle0.msg_count.Control::0 547
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488
+system.ruby.network.routers2.throttle1.link_utilization 5.197153
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312
+system.ruby.network.routers3.throttle0.link_utilization 5.426467
+system.ruby.network.routers3.throttle0.msg_count.Request_Control::0 431
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124
+system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::0 3448
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992
+system.ruby.network.routers3.throttle1.link_utilization 7.342810
+system.ruby.network.routers3.throttle1.msg_count.Control::0 572
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 272
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 45
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 62
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 79
+system.ruby.network.routers3.throttle1.msg_bytes.Control::0 4576
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 39384
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7264
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 2176
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632
+system.ruby.network.routers3.throttle2.link_utilization 1.817386
+system.ruby.network.routers3.throttle2.msg_count.Control::0 547
+system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103
+system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436
+system.ruby.network.routers3.throttle2.msg_bytes.Control::0 4376
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 7416
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 3488
+system.ruby.l1_cntrl0.Load 415 0.00% 0.00%
+system.ruby.l1_cntrl0.Ifetch 2585 0.00% 0.00%
+system.ruby.l1_cntrl0.Store 294 0.00% 0.00%
+system.ruby.l1_cntrl0.Inv 431 0.00% 0.00%
+system.ruby.l1_cntrl0.L1_Replacement 502 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_Exclusive 204 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_all_Acks 368 0.00% 0.00%
+system.ruby.l1_cntrl0.WB_Ack 124 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Load 182 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Ifetch 270 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Store 58 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Inv 162 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Load 22 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Ifetch 30 0.00% 0.00%
+system.ruby.l1_cntrl0.I.Store 10 0.00% 0.00%
+system.ruby.l1_cntrl0.I.L1_Replacement 206 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Ifetch 2285 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Inv 124 0.00% 0.00%
+system.ruby.l1_cntrl0.S.L1_Replacement 172 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Load 140 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Store 41 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Inv 83 0.00% 0.00%
+system.ruby.l1_cntrl0.E.L1_Replacement 79 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Load 71 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Store 185 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Inv 62 0.00% 0.00%
+system.ruby.l1_cntrl0.M.L1_Replacement 45 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_Exclusive 204 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_all_Acks 300 0.00% 0.00%
+system.ruby.l1_cntrl0.IM.Data_all_Acks 68 0.00% 0.00%
+system.ruby.l1_cntrl0.M_I.WB_Ack 124 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GET_INSTR 300 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETS 204 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETX 68 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX 124 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement 43 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement_clean 496 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Data 547 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Ack 539 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data 62 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack_all 369 0.00% 0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock 272 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GET_INSTR 291 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS 192 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX 64 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GET_INSTR 9 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement_clean 286 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETS 12 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETX 4 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement 39 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement_clean 69 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_PUTX 124 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement 4 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement_clean 141 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.Mem_Ack 539 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.WB_Data 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data 60 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.Ack_all 81 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack_all 286 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.Mem_Data 192 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.Mem_Data 291 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.Mem_Data 64 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 272 0.00% 0.00%
+system.ruby.dir_cntrl0.Fetch 547 0.00% 0.00%
+system.ruby.dir_cntrl0.Data 103 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Data 547 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Ack 103 0.00% 0.00%
+system.ruby.dir_cntrl0.CleanReplacement 436 0.00% 0.00%
+system.ruby.dir_cntrl0.I.Fetch 547 0.00% 0.00%
+system.ruby.dir_cntrl0.M.Data 103 0.00% 0.00%
+system.ruby.dir_cntrl0.M.CleanReplacement 436 0.00% 0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data 547 0.00% 0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack 103 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-full_system=false
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem physmem ruby sys_port_proxy voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-init_param=0
-kernel=
-load_addr_mask=1099511627775
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.physmem system.funcmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.cpu0]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
-
-[system.cpu1]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
-
-[system.cpu2]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
-
-[system.cpu3]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
-
-[system.cpu4]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
-
-[system.cpu5]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
-
-[system.cpu6]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
-
-[system.cpu7]
-type=MemTest
-atomic=false
-clk_domain=system.cpu_clk_domain
-issue_dmas=false
-max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
-percent_functional=50
-percent_reads=65
-percent_source_unaligned=50
-percent_uncacheable=0
-progress_interval=10000
-suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
-
-[system.cpu_clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.funcbus]
-type=NoncoherentBus
-clk_domain=system.clk_domain
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-in_addr_map=true
-latency=30
-latency_var=0
-null=true
-range=0:134217727
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network profiler
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-mem_size=268435456
-no_mem_vec=false
-random_seed=1234
-randomization=false
-stats_filename=ruby.stats
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=9
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-memBuffer=system.ruby.dir_cntrl0.memBuffer
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_mem_ctrl_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=5
-size=268435456
-use_map=false
-version=0
-
-[system.ruby.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-clk_domain=system.ruby.memctrl_clk_domain
-dimm_bit_0=12
-dimms_per_channel=2
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-ruby_system=system.ruby
-tFaw=0
-version=0
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=0
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl0.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl0.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.cpu0.test
-
-[system.ruby.l1_cntrl1]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl1.L1Dcache
-L1Icache=system.ruby.l1_cntrl1.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=1
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl1.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl1.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=1
-
-[system.ruby.l1_cntrl1.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl1.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl1.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl1.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl1.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=1
-slave=system.cpu1.test
-
-[system.ruby.l1_cntrl2]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl2.L1Dcache
-L1Icache=system.ruby.l1_cntrl2.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=2
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl2.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl2.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=2
-
-[system.ruby.l1_cntrl2.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl2.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl2.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl2.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl2.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl2.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=2
-slave=system.cpu2.test
-
-[system.ruby.l1_cntrl3]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl3.L1Dcache
-L1Icache=system.ruby.l1_cntrl3.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=3
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl3.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl3.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=3
-
-[system.ruby.l1_cntrl3.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl3.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl3.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl3.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl3.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl3.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=3
-slave=system.cpu3.test
-
-[system.ruby.l1_cntrl4]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl4.L1Dcache
-L1Icache=system.ruby.l1_cntrl4.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=4
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl4.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl4.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=4
-
-[system.ruby.l1_cntrl4.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl4.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl4.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl4.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl4.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl4.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=4
-slave=system.cpu4.test
-
-[system.ruby.l1_cntrl5]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl5.L1Dcache
-L1Icache=system.ruby.l1_cntrl5.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=5
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl5.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl5.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=5
-
-[system.ruby.l1_cntrl5.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl5.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl5.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl5.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl5.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl5.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=5
-slave=system.cpu5.test
-
-[system.ruby.l1_cntrl6]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl6.L1Dcache
-L1Icache=system.ruby.l1_cntrl6.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=6
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl6.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl6.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=6
-
-[system.ruby.l1_cntrl6.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl6.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl6.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl6.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl6.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl6.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=6
-slave=system.cpu6.test
-
-[system.ruby.l1_cntrl7]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl7.L1Dcache
-L1Icache=system.ruby.l1_cntrl7.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=7
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl7.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl7.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=7
-
-[system.ruby.l1_cntrl7.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl7.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl7.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl7.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl7.L1Dcache
-deadlock_threshold=1000000
-icache=system.ruby.l1_cntrl7.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=7
-slave=system.cpu7.test
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=L2cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=8
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_l1_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=15
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 system.ruby.network.ext_links9
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9
-number_of_virtual_networks=10
-routers=system.ruby.network.routers00 system.ruby.network.routers01 system.ruby.network.routers02 system.ruby.network.routers03 system.ruby.network.routers04 system.ruby.network.routers05 system.ruby.network.routers06 system.ruby.network.routers07 system.ruby.network.routers08 system.ruby.network.routers09 system.ruby.network.routers10
-ruby_system=system.ruby
-topology=Crossbar
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers00
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl1
-int_node=system.ruby.network.routers01
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl2
-int_node=system.ruby.network.routers02
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.ext_links3]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl3
-int_node=system.ruby.network.routers03
-latency=1
-link_id=3
-weight=1
-
-[system.ruby.network.ext_links4]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl4
-int_node=system.ruby.network.routers04
-latency=1
-link_id=4
-weight=1
-
-[system.ruby.network.ext_links5]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl5
-int_node=system.ruby.network.routers05
-latency=1
-link_id=5
-weight=1
-
-[system.ruby.network.ext_links6]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl6
-int_node=system.ruby.network.routers06
-latency=1
-link_id=6
-weight=1
-
-[system.ruby.network.ext_links7]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl7
-int_node=system.ruby.network.routers07
-latency=1
-link_id=7
-weight=1
-
-[system.ruby.network.ext_links8]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l2_cntrl0
-int_node=system.ruby.network.routers08
-latency=1
-link_id=8
-weight=1
-
-[system.ruby.network.ext_links9]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers09
-latency=1
-link_id=9
-weight=1
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=10
-node_a=system.ruby.network.routers00
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=11
-node_a=system.ruby.network.routers01
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=12
-node_a=system.ruby.network.routers02
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links3]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=13
-node_a=system.ruby.network.routers03
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links4]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=14
-node_a=system.ruby.network.routers04
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links5]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=15
-node_a=system.ruby.network.routers05
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links6]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=16
-node_a=system.ruby.network.routers06
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links7]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=17
-node_a=system.ruby.network.routers07
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links8]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=18
-node_a=system.ruby.network.routers08
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.int_links9]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=19
-node_a=system.ruby.network.routers09
-node_b=system.ruby.network.routers10
-weight=1
-
-[system.ruby.network.routers00]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=0
-virt_nets=10
-
-[system.ruby.network.routers01]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=1
-virt_nets=10
-
-[system.ruby.network.routers02]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=2
-virt_nets=10
-
-[system.ruby.network.routers03]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=3
-virt_nets=10
-
-[system.ruby.network.routers04]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=4
-virt_nets=10
-
-[system.ruby.network.routers05]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=5
-virt_nets=10
-
-[system.ruby.network.routers06]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=6
-virt_nets=10
-
-[system.ruby.network.routers07]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=7
-virt_nets=10
-
-[system.ruby.network.routers08]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=8
-virt_nets=10
-
-[system.ruby.network.routers09]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=9
-virt_nets=10
-
-[system.ruby.network.routers10]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=10
-virt_nets=10
-
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=8
-ruby_system=system.ruby
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-access_phys_mem=true
-clk_domain=system.clk_domain
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.voltage_domain]
-type=VoltageDomain
-voltage=1.000000
-
+++ /dev/null
-Real time: Sep/22/2013 05:28:42
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 79
-Elapsed_time_in_minutes: 1.31667
-Elapsed_time_in_hours: 0.0219444
-Elapsed_time_in_days: 0.000914352
-
-Virtual_time_in_seconds: 79.09
-Virtual_time_in_minutes: 1.31817
-Virtual_time_in_hours: 0.0219694
-Virtual_time_in_days: 0.000915394
-
-Ruby_current_time: 7257449
-Ruby_start_time: 0
-Ruby_cycles: 7257449
-
-mbytes_resident: 69.1055
-mbytes_total: 251.578
-resident_ratio: 0.275713
-
-Busy Controller Counts:
-L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
-
-L2Cache-0:3
-Directory-0:0
-
-
-Busy Bank Count:0
-
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 610515 average: 15.9984 | standard deviation: 0.12747 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 610394 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-latency: [binsize: 256 max: 4383 count: 610387 average: 1521.7 | standard deviation: 904.039 | 40769 67074 57492 52511 48992 47365 47915 49117 51274 50977 44598 30540 15468 5041 1079 165 9 1 ]
-latency: LD: [binsize: 256 max: 4383 count: 396832 average: 1523.22 | standard deviation: 904.029 | 26404 43574 37232 34002 32011 30828 31124 31930 33469 33023 29077 19942 10106 3291 700 111 7 1 ]
-latency: ST: [binsize: 256 max: 4219 count: 213555 average: 1518.88 | standard deviation: 904.051 | 14365 23500 20260 18509 16981 16537 16791 17187 17805 17954 15521 10598 5362 1750 379 54 2 ]
-hit latency: [binsize: 1 max: 3 count: 11 average: 3 | standard deviation: 0 | 0 0 0 11 ]
-hit latency: LD: [binsize: 1 max: 3 count: 8 average: 3 | standard deviation: 0 | 0 0 0 8 ]
-hit latency: ST: [binsize: 1 max: 3 count: 3 average: 3 | standard deviation: 0 | 0 0 0 3 ]
-miss latency: [binsize: 256 max: 4383 count: 610376 average: 1521.73 | standard deviation: 904.024 | 40758 67074 57492 52511 48992 47365 47915 49117 51274 50977 44598 30540 15468 5041 1079 165 9 1 ]
-miss latency: LD: [binsize: 256 max: 4383 count: 396824 average: 1523.25 | standard deviation: 904.013 | 26396 43574 37232 34002 32011 30828 31124 31930 33469 33023 29077 19942 10106 3291 700 111 7 1 ]
-miss latency: ST: [binsize: 256 max: 4219 count: 213552 average: 1518.9 | standard deviation: 904.04 | 14362 23500 20260 18509 16981 16537 16791 17187 17805 17954 15521 10598 5362 1750 379 54 2 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 32 max: 952 count: 4856797 average: 43.4082 | standard deviation: 104.144 | 4025692 47689 64638 48612 56875 68710 62101 82292 81634 76798 75935 59926 43791 30096 16740 8442 4032 1777 627 240 88 19 15 14 2 5 2 1 2 2 ]
- virtual_network_0_delay_cycles: [binsize: 32 max: 952 count: 1535534 average: 133.924 | standard deviation: 149.364 | 704440 47678 64638 48612 56875 68710 62101 82292 81634 76798 75935 59926 43791 30096 16740 8442 4032 1777 627 240 88 19 15 14 2 5 2 1 2 2 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 25 count: 2729880 average: 1.39963 | standard deviation: 2.33339 | 1665086 261419 142358 182063 191213 107497 51010 39587 36260 24170 11876 5896 4335 3537 1939 669 358 307 184 52 28 21 11 2 1 1 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 36 count: 591383 average: 2.29961 | standard deviation: 3.36899 | 265676 88575 43296 28113 50459 44852 14076 8341 11694 10048 7138 3986 1859 2745 3765 1841 1033 709 762 751 478 229 183 320 183 91 54 43 40 21 9 2 6 3 0 0 2 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+++ /dev/null
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-system.cpu3: completed 10000 read, 5414 write accesses @719275
-system.cpu1: completed 10000 read, 5207 write accesses @725827
-system.cpu2: completed 10000 read, 5346 write accesses @726254
-system.cpu6: completed 10000 read, 5345 write accesses @729597
-system.cpu7: completed 10000 read, 5419 write accesses @731574
-system.cpu4: completed 10000 read, 5529 write accesses @736931
-system.cpu5: completed 10000 read, 5440 write accesses @744470
-system.cpu0: completed 10000 read, 5379 write accesses @746243
-system.cpu3: completed 20000 read, 10692 write accesses @1453209
-system.cpu1: completed 20000 read, 10572 write accesses @1457166
-system.cpu2: completed 20000 read, 10817 write accesses @1460941
-system.cpu7: completed 20000 read, 11051 write accesses @1471674
-system.cpu4: completed 20000 read, 10890 write accesses @1471936
-system.cpu5: completed 20000 read, 10727 write accesses @1478654
-system.cpu6: completed 20000 read, 10906 write accesses @1482356
-system.cpu0: completed 20000 read, 10698 write accesses @1484885
-system.cpu2: completed 30000 read, 16174 write accesses @2184715
-system.cpu6: completed 30000 read, 16276 write accesses @2193615
-system.cpu0: completed 30000 read, 16014 write accesses @2197245
-system.cpu7: completed 30000 read, 16583 write accesses @2199803
-system.cpu1: completed 30000 read, 16153 write accesses @2202627
-system.cpu4: completed 30000 read, 16326 write accesses @2206424
-system.cpu3: completed 30000 read, 16120 write accesses @2214933
-system.cpu5: completed 30000 read, 16017 write accesses @2228709
-system.cpu6: completed 40000 read, 21587 write accesses @2901116
-system.cpu2: completed 40000 read, 21416 write accesses @2916609
-system.cpu0: completed 40000 read, 21318 write accesses @2930718
-system.cpu1: completed 40000 read, 21576 write accesses @2933338
-system.cpu7: completed 40000 read, 22016 write accesses @2933661
-system.cpu4: completed 40000 read, 21632 write accesses @2934839
-system.cpu3: completed 40000 read, 21495 write accesses @2950362
-system.cpu5: completed 40000 read, 21476 write accesses @2978482
-system.cpu6: completed 50000 read, 26852 write accesses @3637893
-system.cpu2: completed 50000 read, 26885 write accesses @3654740
-system.cpu1: completed 50000 read, 27034 write accesses @3657767
-system.cpu0: completed 50000 read, 26670 write accesses @3659997
-system.cpu4: completed 50000 read, 26987 write accesses @3671541
-system.cpu7: completed 50000 read, 27458 write accesses @3674943
-system.cpu3: completed 50000 read, 26989 write accesses @3692057
-system.cpu5: completed 50000 read, 26964 write accesses @3706034
-system.cpu6: completed 60000 read, 32004 write accesses @4355566
-system.cpu0: completed 60000 read, 32011 write accesses @4386276
-system.cpu4: completed 60000 read, 32458 write accesses @4393617
-system.cpu1: completed 60000 read, 32363 write accesses @4400443
-system.cpu2: completed 60000 read, 32317 write accesses @4403435
-system.cpu7: completed 60000 read, 32808 write accesses @4408380
-system.cpu3: completed 60000 read, 32368 write accesses @4439846
-system.cpu5: completed 60000 read, 32369 write accesses @4442699
-system.cpu6: completed 70000 read, 37273 write accesses @5071946
-system.cpu0: completed 70000 read, 37486 write accesses @5119164
-system.cpu4: completed 70000 read, 37898 write accesses @5125200
-system.cpu7: completed 70000 read, 38069 write accesses @5133382
-system.cpu1: completed 70000 read, 37837 write accesses @5136537
-system.cpu2: completed 70000 read, 37818 write accesses @5139253
-system.cpu5: completed 70000 read, 37708 write accesses @5173290
-system.cpu3: completed 70000 read, 37836 write accesses @5178083
-system.cpu6: completed 80000 read, 42670 write accesses @5803436
-system.cpu7: completed 80000 read, 43237 write accesses @5856290
-system.cpu4: completed 80000 read, 43274 write accesses @5860905
-system.cpu2: completed 80000 read, 43098 write accesses @5864154
-system.cpu0: completed 80000 read, 43136 write accesses @5865993
-system.cpu1: completed 80000 read, 43319 write accesses @5873155
-system.cpu5: completed 80000 read, 43110 write accesses @5912619
-system.cpu3: completed 80000 read, 43527 write accesses @5915226
-system.cpu6: completed 90000 read, 47938 write accesses @6517300
-system.cpu7: completed 90000 read, 48616 write accesses @6584472
-system.cpu2: completed 90000 read, 48495 write accesses @6590070
-system.cpu0: completed 90000 read, 48585 write accesses @6598491
-system.cpu1: completed 90000 read, 48584 write accesses @6599764
-system.cpu4: completed 90000 read, 48685 write accesses @6602186
-system.cpu5: completed 90000 read, 48384 write accesses @6637212
-system.cpu3: completed 90000 read, 48869 write accesses @6654178
-system.cpu6: completed 100000 read, 53414 write accesses @7257449
-hack: be nice to actually delete the event here
+++ /dev/null
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:23
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 7257449 because maximum number of loads reached
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.007257 # Number of seconds simulated
-sim_ticks 7257449 # Number of ticks simulated
-final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 91873 # Simulator tick rate (ticks/s)
-host_mem_usage 257620 # Number of bytes of host memory used
-host_seconds 78.99 # Real time elapsed on the host
-system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Dcache.demand_misses 76641 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76643 # Number of cache demand accesses
-system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl4.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl4.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl4.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl4.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl4.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl4.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl5.L1Dcache.demand_hits 2 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Dcache.demand_misses 75966 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Dcache.demand_accesses 75968 # Number of cache demand accesses
-system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl5.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl5.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl5.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl5.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl5.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl5.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl6.L1Dcache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Dcache.demand_misses 76675 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Dcache.demand_accesses 76675 # Number of cache demand accesses
-system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl6.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl6.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl6.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl6.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl6.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl6.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl7.L1Dcache.demand_hits 2 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Dcache.demand_misses 76386 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Dcache.demand_accesses 76388 # Number of cache demand accesses
-system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl7.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl7.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl7.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl7.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl7.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl7.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 3 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 76561 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 76564 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl1.L1Dcache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Dcache.demand_misses 76056 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Dcache.demand_accesses 76056 # Number of cache demand accesses
-system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Dcache.demand_misses 76165 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Dcache.demand_accesses 76166 # Number of cache demand accesses
-system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl2.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl2.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl2.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl2.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl2.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl2.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Dcache.demand_misses 75953 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Dcache.demand_accesses 75954 # Number of cache demand accesses
-system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
-system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
-system.ruby.l1_cntrl3.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl3.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl3.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl3.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl3.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl3.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l2_cntrl0.L2cache.demand_hits 33 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 610348 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 610381 # Number of cache demand accesses
-system.ruby.network.routers00.percent_links_utilized 5.463118
-system.ruby.network.routers00.msg_count.Control::0 76561
-system.ruby.network.routers00.msg_count.Request_Control::0 74092
-system.ruby.network.routers00.msg_count.Response_Data::1 77073
-system.ruby.network.routers00.msg_count.Response_Control::1 63910
-system.ruby.network.routers00.msg_count.Response_Control::2 75920
-system.ruby.network.routers00.msg_count.Writeback_Data::0 14031
-system.ruby.network.routers00.msg_count.Writeback_Data::1 49937
-system.ruby.network.routers00.msg_count.Writeback_Control::0 26080
-system.ruby.network.routers00.msg_bytes.Control::0 612488
-system.ruby.network.routers00.msg_bytes.Request_Control::0 592736
-system.ruby.network.routers00.msg_bytes.Response_Data::1 5549256
-system.ruby.network.routers00.msg_bytes.Response_Control::1 511280
-system.ruby.network.routers00.msg_bytes.Response_Control::2 607360
-system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1010232
-system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3595464
-system.ruby.network.routers00.msg_bytes.Writeback_Control::0 208640
-system.ruby.network.routers01.percent_links_utilized 5.425770
-system.ruby.network.routers01.msg_count.Control::0 76056
-system.ruby.network.routers01.msg_count.Request_Control::0 73721
-system.ruby.network.routers01.msg_count.Response_Data::1 76574
-system.ruby.network.routers01.msg_count.Response_Control::1 63612
-system.ruby.network.routers01.msg_count.Response_Control::2 75434
-system.ruby.network.routers01.msg_count.Writeback_Data::0 14149
-system.ruby.network.routers01.msg_count.Writeback_Data::1 49365
-system.ruby.network.routers01.msg_count.Writeback_Control::0 25475
-system.ruby.network.routers01.msg_bytes.Control::0 608448
-system.ruby.network.routers01.msg_bytes.Request_Control::0 589768
-system.ruby.network.routers01.msg_bytes.Response_Data::1 5513328
-system.ruby.network.routers01.msg_bytes.Response_Control::1 508896
-system.ruby.network.routers01.msg_bytes.Response_Control::2 603472
-system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1018728
-system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3554280
-system.ruby.network.routers01.msg_bytes.Writeback_Control::0 203800
-system.ruby.network.routers02.percent_links_utilized 5.442570
-system.ruby.network.routers02.msg_count.Control::0 76165
-system.ruby.network.routers02.msg_count.Request_Control::0 73785
-system.ruby.network.routers02.msg_count.Response_Data::1 76666
-system.ruby.network.routers02.msg_count.Response_Control::1 63651
-system.ruby.network.routers02.msg_count.Response_Control::2 75573
-system.ruby.network.routers02.msg_count.Writeback_Data::0 14049
-system.ruby.network.routers02.msg_count.Writeback_Data::1 49819
-system.ruby.network.routers02.msg_count.Writeback_Control::0 25987
-system.ruby.network.routers02.msg_bytes.Control::0 609320
-system.ruby.network.routers02.msg_bytes.Request_Control::0 590280
-system.ruby.network.routers02.msg_bytes.Response_Data::1 5519952
-system.ruby.network.routers02.msg_bytes.Response_Control::1 509208
-system.ruby.network.routers02.msg_bytes.Response_Control::2 604584
-system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1011528
-system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3586968
-system.ruby.network.routers02.msg_bytes.Writeback_Control::0 207896
-system.ruby.network.routers03.percent_links_utilized 5.419659
-system.ruby.network.routers03.msg_count.Control::0 75953
-system.ruby.network.routers03.msg_count.Request_Control::0 73621
-system.ruby.network.routers03.msg_count.Response_Data::1 76459
-system.ruby.network.routers03.msg_count.Response_Control::1 63457
-system.ruby.network.routers03.msg_count.Response_Control::2 75316
-system.ruby.network.routers03.msg_count.Writeback_Data::0 13992
-system.ruby.network.routers03.msg_count.Writeback_Data::1 49471
-system.ruby.network.routers03.msg_count.Writeback_Control::0 25671
-system.ruby.network.routers03.msg_bytes.Control::0 607624
-system.ruby.network.routers03.msg_bytes.Request_Control::0 588968
-system.ruby.network.routers03.msg_bytes.Response_Data::1 5505048
-system.ruby.network.routers03.msg_bytes.Response_Control::1 507656
-system.ruby.network.routers03.msg_bytes.Response_Control::2 602528
-system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1007424
-system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3561912
-system.ruby.network.routers03.msg_bytes.Writeback_Control::0 205368
-system.ruby.network.routers04.percent_links_utilized 5.477861
-system.ruby.network.routers04.msg_count.Control::0 76641
-system.ruby.network.routers04.msg_count.Request_Control::0 74200
-system.ruby.network.routers04.msg_count.Response_Data::1 77150
-system.ruby.network.routers04.msg_count.Response_Control::1 63977
-system.ruby.network.routers04.msg_count.Response_Control::2 75951
-system.ruby.network.routers04.msg_count.Writeback_Data::0 14152
-system.ruby.network.routers04.msg_count.Writeback_Data::1 50174
-system.ruby.network.routers04.msg_count.Writeback_Control::0 26159
-system.ruby.network.routers04.msg_bytes.Control::0 613128
-system.ruby.network.routers04.msg_bytes.Request_Control::0 593600
-system.ruby.network.routers04.msg_bytes.Response_Data::1 5554800
-system.ruby.network.routers04.msg_bytes.Response_Control::1 511816
-system.ruby.network.routers04.msg_bytes.Response_Control::2 607608
-system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1018944
-system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3612528
-system.ruby.network.routers04.msg_bytes.Writeback_Control::0 209272
-system.ruby.network.routers05.percent_links_utilized 5.420954
-system.ruby.network.routers05.msg_count.Control::0 75966
-system.ruby.network.routers05.msg_count.Request_Control::0 73736
-system.ruby.network.routers05.msg_count.Response_Data::1 76425
-system.ruby.network.routers05.msg_count.Response_Control::1 63440
-system.ruby.network.routers05.msg_count.Response_Control::2 75352
-system.ruby.network.routers05.msg_count.Writeback_Data::0 14005
-system.ruby.network.routers05.msg_count.Writeback_Data::1 49530
-system.ruby.network.routers05.msg_count.Writeback_Control::0 25558
-system.ruby.network.routers05.msg_bytes.Control::0 607728
-system.ruby.network.routers05.msg_bytes.Request_Control::0 589888
-system.ruby.network.routers05.msg_bytes.Response_Data::1 5502600
-system.ruby.network.routers05.msg_bytes.Response_Control::1 507520
-system.ruby.network.routers05.msg_bytes.Response_Control::2 602816
-system.ruby.network.routers05.msg_bytes.Writeback_Data::0 1008360
-system.ruby.network.routers05.msg_bytes.Writeback_Data::1 3566160
-system.ruby.network.routers05.msg_bytes.Writeback_Control::0 204464
-system.ruby.network.routers06.percent_links_utilized 5.479511
-system.ruby.network.routers06.msg_count.Control::0 76673
-system.ruby.network.routers06.msg_count.Request_Control::0 74320
-system.ruby.network.routers06.msg_count.Response_Data::1 77150
-system.ruby.network.routers06.msg_count.Response_Control::1 64316
-system.ruby.network.routers06.msg_count.Response_Control::2 76042
-system.ruby.network.routers06.msg_count.Writeback_Data::0 14224
-system.ruby.network.routers06.msg_count.Writeback_Data::1 50086
-system.ruby.network.routers06.msg_count.Writeback_Control::0 26201
-system.ruby.network.routers06.msg_bytes.Control::0 613384
-system.ruby.network.routers06.msg_bytes.Request_Control::0 594560
-system.ruby.network.routers06.msg_bytes.Response_Data::1 5554800
-system.ruby.network.routers06.msg_bytes.Response_Control::1 514528
-system.ruby.network.routers06.msg_bytes.Response_Control::2 608336
-system.ruby.network.routers06.msg_bytes.Writeback_Data::0 1024128
-system.ruby.network.routers06.msg_bytes.Writeback_Data::1 3606192
-system.ruby.network.routers06.msg_bytes.Writeback_Control::0 209608
-system.ruby.network.routers07.percent_links_utilized 5.453059
-system.ruby.network.routers07.msg_count.Control::0 76386
-system.ruby.network.routers07.msg_count.Request_Control::0 73908
-system.ruby.network.routers07.msg_count.Response_Data::1 76884
-system.ruby.network.routers07.msg_count.Response_Control::1 63903
-system.ruby.network.routers07.msg_count.Response_Control::2 75759
-system.ruby.network.routers07.msg_count.Writeback_Data::0 14181
-system.ruby.network.routers07.msg_count.Writeback_Data::1 49730
-system.ruby.network.routers07.msg_count.Writeback_Control::0 25901
-system.ruby.network.routers07.msg_bytes.Control::0 611088
-system.ruby.network.routers07.msg_bytes.Request_Control::0 591264
-system.ruby.network.routers07.msg_bytes.Response_Data::1 5535648
-system.ruby.network.routers07.msg_bytes.Response_Control::1 511224
-system.ruby.network.routers07.msg_bytes.Response_Control::2 606072
-system.ruby.network.routers07.msg_bytes.Writeback_Data::0 1021032
-system.ruby.network.routers07.msg_bytes.Writeback_Data::1 3580560
-system.ruby.network.routers07.msg_bytes.Writeback_Control::0 207208
-system.ruby.network.routers08.percent_links_utilized 74.192933
-system.ruby.network.routers08.msg_count.Control::0 1215392
-system.ruby.network.routers08.msg_count.Request_Control::0 587692
-system.ruby.network.routers08.msg_count.Response_Data::1 1424147
-system.ruby.network.routers08.msg_count.Response_Control::1 1507241
-system.ruby.network.routers08.msg_count.Response_Control::2 605346
-system.ruby.network.routers08.msg_count.Writeback_Data::0 112782
-system.ruby.network.routers08.msg_count.Writeback_Data::1 398112
-system.ruby.network.routers08.msg_count.Writeback_Control::0 207030
-system.ruby.network.routers08.msg_bytes.Control::0 9723136
-system.ruby.network.routers08.msg_bytes.Request_Control::0 4701536
-system.ruby.network.routers08.msg_bytes.Response_Data::1 102538584
-system.ruby.network.routers08.msg_bytes.Response_Control::1 12057928
-system.ruby.network.routers08.msg_bytes.Response_Control::2 4842768
-system.ruby.network.routers08.msg_bytes.Writeback_Data::0 8120304
-system.ruby.network.routers08.msg_bytes.Writeback_Data::1 28664064
-system.ruby.network.routers08.msg_bytes.Writeback_Control::0 1656240
-system.ruby.dir_cntrl0.memBuffer.memReq 817953 # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead 604997 # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite 212953 # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh 50399 # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles 5089443 # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ 172403 # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ 411771 # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls 5673617 # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq 6.936361 # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy 991356 # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy 1587349 # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 927948 # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 413483 # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait 976938 # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memNotOld 192369 # memory stalls due to anti starvation
-system.ruby.dir_cntrl0.memBuffer.memBankCount | 25693 3.14% 3.14% | 25309 3.09% 6.24% | 25639 3.13% 9.37% | 25493 3.12% 12.49% | 25446 3.11% 15.60% | 25240 3.09% 18.68% | 25202 3.08% 21.76% | 25657 3.14% 24.90% | 25510 3.12% 28.02% | 25612 3.13% 31.15% | 25713 3.14% 34.29% | 25863 3.16% 37.46% | 25420 3.11% 40.56% | 25756 3.15% 43.71% | 25574 3.13% 46.84% | 25666 3.14% 49.98% | 25584 3.13% 53.11% | 25558 3.12% 56.23% | 25869 3.16% 59.39% | 25665 3.14% 62.53% | 25398 3.11% 65.64% | 25614 3.13% 68.77% | 25401 3.11% 71.87% | 25740 3.15% 75.02% | 25400 3.11% 78.12% | 25542 3.12% 81.25% | 25601 3.13% 84.38% | 25502 3.12% 87.49% | 25584 3.13% 90.62% | 25779 3.15% 93.77% | 25408 3.11% 96.88% | 25515 3.12% 100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total 817953 # Number of accesses per bank
-
-system.ruby.network.routers09.percent_links_utilized 30.877103
-system.ruby.network.routers09.msg_count.Control::0 604998
-system.ruby.network.routers09.msg_count.Response_Data::1 817950
-system.ruby.network.routers09.msg_count.Response_Control::1 997019
-system.ruby.network.routers09.msg_bytes.Control::0 4839984
-system.ruby.network.routers09.msg_bytes.Response_Data::1 58892400
-system.ruby.network.routers09.msg_bytes.Response_Control::1 7976152
-system.ruby.network.routers10.percent_links_utilized 14.874317
-system.ruby.network.routers10.msg_count.Control::0 1215392
-system.ruby.network.routers10.msg_count.Request_Control::0 591383
-system.ruby.network.routers10.msg_count.Response_Data::1 1429496
-system.ruby.network.routers10.msg_count.Response_Control::1 1507263
-system.ruby.network.routers10.msg_count.Response_Control::2 605346
-system.ruby.network.routers10.msg_count.Writeback_Data::0 112782
-system.ruby.network.routers10.msg_count.Writeback_Data::1 398112
-system.ruby.network.routers10.msg_count.Writeback_Control::0 207030
-system.ruby.network.routers10.msg_bytes.Control::0 9723136
-system.ruby.network.routers10.msg_bytes.Request_Control::0 4731064
-system.ruby.network.routers10.msg_bytes.Response_Data::1 102923712
-system.ruby.network.routers10.msg_bytes.Response_Control::1 12058104
-system.ruby.network.routers10.msg_bytes.Response_Control::2 4842768
-system.ruby.network.routers10.msg_bytes.Writeback_Data::0 8120304
-system.ruby.network.routers10.msg_bytes.Writeback_Data::1 28664064
-system.ruby.network.routers10.msg_bytes.Writeback_Control::0 1656240
-system.ruby.network.msg_count.Control 3646183
-system.ruby.network.msg_count.Request_Control 1770458
-system.ruby.network.msg_count.Response_Data 4285974
-system.ruby.network.msg_count.Response_Control 6337828
-system.ruby.network.msg_count.Writeback_Data 1532683
-system.ruby.network.msg_count.Writeback_Control 621092
-system.ruby.network.msg_byte.Control 29169464
-system.ruby.network.msg_byte.Request_Control 14163664
-system.ruby.network.msg_byte.Response_Data 308590128
-system.ruby.network.msg_byte.Response_Control 50702624
-system.ruby.network.msg_byte.Writeback_Data 110353176
-system.ruby.network.msg_byte.Writeback_Control 4968736
-system.funcbus.throughput 0 # Throughput (bytes/s)
-system.funcbus.data_through_bus 0 # Total data (bytes)
-system.cpu0.num_reads 99060 # number of read accesses completed
-system.cpu0.num_writes 53442 # number of write accesses completed
-system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu1.num_reads 99097 # number of read accesses completed
-system.cpu1.num_writes 53480 # number of write accesses completed
-system.cpu1.num_copies 0 # number of copy accesses completed
-system.cpu2.num_reads 99034 # number of read accesses completed
-system.cpu2.num_writes 53431 # number of write accesses completed
-system.cpu2.num_copies 0 # number of copy accesses completed
-system.cpu3.num_reads 98135 # number of read accesses completed
-system.cpu3.num_writes 53229 # number of write accesses completed
-system.cpu3.num_copies 0 # number of copy accesses completed
-system.cpu4.num_reads 98915 # number of read accesses completed
-system.cpu4.num_writes 53496 # number of write accesses completed
-system.cpu4.num_copies 0 # number of copy accesses completed
-system.cpu5.num_reads 98351 # number of read accesses completed
-system.cpu5.num_writes 52957 # number of write accesses completed
-system.cpu5.num_copies 0 # number of copy accesses completed
-system.cpu6.num_reads 100000 # number of read accesses completed
-system.cpu6.num_writes 53414 # number of write accesses completed
-system.cpu6.num_copies 0 # number of copy accesses completed
-system.cpu7.num_reads 99052 # number of read accesses completed
-system.cpu7.num_writes 53517 # number of write accesses completed
-system.cpu7.num_copies 0 # number of copy accesses completed
-system.ruby.network.routers00.throttle0.link_utilization 5.533742
-system.ruby.network.routers00.throttle0.msg_count.Request_Control::0 74092
-system.ruby.network.routers00.throttle0.msg_count.Response_Data::1 76557
-system.ruby.network.routers00.throttle0.msg_count.Response_Control::1 40112
-system.ruby.network.routers00.throttle0.msg_bytes.Request_Control::0 592736
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Data::1 5512104
-system.ruby.network.routers00.throttle0.msg_bytes.Response_Control::1 320896
-system.ruby.network.routers00.throttle1.link_utilization 5.392494
-system.ruby.network.routers00.throttle1.msg_count.Control::0 76561
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-system.ruby.network.routers10.throttle9.msg_bytes.Control::0 4839984
-system.ruby.network.routers10.throttle9.msg_bytes.Response_Data::1 15332760
-system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3136272
-system.ruby.l1_cntrl0.Load | 49778 12.54% 12.54% | 49377 12.44% 24.99% | 49516 12.48% 37.46% | 49381 12.44% 49.91% | 49747 12.54% 62.44% | 49368 12.44% 74.88% | 50044 12.61% 87.49% | 49642 12.51% 100.00%
-system.ruby.l1_cntrl0.Load::total 396853
-
-system.ruby.l1_cntrl0.Store | 26786 12.54% 12.54% | 26679 12.49% 25.03% | 26651 12.48% 37.51% | 26574 12.44% 49.96% | 26897 12.59% 62.55% | 26600 12.46% 75.01% | 26631 12.47% 87.48% | 26746 12.52% 100.00%
-system.ruby.l1_cntrl0.Store::total 213564
-
-system.ruby.l1_cntrl0.Inv | 73735 12.53% 12.53% | 73350 12.46% 24.99% | 73434 12.48% 37.47% | 73266 12.45% 49.92% | 73836 12.55% 62.46% | 73403 12.47% 74.93% | 73975 12.57% 87.50% | 73550 12.50% 100.00%
-system.ruby.l1_cntrl0.Inv::total 588549
-
-system.ruby.l1_cntrl0.L1_Replacement | 533617 12.54% 12.54% | 530929 12.48% 25.02% | 531837 12.50% 37.52% | 527767 12.41% 49.93% | 533499 12.54% 62.47% | 530493 12.47% 74.94% | 533236 12.53% 87.48% | 532831 12.52% 100.00%
-system.ruby.l1_cntrl0.L1_Replacement::total 4254209
-
-system.ruby.l1_cntrl0.Fwd_GETX | 198 11.91% 11.91% | 220 13.23% 25.14% | 198 11.91% 37.04% | 200 12.03% 49.07% | 215 12.93% 62.00% | 204 12.27% 74.26% | 212 12.75% 87.01% | 216 12.99% 100.00%
-system.ruby.l1_cntrl0.Fwd_GETX::total 1663
-
-system.ruby.l1_cntrl0.Fwd_GETS | 159 13.58% 13.58% | 151 12.89% 26.47% | 153 13.07% 39.54% | 155 13.24% 52.78% | 149 12.72% 65.50% | 129 11.02% 76.52% | 133 11.36% 87.87% | 142 12.13% 100.00%
-system.ruby.l1_cntrl0.Fwd_GETS::total 1171
-
-system.ruby.l1_cntrl0.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
-system.ruby.l1_cntrl0.Data::total 11
-
-system.ruby.l1_cntrl0.Data_Exclusive | 48989 12.54% 12.54% | 48607 12.44% 24.98% | 48775 12.49% 37.47% | 48593 12.44% 49.91% | 48923 12.52% 62.44% | 48630 12.45% 74.88% | 49230 12.60% 87.49% | 48877 12.51% 100.00%
-system.ruby.l1_cntrl0.Data_Exclusive::total 390624
-
-system.ruby.l1_cntrl0.DataS_fromL1 | 147 12.55% 12.55% | 148 12.64% 25.19% | 149 12.72% 37.92% | 152 12.98% 50.90% | 133 11.36% 62.25% | 124 10.59% 72.84% | 182 15.54% 88.39% | 136 11.61% 100.00%
-system.ruby.l1_cntrl0.DataS_fromL1::total 1171
-
-system.ruby.l1_cntrl0.Data_all_Acks | 27420 12.55% 12.55% | 27295 12.49% 25.03% | 27237 12.46% 37.49% | 27204 12.45% 49.94% | 27578 12.62% 62.56% | 27207 12.45% 75.01% | 27259 12.47% 87.48% | 27370 12.52% 100.00%
-system.ruby.l1_cntrl0.Data_all_Acks::total 218570
-
-system.ruby.l1_cntrl0.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
-system.ruby.l1_cntrl0.Ack::total 11
-
-system.ruby.l1_cntrl0.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
-system.ruby.l1_cntrl0.Ack_all::total 11
-
-system.ruby.l1_cntrl0.WB_Ack | 40110 12.54% 12.54% | 39623 12.39% 24.93% | 40034 12.52% 37.45% | 39662 12.40% 49.85% | 40309 12.60% 62.46% | 39563 12.37% 74.83% | 40425 12.64% 87.47% | 40081 12.53% 100.00%
-system.ruby.l1_cntrl0.WB_Ack::total 319807
-
-system.ruby.l1_cntrl0.NP.Load | 49768 12.54% 12.54% | 49368 12.44% 24.99% | 49506 12.48% 37.46% | 49370 12.44% 49.90% | 49736 12.53% 62.44% | 49359 12.44% 74.88% | 50040 12.61% 87.49% | 49632 12.51% 100.00%
-system.ruby.l1_cntrl0.NP.Load::total 396779
-
-system.ruby.l1_cntrl0.NP.Store | 26783 12.54% 12.54% | 26673 12.49% 25.04% | 26639 12.48% 37.51% | 26570 12.44% 49.96% | 26890 12.59% 62.55% | 26593 12.45% 75.00% | 26629 12.47% 87.47% | 26744 12.53% 100.00%
-system.ruby.l1_cntrl0.NP.Store::total 213521
-
-system.ruby.l1_cntrl0.NP.Inv | 436 13.54% 13.54% | 404 12.55% 26.09% | 386 11.99% 38.07% | 385 11.96% 50.03% | 420 13.04% 63.07% | 399 12.39% 75.47% | 405 12.58% 88.04% | 385 11.96% 100.00%
-system.ruby.l1_cntrl0.NP.Inv::total 3220
-
-system.ruby.l1_cntrl0.I.Load | 8 12.50% 12.50% | 9 14.06% 26.56% | 9 14.06% 40.62% | 9 14.06% 54.69% | 9 14.06% 68.75% | 8 12.50% 81.25% | 4 6.25% 87.50% | 8 12.50% 100.00%
-system.ruby.l1_cntrl0.I.Load::total 64
-
-system.ruby.l1_cntrl0.I.Store | 2 5.13% 5.13% | 6 15.38% 20.51% | 11 28.21% 48.72% | 4 10.26% 58.97% | 6 15.38% 74.36% | 6 15.38% 89.74% | 2 5.13% 94.87% | 2 5.13% 100.00%
-system.ruby.l1_cntrl0.I.Store::total 39
-
-system.ruby.l1_cntrl0.I.L1_Replacement | 36061 12.53% 12.53% | 36066 12.54% 25.07% | 35776 12.44% 37.51% | 35948 12.50% 50.00% | 35950 12.50% 62.50% | 36049 12.53% 75.03% | 35879 12.47% 87.50% | 35962 12.50% 100.00%
-system.ruby.l1_cntrl0.I.L1_Replacement::total 287691
-
-system.ruby.l1_cntrl0.S.Inv | 475 12.01% 12.01% | 488 12.34% 24.34% | 482 12.18% 36.53% | 528 13.35% 49.87% | 526 13.30% 63.17% | 446 11.27% 74.44% | 511 12.92% 87.36% | 500 12.64% 100.00%
-system.ruby.l1_cntrl0.S.Inv::total 3956
-
-system.ruby.l1_cntrl0.S.L1_Replacement | 375 13.58% 13.58% | 347 12.57% 26.15% | 329 11.92% 38.07% | 325 11.77% 49.84% | 361 13.07% 62.91% | 336 12.17% 75.08% | 360 13.04% 88.12% | 328 11.88% 100.00%
-system.ruby.l1_cntrl0.S.L1_Replacement::total 2761
-
-system.ruby.l1_cntrl0.E.Load | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00%
-system.ruby.l1_cntrl0.E.Load::total 5
-
-system.ruby.l1_cntrl0.E.Inv | 22855 12.48% 12.48% | 23068 12.60% 25.09% | 22724 12.41% 37.50% | 22855 12.48% 49.98% | 22694 12.40% 62.38% | 23009 12.57% 74.95% | 22944 12.53% 87.48% | 22917 12.52% 100.00%
-system.ruby.l1_cntrl0.E.Inv::total 183066
-
-system.ruby.l1_cntrl0.E.L1_Replacement | 26080 12.60% 12.60% | 25475 12.30% 24.90% | 25987 12.55% 37.45% | 25671 12.40% 49.85% | 26159 12.64% 62.49% | 25558 12.34% 74.83% | 26202 12.66% 87.49% | 25901 12.51% 100.00%
-system.ruby.l1_cntrl0.E.L1_Replacement::total 207033
-
-system.ruby.l1_cntrl0.E.Fwd_GETX | 47 10.28% 10.28% | 55 12.04% 22.32% | 52 11.38% 33.70% | 62 13.57% 47.26% | 56 12.25% 59.52% | 56 12.25% 71.77% | 77 16.85% 88.62% | 52 11.38% 100.00%
-system.ruby.l1_cntrl0.E.Fwd_GETX::total 457
-
-system.ruby.l1_cntrl0.E.Fwd_GETS | 7 10.29% 10.29% | 9 13.24% 23.53% | 12 17.65% 41.18% | 5 7.35% 48.53% | 14 20.59% 69.12% | 7 10.29% 79.41% | 7 10.29% 89.71% | 7 10.29% 100.00%
-system.ruby.l1_cntrl0.E.Fwd_GETS::total 68
-
-system.ruby.l1_cntrl0.M.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.l1_cntrl0.M.Load::total 3
-
-system.ruby.l1_cntrl0.M.Store | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.l1_cntrl0.M.Store::total 3
-
-system.ruby.l1_cntrl0.M.Inv | 12660 12.65% 12.65% | 12445 12.44% 25.09% | 12509 12.50% 37.59% | 12484 12.47% 50.06% | 12663 12.65% 62.71% | 12517 12.51% 75.22% | 12326 12.32% 87.54% | 12472 12.46% 100.00%
-system.ruby.l1_cntrl0.M.Inv::total 100076
-
-system.ruby.l1_cntrl0.M.L1_Replacement | 14031 12.44% 12.44% | 14149 12.55% 24.99% | 14049 12.46% 37.44% | 13992 12.41% 49.85% | 14152 12.55% 62.40% | 14005 12.42% 74.81% | 14224 12.61% 87.43% | 14181 12.57% 100.00%
-system.ruby.l1_cntrl0.M.L1_Replacement::total 112783
-
-system.ruby.l1_cntrl0.M.Fwd_GETX | 34 14.05% 14.05% | 25 10.33% 24.38% | 30 12.40% 36.78% | 32 13.22% 50.00% | 26 10.74% 60.74% | 36 14.88% 75.62% | 27 11.16% 86.78% | 32 13.22% 100.00%
-system.ruby.l1_cntrl0.M.Fwd_GETX::total 242
-
-system.ruby.l1_cntrl0.M.Fwd_GETS | 59 13.08% 13.08% | 60 13.30% 26.39% | 61 13.53% 39.91% | 63 13.97% 53.88% | 54 11.97% 65.85% | 40 8.87% 74.72% | 53 11.75% 86.47% | 61 13.53% 100.00%
-system.ruby.l1_cntrl0.M.Fwd_GETS::total 451
-
-system.ruby.l1_cntrl0.IS.Inv | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.l1_cntrl0.IS.Inv::total 2
-
-system.ruby.l1_cntrl0.IS.L1_Replacement | 297388 12.54% 12.54% | 295578 12.46% 24.99% | 296859 12.51% 37.51% | 294148 12.40% 49.91% | 297188 12.53% 62.43% | 294582 12.42% 74.85% | 298840 12.60% 87.44% | 297864 12.56% 100.00%
-system.ruby.l1_cntrl0.IS.L1_Replacement::total 2372447
-
-system.ruby.l1_cntrl0.IS.Data_Exclusive | 48989 12.54% 12.54% | 48607 12.44% 24.98% | 48775 12.49% 37.47% | 48593 12.44% 49.91% | 48923 12.52% 62.44% | 48630 12.45% 74.88% | 49230 12.60% 87.49% | 48877 12.51% 100.00%
-system.ruby.l1_cntrl0.IS.Data_Exclusive::total 390624
-
-system.ruby.l1_cntrl0.IS.DataS_fromL1 | 147 12.55% 12.55% | 148 12.64% 25.19% | 149 12.72% 37.92% | 152 12.98% 50.90% | 133 11.36% 62.25% | 124 10.59% 72.84% | 182 15.54% 88.39% | 136 11.61% 100.00%
-system.ruby.l1_cntrl0.IS.DataS_fromL1::total 1171
-
-system.ruby.l1_cntrl0.IS.Data_all_Acks | 637 12.67% 12.67% | 618 12.29% 24.97% | 589 11.72% 36.68% | 633 12.59% 49.27% | 686 13.65% 62.92% | 611 12.15% 75.07% | 629 12.51% 87.59% | 624 12.41% 100.00%
-system.ruby.l1_cntrl0.IS.Data_all_Acks::total 5027
-
-system.ruby.l1_cntrl0.IM.L1_Replacement | 159682 12.56% 12.56% | 159314 12.53% 25.09% | 158837 12.49% 37.58% | 157683 12.40% 49.98% | 159689 12.56% 62.54% | 159963 12.58% 75.12% | 157731 12.41% 87.53% | 158595 12.47% 100.00%
-system.ruby.l1_cntrl0.IM.L1_Replacement::total 1271494
-
-system.ruby.l1_cntrl0.IM.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
-system.ruby.l1_cntrl0.IM.Data::total 11
-
-system.ruby.l1_cntrl0.IM.Data_all_Acks | 26783 12.54% 12.54% | 26677 12.49% 25.04% | 26648 12.48% 37.51% | 26571 12.44% 49.96% | 26892 12.59% 62.55% | 26596 12.45% 75.01% | 26629 12.47% 87.48% | 26745 12.52% 100.00%
-system.ruby.l1_cntrl0.IM.Data_all_Acks::total 213541
-
-system.ruby.l1_cntrl0.SM.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
-system.ruby.l1_cntrl0.SM.Ack::total 11
-
-system.ruby.l1_cntrl0.SM.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
-system.ruby.l1_cntrl0.SM.Ack_all::total 11
-
-system.ruby.l1_cntrl0.IS_I.Data_all_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00%
-system.ruby.l1_cntrl0.IS_I.Data_all_Acks::total 2
-
-system.ruby.l1_cntrl0.M_I.Inv | 37277 12.51% 12.51% | 36920 12.39% 24.90% | 37310 12.52% 37.41% | 36987 12.41% 49.82% | 37511 12.59% 62.41% | 37013 12.42% 74.83% | 37760 12.67% 87.50% | 37258 12.50% 100.00%
-system.ruby.l1_cntrl0.M_I.Inv::total 298036
-
-system.ruby.l1_cntrl0.M_I.Fwd_GETX | 117 12.14% 12.14% | 140 14.52% 26.66% | 116 12.03% 38.69% | 106 11.00% 49.69% | 133 13.80% 63.49% | 112 11.62% 75.10% | 108 11.20% 86.31% | 132 13.69% 100.00%
-system.ruby.l1_cntrl0.M_I.Fwd_GETX::total 964
-
-system.ruby.l1_cntrl0.M_I.Fwd_GETS | 93 14.26% 14.26% | 82 12.58% 26.84% | 80 12.27% 39.11% | 87 13.34% 52.45% | 81 12.42% 64.88% | 82 12.58% 77.45% | 73 11.20% 88.65% | 74 11.35% 100.00%
-system.ruby.l1_cntrl0.M_I.Fwd_GETS::total 652
-
-system.ruby.l1_cntrl0.M_I.WB_Ack | 2624 13.02% 13.02% | 2482 12.31% 25.33% | 2530 12.55% 37.88% | 2483 12.32% 50.19% | 2584 12.82% 63.01% | 2356 11.69% 74.69% | 2484 12.32% 87.01% | 2618 12.99% 100.00%
-system.ruby.l1_cntrl0.M_I.WB_Ack::total 20161
-
-system.ruby.l1_cntrl0.SINK_WB_ACK.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.l1_cntrl0.SINK_WB_ACK.Load::total 2
-
-system.ruby.l1_cntrl0.SINK_WB_ACK.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
-system.ruby.l1_cntrl0.SINK_WB_ACK.Store::total 1
-
-system.ruby.l1_cntrl0.SINK_WB_ACK.Inv | 32 16.58% 16.58% | 25 12.95% 29.53% | 23 11.92% 41.45% | 27 13.99% 55.44% | 22 11.40% 66.84% | 19 9.84% 76.68% | 28 14.51% 91.19% | 17 8.81% 100.00%
-system.ruby.l1_cntrl0.SINK_WB_ACK.Inv::total 193
-
-system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack | 37486 12.51% 12.51% | 37141 12.39% 24.91% | 37504 12.52% 37.42% | 37179 12.41% 49.83% | 37725 12.59% 62.42% | 37207 12.42% 74.84% | 37941 12.66% 87.50% | 37463 12.50% 100.00%
-system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack::total 299646
-
-system.ruby.l2_cntrl0.L1_GETS 398575 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETX 215875 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_PUTX 21987 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_PUTX_old 305455 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement 8554 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement_clean 4607156 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Data 604993 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Ack 604984 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data 205698 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data_clean 193585 0.00% 0.00%
-system.ruby.l2_cntrl0.Ack 3680 0.00% 0.00%
-system.ruby.l2_cntrl0.Ack_all 186735 0.00% 0.00%
-system.ruby.l2_cntrl0.Unblock 1171 0.00% 0.00%
-system.ruby.l2_cntrl0.Exclusive_Unblock 604175 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETS 393127 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETX 211871 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_PUTX_old 283962 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GETS 4 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GETX 11 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_PUTX 456 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L2_Replacement 1087 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L2_Replacement_clean 2582 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETS 9 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETX 9 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement 7258 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement_clean 12885 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_GETS 1171 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_GETX 1663 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_PUTX 20161 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_PUTX_old 694 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement 5 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement_clean 581173 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.L1_GETS 226 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.L1_GETX 136 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.L1_PUTX_old 13952 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.Mem_Ack 604984 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.WB_Data 3 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.L1_GETS 67 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.L1_GETX 78 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 6266 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.WB_Data 204606 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 193503 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.Ack_all 183064 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.Ack 2590 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.Ack_all 2582 0.00% 0.00%
-system.ruby.l2_cntrl0.S_I.Ack 1090 0.00% 0.00%
-system.ruby.l2_cntrl0.S_I.Ack_all 1087 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.L1_GETS 2509 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.L1_GETX 1307 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.L1_PUTX_old 266 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 2167226 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.Mem_Data 390615 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.L1_GETS 7 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.L1_GETX 3 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.L2_Replacement_clean 14533 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.Mem_Data 2509 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.L1_GETS 1302 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.L1_GETX 709 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.L1_PUTX_old 310 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.L2_Replacement_clean 1170224 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.Mem_Data 211869 0.00% 0.00%
-system.ruby.l2_cntrl0.SS_MB.L2_Replacement 5 0.00% 0.00%
-system.ruby.l2_cntrl0.SS_MB.L2_Replacement_clean 10 0.00% 0.00%
-system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 11 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_GETS 151 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_GETX 87 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_PUTX 840 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 655321 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 604164 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.L1_GETS 2 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.L1_GETX 1 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.L1_PUTX 527 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.L1_PUTX_old 1 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.L2_Replacement_clean 3164 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.WB_Data 727 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 53 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IIB.Unblock 391 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IB.L1_PUTX 1 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IB.L2_Replacement_clean 38 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IB.WB_Data 362 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_IB.WB_Data_clean 29 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_SB.L1_PUTX 2 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_SB.L2_Replacement 199 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_SB.Unblock 780 0.00% 0.00%
-system.ruby.dir_cntrl0.Fetch 604998 0.00% 0.00%
-system.ruby.dir_cntrl0.Data 212955 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Data 604995 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Ack 212951 0.00% 0.00%
-system.ruby.dir_cntrl0.CleanReplacement 392034 0.00% 0.00%
-system.ruby.dir_cntrl0.I.Fetch 604998 0.00% 0.00%
-system.ruby.dir_cntrl0.M.Data 212955 0.00% 0.00%
-system.ruby.dir_cntrl0.M.CleanReplacement 392034 0.00% 0.00%
-system.ruby.dir_cntrl0.IM.Memory_Data 604995 0.00% 0.00%
-system.ruby.dir_cntrl0.MI.Memory_Ack 212951 0.00% 0.00%
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem physmem ruby sys_port_proxy voltage_domain
+boot_osflags=a
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+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=timing
+mem_ranges=0:268435455
+memories=system.physmem system.funcmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=MemTest
+atomic=false
+clk_domain=system.cpu_clk_domain
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+suppress_func_warnings=true
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[0]
+test=system.ruby.l1_cntrl0.sequencer.slave[0]
+
+[system.cpu1]
+type=MemTest
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+clk_domain=system.cpu_clk_domain
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+suppress_func_warnings=true
+sys=system
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+functional=system.funcbus.slave[1]
+test=system.ruby.l1_cntrl1.sequencer.slave[0]
+
+[system.cpu2]
+type=MemTest
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+clk_domain=system.cpu_clk_domain
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+suppress_func_warnings=true
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[2]
+test=system.ruby.l1_cntrl2.sequencer.slave[0]
+
+[system.cpu3]
+type=MemTest
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+max_loads=100000
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+percent_dest_unaligned=50
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+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[3]
+test=system.ruby.l1_cntrl3.sequencer.slave[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+clk_domain=system.cpu_clk_domain
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
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+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[4]
+test=system.ruby.l1_cntrl4.sequencer.slave[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+clk_domain=system.cpu_clk_domain
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[5]
+test=system.ruby.l1_cntrl5.sequencer.slave[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+clk_domain=system.cpu_clk_domain
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
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+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[6]
+test=system.ruby.l1_cntrl6.sequencer.slave[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+clk_domain=system.cpu_clk_domain
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[7]
+test=system.ruby.l1_cntrl7.sequencer.slave[0]
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.funcbus]
+type=NoncoherentBus
+clk_domain=system.clk_domain
+header_cycles=1
+use_default_range=false
+width=8
+master=system.funcmem.port
+slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.funcmem]
+type=SimpleMemory
+bandwidth=0.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+in_addr_map=false
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+port=system.funcbus.master[0]
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=0.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+in_addr_map=true
+latency=30
+latency_var=0
+null=true
+range=0:134217727
+
+[system.ruby]
+type=RubySystem
+children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network profiler
+block_size_bytes=64
+clk_domain=system.ruby.clk_domain
+mem_size=268435456
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.ruby.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=9
+directory=system.ruby.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.ruby.dir_cntrl0.memBuffer
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=5
+size=268435456
+use_map=false
+version=0
+
+[system.ruby.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+clk_domain=system.ruby.memctrl_clk_domain
+dimm_bit_0=12
+dimms_per_channel=2
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+ruby_system=system.ruby
+tFaw=0
+version=0
+
+[system.ruby.l1_cntrl0]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl0.L1Dcache
+L1Icache=system.ruby.l1_cntrl0.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=0
+enable_prefetch=false
+l1_request_latency=2
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+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl0.prefetcher
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+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl0.sequencer
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+version=0
+
+[system.ruby.l1_cntrl0.L1Dcache]
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+replacement_policy=PSEUDO_LRU
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+tagAccessLatency=1
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+
+[system.ruby.l1_cntrl0.L1Icache]
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+start_index_bit=6
+tagAccessLatency=1
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+
+[system.ruby.l1_cntrl0.prefetcher]
+type=Prefetcher
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+nonunit_filter=8
+num_startup_pfs=1
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+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl0.sequencer]
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+clk_domain=system.ruby.clk_domain
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+support_data_reqs=true
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+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.cpu0.test
+
+[system.ruby.l1_cntrl1]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl1.L1Dcache
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+clk_domain=system.ruby.clk_domain
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+version=1
+
+[system.ruby.l1_cntrl1.L1Dcache]
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+
+[system.ruby.l1_cntrl1.L1Icache]
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+
+[system.ruby.l1_cntrl1.prefetcher]
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+
+[system.ruby.l1_cntrl1.sequencer]
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+system=system
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+using_ruby_tester=false
+version=1
+slave=system.cpu1.test
+
+[system.ruby.l1_cntrl2]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl2.L1Dcache
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+clk_domain=system.ruby.clk_domain
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+
+[system.ruby.l1_cntrl2.L1Dcache]
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+
+[system.ruby.l1_cntrl2.L1Icache]
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+
+[system.ruby.l1_cntrl2.prefetcher]
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+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
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+unit_filter=8
+
+[system.ruby.l1_cntrl2.sequencer]
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+clk_domain=system.ruby.clk_domain
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+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=2
+slave=system.cpu2.test
+
+[system.ruby.l1_cntrl3]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl3.L1Dcache
+L1Icache=system.ruby.l1_cntrl3.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=3
+enable_prefetch=false
+l1_request_latency=2
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+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
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+send_evictions=false
+sequencer=system.ruby.l1_cntrl3.sequencer
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+transitions_per_cycle=32
+version=3
+
+[system.ruby.l1_cntrl3.L1Dcache]
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+is_icache=false
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+replacement_policy=PSEUDO_LRU
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+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl3.L1Icache]
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+dataArrayBanks=1
+is_icache=true
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+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl3.prefetcher]
+type=Prefetcher
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+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl3.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl3.L1Dcache
+deadlock_threshold=1000000
+icache=system.ruby.l1_cntrl3.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=3
+slave=system.cpu3.test
+
+[system.ruby.l1_cntrl4]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl4.L1Dcache
+L1Icache=system.ruby.l1_cntrl4.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=4
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl4.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl4.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=4
+
+[system.ruby.l1_cntrl4.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl4.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl4.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl4.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl4.L1Dcache
+deadlock_threshold=1000000
+icache=system.ruby.l1_cntrl4.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=4
+slave=system.cpu4.test
+
+[system.ruby.l1_cntrl5]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl5.L1Dcache
+L1Icache=system.ruby.l1_cntrl5.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=5
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl5.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl5.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=5
+
+[system.ruby.l1_cntrl5.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl5.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl5.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl5.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl5.L1Dcache
+deadlock_threshold=1000000
+icache=system.ruby.l1_cntrl5.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=5
+slave=system.cpu5.test
+
+[system.ruby.l1_cntrl6]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl6.L1Dcache
+L1Icache=system.ruby.l1_cntrl6.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=6
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl6.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl6.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=6
+
+[system.ruby.l1_cntrl6.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl6.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl6.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl6.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl6.L1Dcache
+deadlock_threshold=1000000
+icache=system.ruby.l1_cntrl6.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=6
+slave=system.cpu6.test
+
+[system.ruby.l1_cntrl7]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl7.L1Dcache
+L1Icache=system.ruby.l1_cntrl7.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=7
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl7.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl7.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=7
+
+[system.ruby.l1_cntrl7.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl7.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl7.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl7.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl7.L1Dcache
+deadlock_threshold=1000000
+icache=system.ruby.l1_cntrl7.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=7
+slave=system.cpu7.test
+
+[system.ruby.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cache
+L2cache=system.ruby.l2_cntrl0.L2cache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=8
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.l2_cntrl0.L2cache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=15
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=512
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
+[system.ruby.network]
+type=SimpleNetwork
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
+adaptive_routing=false
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+control_msg_size=8
+endpoint_bandwidth=1000
+ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 system.ruby.network.ext_links9
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5 system.ruby.network.int_links6 system.ruby.network.int_links7 system.ruby.network.int_links8 system.ruby.network.int_links9
+number_of_virtual_networks=10
+routers=system.ruby.network.routers00 system.ruby.network.routers01 system.ruby.network.routers02 system.ruby.network.routers03 system.ruby.network.routers04 system.ruby.network.routers05 system.ruby.network.routers06 system.ruby.network.routers07 system.ruby.network.routers08 system.ruby.network.routers09 system.ruby.network.routers10
+ruby_system=system.ruby
+topology=Crossbar
+
+[system.ruby.network.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl0
+int_node=system.ruby.network.routers00
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl1
+int_node=system.ruby.network.routers01
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl2
+int_node=system.ruby.network.routers02
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.ext_links3]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl3
+int_node=system.ruby.network.routers03
+latency=1
+link_id=3
+weight=1
+
+[system.ruby.network.ext_links4]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl4
+int_node=system.ruby.network.routers04
+latency=1
+link_id=4
+weight=1
+
+[system.ruby.network.ext_links5]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl5
+int_node=system.ruby.network.routers05
+latency=1
+link_id=5
+weight=1
+
+[system.ruby.network.ext_links6]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl6
+int_node=system.ruby.network.routers06
+latency=1
+link_id=6
+weight=1
+
+[system.ruby.network.ext_links7]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl7
+int_node=system.ruby.network.routers07
+latency=1
+link_id=7
+weight=1
+
+[system.ruby.network.ext_links8]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l2_cntrl0
+int_node=system.ruby.network.routers08
+latency=1
+link_id=8
+weight=1
+
+[system.ruby.network.ext_links9]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.dir_cntrl0
+int_node=system.ruby.network.routers09
+latency=1
+link_id=9
+weight=1
+
+[system.ruby.network.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=10
+node_a=system.ruby.network.routers00
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=11
+node_a=system.ruby.network.routers01
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=12
+node_a=system.ruby.network.routers02
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=13
+node_a=system.ruby.network.routers03
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=14
+node_a=system.ruby.network.routers04
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=15
+node_a=system.ruby.network.routers05
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links6]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=16
+node_a=system.ruby.network.routers06
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links7]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=17
+node_a=system.ruby.network.routers07
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links8]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=18
+node_a=system.ruby.network.routers08
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.int_links9]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=19
+node_a=system.ruby.network.routers09
+node_b=system.ruby.network.routers10
+weight=1
+
+[system.ruby.network.routers00]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=0
+virt_nets=10
+
+[system.ruby.network.routers01]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=1
+virt_nets=10
+
+[system.ruby.network.routers02]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=2
+virt_nets=10
+
+[system.ruby.network.routers03]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=3
+virt_nets=10
+
+[system.ruby.network.routers04]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=4
+virt_nets=10
+
+[system.ruby.network.routers05]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=5
+virt_nets=10
+
+[system.ruby.network.routers06]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=6
+virt_nets=10
+
+[system.ruby.network.routers07]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=7
+virt_nets=10
+
+[system.ruby.network.routers08]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=8
+virt_nets=10
+
+[system.ruby.network.routers09]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=9
+virt_nets=10
+
+[system.ruby.network.routers10]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=10
+virt_nets=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+clk_domain=system.clk_domain
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.system_port
+
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
--- /dev/null
+Real time: Sep/22/2013 05:28:42
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 79
+Elapsed_time_in_minutes: 1.31667
+Elapsed_time_in_hours: 0.0219444
+Elapsed_time_in_days: 0.000914352
+
+Virtual_time_in_seconds: 79.09
+Virtual_time_in_minutes: 1.31817
+Virtual_time_in_hours: 0.0219694
+Virtual_time_in_days: 0.000915394
+
+Ruby_current_time: 7257449
+Ruby_start_time: 0
+Ruby_cycles: 7257449
+
+mbytes_resident: 69.1055
+mbytes_total: 251.578
+resident_ratio: 0.275713
+
+Busy Controller Counts:
+L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0
+
+L2Cache-0:3
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 610515 average: 15.9984 | standard deviation: 0.12747 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 610394 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+latency: [binsize: 256 max: 4383 count: 610387 average: 1521.7 | standard deviation: 904.039 | 40769 67074 57492 52511 48992 47365 47915 49117 51274 50977 44598 30540 15468 5041 1079 165 9 1 ]
+latency: LD: [binsize: 256 max: 4383 count: 396832 average: 1523.22 | standard deviation: 904.029 | 26404 43574 37232 34002 32011 30828 31124 31930 33469 33023 29077 19942 10106 3291 700 111 7 1 ]
+latency: ST: [binsize: 256 max: 4219 count: 213555 average: 1518.88 | standard deviation: 904.051 | 14365 23500 20260 18509 16981 16537 16791 17187 17805 17954 15521 10598 5362 1750 379 54 2 ]
+hit latency: [binsize: 1 max: 3 count: 11 average: 3 | standard deviation: 0 | 0 0 0 11 ]
+hit latency: LD: [binsize: 1 max: 3 count: 8 average: 3 | standard deviation: 0 | 0 0 0 8 ]
+hit latency: ST: [binsize: 1 max: 3 count: 3 average: 3 | standard deviation: 0 | 0 0 0 3 ]
+miss latency: [binsize: 256 max: 4383 count: 610376 average: 1521.73 | standard deviation: 904.024 | 40758 67074 57492 52511 48992 47365 47915 49117 51274 50977 44598 30540 15468 5041 1079 165 9 1 ]
+miss latency: LD: [binsize: 256 max: 4383 count: 396824 average: 1523.25 | standard deviation: 904.013 | 26396 43574 37232 34002 32011 30828 31124 31930 33469 33023 29077 19942 10106 3291 700 111 7 1 ]
+miss latency: ST: [binsize: 256 max: 4219 count: 213552 average: 1518.9 | standard deviation: 904.04 | 14362 23500 20260 18509 16981 16537 16791 17187 17805 17954 15521 10598 5362 1750 379 54 2 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 32 max: 952 count: 4856797 average: 43.4082 | standard deviation: 104.144 | 4025692 47689 64638 48612 56875 68710 62101 82292 81634 76798 75935 59926 43791 30096 16740 8442 4032 1777 627 240 88 19 15 14 2 5 2 1 2 2 ]
+ virtual_network_0_delay_cycles: [binsize: 32 max: 952 count: 1535534 average: 133.924 | standard deviation: 149.364 | 704440 47678 64638 48612 56875 68710 62101 82292 81634 76798 75935 59926 43791 30096 16740 8442 4032 1777 627 240 88 19 15 14 2 5 2 1 2 2 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 25 count: 2729880 average: 1.39963 | standard deviation: 2.33339 | 1665086 261419 142358 182063 191213 107497 51010 39587 36260 24170 11876 5896 4335 3537 1939 669 358 307 184 52 28 21 11 2 1 1 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 36 count: 591383 average: 2.29961 | standard deviation: 3.36899 | 265676 88575 43296 28113 50459 44852 14076 8341 11694 10048 7138 3986 1859 2745 3765 1841 1033 709 762 751 478 229 183 320 183 91 54 43 40 21 9 2 6 3 0 0 2 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- /dev/null
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+system.cpu3: completed 10000 read, 5414 write accesses @719275
+system.cpu1: completed 10000 read, 5207 write accesses @725827
+system.cpu2: completed 10000 read, 5346 write accesses @726254
+system.cpu6: completed 10000 read, 5345 write accesses @729597
+system.cpu7: completed 10000 read, 5419 write accesses @731574
+system.cpu4: completed 10000 read, 5529 write accesses @736931
+system.cpu5: completed 10000 read, 5440 write accesses @744470
+system.cpu0: completed 10000 read, 5379 write accesses @746243
+system.cpu3: completed 20000 read, 10692 write accesses @1453209
+system.cpu1: completed 20000 read, 10572 write accesses @1457166
+system.cpu2: completed 20000 read, 10817 write accesses @1460941
+system.cpu7: completed 20000 read, 11051 write accesses @1471674
+system.cpu4: completed 20000 read, 10890 write accesses @1471936
+system.cpu5: completed 20000 read, 10727 write accesses @1478654
+system.cpu6: completed 20000 read, 10906 write accesses @1482356
+system.cpu0: completed 20000 read, 10698 write accesses @1484885
+system.cpu2: completed 30000 read, 16174 write accesses @2184715
+system.cpu6: completed 30000 read, 16276 write accesses @2193615
+system.cpu0: completed 30000 read, 16014 write accesses @2197245
+system.cpu7: completed 30000 read, 16583 write accesses @2199803
+system.cpu1: completed 30000 read, 16153 write accesses @2202627
+system.cpu4: completed 30000 read, 16326 write accesses @2206424
+system.cpu3: completed 30000 read, 16120 write accesses @2214933
+system.cpu5: completed 30000 read, 16017 write accesses @2228709
+system.cpu6: completed 40000 read, 21587 write accesses @2901116
+system.cpu2: completed 40000 read, 21416 write accesses @2916609
+system.cpu0: completed 40000 read, 21318 write accesses @2930718
+system.cpu1: completed 40000 read, 21576 write accesses @2933338
+system.cpu7: completed 40000 read, 22016 write accesses @2933661
+system.cpu4: completed 40000 read, 21632 write accesses @2934839
+system.cpu3: completed 40000 read, 21495 write accesses @2950362
+system.cpu5: completed 40000 read, 21476 write accesses @2978482
+system.cpu6: completed 50000 read, 26852 write accesses @3637893
+system.cpu2: completed 50000 read, 26885 write accesses @3654740
+system.cpu1: completed 50000 read, 27034 write accesses @3657767
+system.cpu0: completed 50000 read, 26670 write accesses @3659997
+system.cpu4: completed 50000 read, 26987 write accesses @3671541
+system.cpu7: completed 50000 read, 27458 write accesses @3674943
+system.cpu3: completed 50000 read, 26989 write accesses @3692057
+system.cpu5: completed 50000 read, 26964 write accesses @3706034
+system.cpu6: completed 60000 read, 32004 write accesses @4355566
+system.cpu0: completed 60000 read, 32011 write accesses @4386276
+system.cpu4: completed 60000 read, 32458 write accesses @4393617
+system.cpu1: completed 60000 read, 32363 write accesses @4400443
+system.cpu2: completed 60000 read, 32317 write accesses @4403435
+system.cpu7: completed 60000 read, 32808 write accesses @4408380
+system.cpu3: completed 60000 read, 32368 write accesses @4439846
+system.cpu5: completed 60000 read, 32369 write accesses @4442699
+system.cpu6: completed 70000 read, 37273 write accesses @5071946
+system.cpu0: completed 70000 read, 37486 write accesses @5119164
+system.cpu4: completed 70000 read, 37898 write accesses @5125200
+system.cpu7: completed 70000 read, 38069 write accesses @5133382
+system.cpu1: completed 70000 read, 37837 write accesses @5136537
+system.cpu2: completed 70000 read, 37818 write accesses @5139253
+system.cpu5: completed 70000 read, 37708 write accesses @5173290
+system.cpu3: completed 70000 read, 37836 write accesses @5178083
+system.cpu6: completed 80000 read, 42670 write accesses @5803436
+system.cpu7: completed 80000 read, 43237 write accesses @5856290
+system.cpu4: completed 80000 read, 43274 write accesses @5860905
+system.cpu2: completed 80000 read, 43098 write accesses @5864154
+system.cpu0: completed 80000 read, 43136 write accesses @5865993
+system.cpu1: completed 80000 read, 43319 write accesses @5873155
+system.cpu5: completed 80000 read, 43110 write accesses @5912619
+system.cpu3: completed 80000 read, 43527 write accesses @5915226
+system.cpu6: completed 90000 read, 47938 write accesses @6517300
+system.cpu7: completed 90000 read, 48616 write accesses @6584472
+system.cpu2: completed 90000 read, 48495 write accesses @6590070
+system.cpu0: completed 90000 read, 48585 write accesses @6598491
+system.cpu1: completed 90000 read, 48584 write accesses @6599764
+system.cpu4: completed 90000 read, 48685 write accesses @6602186
+system.cpu5: completed 90000 read, 48384 write accesses @6637212
+system.cpu3: completed 90000 read, 48869 write accesses @6654178
+system.cpu6: completed 100000 read, 53414 write accesses @7257449
+hack: be nice to actually delete the event here
--- /dev/null
+Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:23
+gem5 executing on zizzer
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 7257449 because maximum number of loads reached
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.007257 # Number of seconds simulated
+sim_ticks 7257449 # Number of ticks simulated
+final_tick 7257449 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_tick_rate 91873 # Simulator tick rate (ticks/s)
+host_mem_usage 257620 # Number of bytes of host memory used
+host_seconds 78.99 # Real time elapsed on the host
+system.ruby.l1_cntrl4.L1Dcache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Dcache.demand_misses 76641 # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Dcache.demand_accesses 76643 # Number of cache demand accesses
+system.ruby.l1_cntrl4.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl4.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl4.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl4.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl4.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl4.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl4.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl4.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl4.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl4.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl4.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl4.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl5.L1Dcache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Dcache.demand_misses 75966 # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Dcache.demand_accesses 75968 # Number of cache demand accesses
+system.ruby.l1_cntrl5.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl5.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl5.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl5.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl5.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl5.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl5.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl5.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl5.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl5.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl5.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl5.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl6.L1Dcache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Dcache.demand_misses 76675 # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Dcache.demand_accesses 76675 # Number of cache demand accesses
+system.ruby.l1_cntrl6.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl6.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl6.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl6.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl6.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl6.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl6.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl6.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl6.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl6.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl6.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl6.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl7.L1Dcache.demand_hits 2 # Number of cache demand hits
+system.ruby.l1_cntrl7.L1Dcache.demand_misses 76386 # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Dcache.demand_accesses 76388 # Number of cache demand accesses
+system.ruby.l1_cntrl7.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl7.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl7.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl7.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl7.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl7.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl7.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl7.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl7.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl7.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl7.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl7.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 3 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 76561 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 76564 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl1.L1Dcache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Dcache.demand_misses 76056 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Dcache.demand_accesses 76056 # Number of cache demand accesses
+system.ruby.l1_cntrl1.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl1.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl1.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl1.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl1.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl1.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl2.L1Dcache.demand_hits 1 # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Dcache.demand_misses 76165 # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Dcache.demand_accesses 76166 # Number of cache demand accesses
+system.ruby.l1_cntrl2.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl2.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl2.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl2.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl2.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl2.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl2.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl2.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl2.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl2.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl2.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl2.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l1_cntrl3.L1Dcache.demand_hits 1 # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Dcache.demand_misses 75953 # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Dcache.demand_accesses 75954 # Number of cache demand accesses
+system.ruby.l1_cntrl3.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl3.L1Icache.demand_misses 0 # Number of cache demand misses
+system.ruby.l1_cntrl3.L1Icache.demand_accesses 0 # Number of cache demand accesses
+system.ruby.l1_cntrl3.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl3.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl3.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl3.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl3.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl3.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl3.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl3.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl3.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.l2_cntrl0.L2cache.demand_hits 33 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 610348 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 610381 # Number of cache demand accesses
+system.ruby.network.routers00.percent_links_utilized 5.463118
+system.ruby.network.routers00.msg_count.Control::0 76561
+system.ruby.network.routers00.msg_count.Request_Control::0 74092
+system.ruby.network.routers00.msg_count.Response_Data::1 77073
+system.ruby.network.routers00.msg_count.Response_Control::1 63910
+system.ruby.network.routers00.msg_count.Response_Control::2 75920
+system.ruby.network.routers00.msg_count.Writeback_Data::0 14031
+system.ruby.network.routers00.msg_count.Writeback_Data::1 49937
+system.ruby.network.routers00.msg_count.Writeback_Control::0 26080
+system.ruby.network.routers00.msg_bytes.Control::0 612488
+system.ruby.network.routers00.msg_bytes.Request_Control::0 592736
+system.ruby.network.routers00.msg_bytes.Response_Data::1 5549256
+system.ruby.network.routers00.msg_bytes.Response_Control::1 511280
+system.ruby.network.routers00.msg_bytes.Response_Control::2 607360
+system.ruby.network.routers00.msg_bytes.Writeback_Data::0 1010232
+system.ruby.network.routers00.msg_bytes.Writeback_Data::1 3595464
+system.ruby.network.routers00.msg_bytes.Writeback_Control::0 208640
+system.ruby.network.routers01.percent_links_utilized 5.425770
+system.ruby.network.routers01.msg_count.Control::0 76056
+system.ruby.network.routers01.msg_count.Request_Control::0 73721
+system.ruby.network.routers01.msg_count.Response_Data::1 76574
+system.ruby.network.routers01.msg_count.Response_Control::1 63612
+system.ruby.network.routers01.msg_count.Response_Control::2 75434
+system.ruby.network.routers01.msg_count.Writeback_Data::0 14149
+system.ruby.network.routers01.msg_count.Writeback_Data::1 49365
+system.ruby.network.routers01.msg_count.Writeback_Control::0 25475
+system.ruby.network.routers01.msg_bytes.Control::0 608448
+system.ruby.network.routers01.msg_bytes.Request_Control::0 589768
+system.ruby.network.routers01.msg_bytes.Response_Data::1 5513328
+system.ruby.network.routers01.msg_bytes.Response_Control::1 508896
+system.ruby.network.routers01.msg_bytes.Response_Control::2 603472
+system.ruby.network.routers01.msg_bytes.Writeback_Data::0 1018728
+system.ruby.network.routers01.msg_bytes.Writeback_Data::1 3554280
+system.ruby.network.routers01.msg_bytes.Writeback_Control::0 203800
+system.ruby.network.routers02.percent_links_utilized 5.442570
+system.ruby.network.routers02.msg_count.Control::0 76165
+system.ruby.network.routers02.msg_count.Request_Control::0 73785
+system.ruby.network.routers02.msg_count.Response_Data::1 76666
+system.ruby.network.routers02.msg_count.Response_Control::1 63651
+system.ruby.network.routers02.msg_count.Response_Control::2 75573
+system.ruby.network.routers02.msg_count.Writeback_Data::0 14049
+system.ruby.network.routers02.msg_count.Writeback_Data::1 49819
+system.ruby.network.routers02.msg_count.Writeback_Control::0 25987
+system.ruby.network.routers02.msg_bytes.Control::0 609320
+system.ruby.network.routers02.msg_bytes.Request_Control::0 590280
+system.ruby.network.routers02.msg_bytes.Response_Data::1 5519952
+system.ruby.network.routers02.msg_bytes.Response_Control::1 509208
+system.ruby.network.routers02.msg_bytes.Response_Control::2 604584
+system.ruby.network.routers02.msg_bytes.Writeback_Data::0 1011528
+system.ruby.network.routers02.msg_bytes.Writeback_Data::1 3586968
+system.ruby.network.routers02.msg_bytes.Writeback_Control::0 207896
+system.ruby.network.routers03.percent_links_utilized 5.419659
+system.ruby.network.routers03.msg_count.Control::0 75953
+system.ruby.network.routers03.msg_count.Request_Control::0 73621
+system.ruby.network.routers03.msg_count.Response_Data::1 76459
+system.ruby.network.routers03.msg_count.Response_Control::1 63457
+system.ruby.network.routers03.msg_count.Response_Control::2 75316
+system.ruby.network.routers03.msg_count.Writeback_Data::0 13992
+system.ruby.network.routers03.msg_count.Writeback_Data::1 49471
+system.ruby.network.routers03.msg_count.Writeback_Control::0 25671
+system.ruby.network.routers03.msg_bytes.Control::0 607624
+system.ruby.network.routers03.msg_bytes.Request_Control::0 588968
+system.ruby.network.routers03.msg_bytes.Response_Data::1 5505048
+system.ruby.network.routers03.msg_bytes.Response_Control::1 507656
+system.ruby.network.routers03.msg_bytes.Response_Control::2 602528
+system.ruby.network.routers03.msg_bytes.Writeback_Data::0 1007424
+system.ruby.network.routers03.msg_bytes.Writeback_Data::1 3561912
+system.ruby.network.routers03.msg_bytes.Writeback_Control::0 205368
+system.ruby.network.routers04.percent_links_utilized 5.477861
+system.ruby.network.routers04.msg_count.Control::0 76641
+system.ruby.network.routers04.msg_count.Request_Control::0 74200
+system.ruby.network.routers04.msg_count.Response_Data::1 77150
+system.ruby.network.routers04.msg_count.Response_Control::1 63977
+system.ruby.network.routers04.msg_count.Response_Control::2 75951
+system.ruby.network.routers04.msg_count.Writeback_Data::0 14152
+system.ruby.network.routers04.msg_count.Writeback_Data::1 50174
+system.ruby.network.routers04.msg_count.Writeback_Control::0 26159
+system.ruby.network.routers04.msg_bytes.Control::0 613128
+system.ruby.network.routers04.msg_bytes.Request_Control::0 593600
+system.ruby.network.routers04.msg_bytes.Response_Data::1 5554800
+system.ruby.network.routers04.msg_bytes.Response_Control::1 511816
+system.ruby.network.routers04.msg_bytes.Response_Control::2 607608
+system.ruby.network.routers04.msg_bytes.Writeback_Data::0 1018944
+system.ruby.network.routers04.msg_bytes.Writeback_Data::1 3612528
+system.ruby.network.routers04.msg_bytes.Writeback_Control::0 209272
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+system.ruby.dir_cntrl0.memBuffer.memRead 604997 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 212953 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 50399 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 5089443 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ 172403 # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ 411771 # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 5673617 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 6.936361 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 991356 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 1587349 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 927948 # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 413483 # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait 976938 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memNotOld 192369 # memory stalls due to anti starvation
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 25693 3.14% 3.14% | 25309 3.09% 6.24% | 25639 3.13% 9.37% | 25493 3.12% 12.49% | 25446 3.11% 15.60% | 25240 3.09% 18.68% | 25202 3.08% 21.76% | 25657 3.14% 24.90% | 25510 3.12% 28.02% | 25612 3.13% 31.15% | 25713 3.14% 34.29% | 25863 3.16% 37.46% | 25420 3.11% 40.56% | 25756 3.15% 43.71% | 25574 3.13% 46.84% | 25666 3.14% 49.98% | 25584 3.13% 53.11% | 25558 3.12% 56.23% | 25869 3.16% 59.39% | 25665 3.14% 62.53% | 25398 3.11% 65.64% | 25614 3.13% 68.77% | 25401 3.11% 71.87% | 25740 3.15% 75.02% | 25400 3.11% 78.12% | 25542 3.12% 81.25% | 25601 3.13% 84.38% | 25502 3.12% 87.49% | 25584 3.13% 90.62% | 25779 3.15% 93.77% | 25408 3.11% 96.88% | 25515 3.12% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 817953 # Number of accesses per bank
+
+system.ruby.network.routers09.percent_links_utilized 30.877103
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+system.funcbus.throughput 0 # Throughput (bytes/s)
+system.funcbus.data_through_bus 0 # Total data (bytes)
+system.cpu0.num_reads 99060 # number of read accesses completed
+system.cpu0.num_writes 53442 # number of write accesses completed
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+system.cpu5.num_copies 0 # number of copy accesses completed
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+system.cpu7.num_copies 0 # number of copy accesses completed
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+system.ruby.network.routers10.throttle9.msg_bytes.Response_Control::1 3136272
+system.ruby.l1_cntrl0.Load | 49778 12.54% 12.54% | 49377 12.44% 24.99% | 49516 12.48% 37.46% | 49381 12.44% 49.91% | 49747 12.54% 62.44% | 49368 12.44% 74.88% | 50044 12.61% 87.49% | 49642 12.51% 100.00%
+system.ruby.l1_cntrl0.Load::total 396853
+
+system.ruby.l1_cntrl0.Store | 26786 12.54% 12.54% | 26679 12.49% 25.03% | 26651 12.48% 37.51% | 26574 12.44% 49.96% | 26897 12.59% 62.55% | 26600 12.46% 75.01% | 26631 12.47% 87.48% | 26746 12.52% 100.00%
+system.ruby.l1_cntrl0.Store::total 213564
+
+system.ruby.l1_cntrl0.Inv | 73735 12.53% 12.53% | 73350 12.46% 24.99% | 73434 12.48% 37.47% | 73266 12.45% 49.92% | 73836 12.55% 62.46% | 73403 12.47% 74.93% | 73975 12.57% 87.50% | 73550 12.50% 100.00%
+system.ruby.l1_cntrl0.Inv::total 588549
+
+system.ruby.l1_cntrl0.L1_Replacement | 533617 12.54% 12.54% | 530929 12.48% 25.02% | 531837 12.50% 37.52% | 527767 12.41% 49.93% | 533499 12.54% 62.47% | 530493 12.47% 74.94% | 533236 12.53% 87.48% | 532831 12.52% 100.00%
+system.ruby.l1_cntrl0.L1_Replacement::total 4254209
+
+system.ruby.l1_cntrl0.Fwd_GETX | 198 11.91% 11.91% | 220 13.23% 25.14% | 198 11.91% 37.04% | 200 12.03% 49.07% | 215 12.93% 62.00% | 204 12.27% 74.26% | 212 12.75% 87.01% | 216 12.99% 100.00%
+system.ruby.l1_cntrl0.Fwd_GETX::total 1663
+
+system.ruby.l1_cntrl0.Fwd_GETS | 159 13.58% 13.58% | 151 12.89% 26.47% | 153 13.07% 39.54% | 155 13.24% 52.78% | 149 12.72% 65.50% | 129 11.02% 76.52% | 133 11.36% 87.87% | 142 12.13% 100.00%
+system.ruby.l1_cntrl0.Fwd_GETS::total 1171
+
+system.ruby.l1_cntrl0.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
+system.ruby.l1_cntrl0.Data::total 11
+
+system.ruby.l1_cntrl0.Data_Exclusive | 48989 12.54% 12.54% | 48607 12.44% 24.98% | 48775 12.49% 37.47% | 48593 12.44% 49.91% | 48923 12.52% 62.44% | 48630 12.45% 74.88% | 49230 12.60% 87.49% | 48877 12.51% 100.00%
+system.ruby.l1_cntrl0.Data_Exclusive::total 390624
+
+system.ruby.l1_cntrl0.DataS_fromL1 | 147 12.55% 12.55% | 148 12.64% 25.19% | 149 12.72% 37.92% | 152 12.98% 50.90% | 133 11.36% 62.25% | 124 10.59% 72.84% | 182 15.54% 88.39% | 136 11.61% 100.00%
+system.ruby.l1_cntrl0.DataS_fromL1::total 1171
+
+system.ruby.l1_cntrl0.Data_all_Acks | 27420 12.55% 12.55% | 27295 12.49% 25.03% | 27237 12.46% 37.49% | 27204 12.45% 49.94% | 27578 12.62% 62.56% | 27207 12.45% 75.01% | 27259 12.47% 87.48% | 27370 12.52% 100.00%
+system.ruby.l1_cntrl0.Data_all_Acks::total 218570
+
+system.ruby.l1_cntrl0.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
+system.ruby.l1_cntrl0.Ack::total 11
+
+system.ruby.l1_cntrl0.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
+system.ruby.l1_cntrl0.Ack_all::total 11
+
+system.ruby.l1_cntrl0.WB_Ack | 40110 12.54% 12.54% | 39623 12.39% 24.93% | 40034 12.52% 37.45% | 39662 12.40% 49.85% | 40309 12.60% 62.46% | 39563 12.37% 74.83% | 40425 12.64% 87.47% | 40081 12.53% 100.00%
+system.ruby.l1_cntrl0.WB_Ack::total 319807
+
+system.ruby.l1_cntrl0.NP.Load | 49768 12.54% 12.54% | 49368 12.44% 24.99% | 49506 12.48% 37.46% | 49370 12.44% 49.90% | 49736 12.53% 62.44% | 49359 12.44% 74.88% | 50040 12.61% 87.49% | 49632 12.51% 100.00%
+system.ruby.l1_cntrl0.NP.Load::total 396779
+
+system.ruby.l1_cntrl0.NP.Store | 26783 12.54% 12.54% | 26673 12.49% 25.04% | 26639 12.48% 37.51% | 26570 12.44% 49.96% | 26890 12.59% 62.55% | 26593 12.45% 75.00% | 26629 12.47% 87.47% | 26744 12.53% 100.00%
+system.ruby.l1_cntrl0.NP.Store::total 213521
+
+system.ruby.l1_cntrl0.NP.Inv | 436 13.54% 13.54% | 404 12.55% 26.09% | 386 11.99% 38.07% | 385 11.96% 50.03% | 420 13.04% 63.07% | 399 12.39% 75.47% | 405 12.58% 88.04% | 385 11.96% 100.00%
+system.ruby.l1_cntrl0.NP.Inv::total 3220
+
+system.ruby.l1_cntrl0.I.Load | 8 12.50% 12.50% | 9 14.06% 26.56% | 9 14.06% 40.62% | 9 14.06% 54.69% | 9 14.06% 68.75% | 8 12.50% 81.25% | 4 6.25% 87.50% | 8 12.50% 100.00%
+system.ruby.l1_cntrl0.I.Load::total 64
+
+system.ruby.l1_cntrl0.I.Store | 2 5.13% 5.13% | 6 15.38% 20.51% | 11 28.21% 48.72% | 4 10.26% 58.97% | 6 15.38% 74.36% | 6 15.38% 89.74% | 2 5.13% 94.87% | 2 5.13% 100.00%
+system.ruby.l1_cntrl0.I.Store::total 39
+
+system.ruby.l1_cntrl0.I.L1_Replacement | 36061 12.53% 12.53% | 36066 12.54% 25.07% | 35776 12.44% 37.51% | 35948 12.50% 50.00% | 35950 12.50% 62.50% | 36049 12.53% 75.03% | 35879 12.47% 87.50% | 35962 12.50% 100.00%
+system.ruby.l1_cntrl0.I.L1_Replacement::total 287691
+
+system.ruby.l1_cntrl0.S.Inv | 475 12.01% 12.01% | 488 12.34% 24.34% | 482 12.18% 36.53% | 528 13.35% 49.87% | 526 13.30% 63.17% | 446 11.27% 74.44% | 511 12.92% 87.36% | 500 12.64% 100.00%
+system.ruby.l1_cntrl0.S.Inv::total 3956
+
+system.ruby.l1_cntrl0.S.L1_Replacement | 375 13.58% 13.58% | 347 12.57% 26.15% | 329 11.92% 38.07% | 325 11.77% 49.84% | 361 13.07% 62.91% | 336 12.17% 75.08% | 360 13.04% 88.12% | 328 11.88% 100.00%
+system.ruby.l1_cntrl0.S.L1_Replacement::total 2761
+
+system.ruby.l1_cntrl0.E.Load | 2 40.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 0 0.00% 40.00% | 1 20.00% 60.00% | 0 0.00% 60.00% | 0 0.00% 60.00% | 2 40.00% 100.00%
+system.ruby.l1_cntrl0.E.Load::total 5
+
+system.ruby.l1_cntrl0.E.Inv | 22855 12.48% 12.48% | 23068 12.60% 25.09% | 22724 12.41% 37.50% | 22855 12.48% 49.98% | 22694 12.40% 62.38% | 23009 12.57% 74.95% | 22944 12.53% 87.48% | 22917 12.52% 100.00%
+system.ruby.l1_cntrl0.E.Inv::total 183066
+
+system.ruby.l1_cntrl0.E.L1_Replacement | 26080 12.60% 12.60% | 25475 12.30% 24.90% | 25987 12.55% 37.45% | 25671 12.40% 49.85% | 26159 12.64% 62.49% | 25558 12.34% 74.83% | 26202 12.66% 87.49% | 25901 12.51% 100.00%
+system.ruby.l1_cntrl0.E.L1_Replacement::total 207033
+
+system.ruby.l1_cntrl0.E.Fwd_GETX | 47 10.28% 10.28% | 55 12.04% 22.32% | 52 11.38% 33.70% | 62 13.57% 47.26% | 56 12.25% 59.52% | 56 12.25% 71.77% | 77 16.85% 88.62% | 52 11.38% 100.00%
+system.ruby.l1_cntrl0.E.Fwd_GETX::total 457
+
+system.ruby.l1_cntrl0.E.Fwd_GETS | 7 10.29% 10.29% | 9 13.24% 23.53% | 12 17.65% 41.18% | 5 7.35% 48.53% | 14 20.59% 69.12% | 7 10.29% 79.41% | 7 10.29% 89.71% | 7 10.29% 100.00%
+system.ruby.l1_cntrl0.E.Fwd_GETS::total 68
+
+system.ruby.l1_cntrl0.M.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 1 33.33% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.l1_cntrl0.M.Load::total 3
+
+system.ruby.l1_cntrl0.M.Store | 1 33.33% 33.33% | 0 0.00% 33.33% | 1 33.33% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.l1_cntrl0.M.Store::total 3
+
+system.ruby.l1_cntrl0.M.Inv | 12660 12.65% 12.65% | 12445 12.44% 25.09% | 12509 12.50% 37.59% | 12484 12.47% 50.06% | 12663 12.65% 62.71% | 12517 12.51% 75.22% | 12326 12.32% 87.54% | 12472 12.46% 100.00%
+system.ruby.l1_cntrl0.M.Inv::total 100076
+
+system.ruby.l1_cntrl0.M.L1_Replacement | 14031 12.44% 12.44% | 14149 12.55% 24.99% | 14049 12.46% 37.44% | 13992 12.41% 49.85% | 14152 12.55% 62.40% | 14005 12.42% 74.81% | 14224 12.61% 87.43% | 14181 12.57% 100.00%
+system.ruby.l1_cntrl0.M.L1_Replacement::total 112783
+
+system.ruby.l1_cntrl0.M.Fwd_GETX | 34 14.05% 14.05% | 25 10.33% 24.38% | 30 12.40% 36.78% | 32 13.22% 50.00% | 26 10.74% 60.74% | 36 14.88% 75.62% | 27 11.16% 86.78% | 32 13.22% 100.00%
+system.ruby.l1_cntrl0.M.Fwd_GETX::total 242
+
+system.ruby.l1_cntrl0.M.Fwd_GETS | 59 13.08% 13.08% | 60 13.30% 26.39% | 61 13.53% 39.91% | 63 13.97% 53.88% | 54 11.97% 65.85% | 40 8.87% 74.72% | 53 11.75% 86.47% | 61 13.53% 100.00%
+system.ruby.l1_cntrl0.M.Fwd_GETS::total 451
+
+system.ruby.l1_cntrl0.IS.Inv | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00%
+system.ruby.l1_cntrl0.IS.Inv::total 2
+
+system.ruby.l1_cntrl0.IS.L1_Replacement | 297388 12.54% 12.54% | 295578 12.46% 24.99% | 296859 12.51% 37.51% | 294148 12.40% 49.91% | 297188 12.53% 62.43% | 294582 12.42% 74.85% | 298840 12.60% 87.44% | 297864 12.56% 100.00%
+system.ruby.l1_cntrl0.IS.L1_Replacement::total 2372447
+
+system.ruby.l1_cntrl0.IS.Data_Exclusive | 48989 12.54% 12.54% | 48607 12.44% 24.98% | 48775 12.49% 37.47% | 48593 12.44% 49.91% | 48923 12.52% 62.44% | 48630 12.45% 74.88% | 49230 12.60% 87.49% | 48877 12.51% 100.00%
+system.ruby.l1_cntrl0.IS.Data_Exclusive::total 390624
+
+system.ruby.l1_cntrl0.IS.DataS_fromL1 | 147 12.55% 12.55% | 148 12.64% 25.19% | 149 12.72% 37.92% | 152 12.98% 50.90% | 133 11.36% 62.25% | 124 10.59% 72.84% | 182 15.54% 88.39% | 136 11.61% 100.00%
+system.ruby.l1_cntrl0.IS.DataS_fromL1::total 1171
+
+system.ruby.l1_cntrl0.IS.Data_all_Acks | 637 12.67% 12.67% | 618 12.29% 24.97% | 589 11.72% 36.68% | 633 12.59% 49.27% | 686 13.65% 62.92% | 611 12.15% 75.07% | 629 12.51% 87.59% | 624 12.41% 100.00%
+system.ruby.l1_cntrl0.IS.Data_all_Acks::total 5027
+
+system.ruby.l1_cntrl0.IM.L1_Replacement | 159682 12.56% 12.56% | 159314 12.53% 25.09% | 158837 12.49% 37.58% | 157683 12.40% 49.98% | 159689 12.56% 62.54% | 159963 12.58% 75.12% | 157731 12.41% 87.53% | 158595 12.47% 100.00%
+system.ruby.l1_cntrl0.IM.L1_Replacement::total 1271494
+
+system.ruby.l1_cntrl0.IM.Data | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
+system.ruby.l1_cntrl0.IM.Data::total 11
+
+system.ruby.l1_cntrl0.IM.Data_all_Acks | 26783 12.54% 12.54% | 26677 12.49% 25.04% | 26648 12.48% 37.51% | 26571 12.44% 49.96% | 26892 12.59% 62.55% | 26596 12.45% 75.01% | 26629 12.47% 87.48% | 26745 12.52% 100.00%
+system.ruby.l1_cntrl0.IM.Data_all_Acks::total 213541
+
+system.ruby.l1_cntrl0.SM.Ack | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
+system.ruby.l1_cntrl0.SM.Ack::total 11
+
+system.ruby.l1_cntrl0.SM.Ack_all | 1 9.09% 9.09% | 2 18.18% 27.27% | 1 9.09% 36.36% | 0 0.00% 36.36% | 3 27.27% 63.64% | 2 18.18% 81.82% | 1 9.09% 90.91% | 1 9.09% 100.00%
+system.ruby.l1_cntrl0.SM.Ack_all::total 11
+
+system.ruby.l1_cntrl0.IS_I.Data_all_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00%
+system.ruby.l1_cntrl0.IS_I.Data_all_Acks::total 2
+
+system.ruby.l1_cntrl0.M_I.Inv | 37277 12.51% 12.51% | 36920 12.39% 24.90% | 37310 12.52% 37.41% | 36987 12.41% 49.82% | 37511 12.59% 62.41% | 37013 12.42% 74.83% | 37760 12.67% 87.50% | 37258 12.50% 100.00%
+system.ruby.l1_cntrl0.M_I.Inv::total 298036
+
+system.ruby.l1_cntrl0.M_I.Fwd_GETX | 117 12.14% 12.14% | 140 14.52% 26.66% | 116 12.03% 38.69% | 106 11.00% 49.69% | 133 13.80% 63.49% | 112 11.62% 75.10% | 108 11.20% 86.31% | 132 13.69% 100.00%
+system.ruby.l1_cntrl0.M_I.Fwd_GETX::total 964
+
+system.ruby.l1_cntrl0.M_I.Fwd_GETS | 93 14.26% 14.26% | 82 12.58% 26.84% | 80 12.27% 39.11% | 87 13.34% 52.45% | 81 12.42% 64.88% | 82 12.58% 77.45% | 73 11.20% 88.65% | 74 11.35% 100.00%
+system.ruby.l1_cntrl0.M_I.Fwd_GETS::total 652
+
+system.ruby.l1_cntrl0.M_I.WB_Ack | 2624 13.02% 13.02% | 2482 12.31% 25.33% | 2530 12.55% 37.88% | 2483 12.32% 50.19% | 2584 12.82% 63.01% | 2356 11.69% 74.69% | 2484 12.32% 87.01% | 2618 12.99% 100.00%
+system.ruby.l1_cntrl0.M_I.WB_Ack::total 20161
+
+system.ruby.l1_cntrl0.SINK_WB_ACK.Load | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.l1_cntrl0.SINK_WB_ACK.Load::total 2
+
+system.ruby.l1_cntrl0.SINK_WB_ACK.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.l1_cntrl0.SINK_WB_ACK.Store::total 1
+
+system.ruby.l1_cntrl0.SINK_WB_ACK.Inv | 32 16.58% 16.58% | 25 12.95% 29.53% | 23 11.92% 41.45% | 27 13.99% 55.44% | 22 11.40% 66.84% | 19 9.84% 76.68% | 28 14.51% 91.19% | 17 8.81% 100.00%
+system.ruby.l1_cntrl0.SINK_WB_ACK.Inv::total 193
+
+system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack | 37486 12.51% 12.51% | 37141 12.39% 24.91% | 37504 12.52% 37.42% | 37179 12.41% 49.83% | 37725 12.59% 62.42% | 37207 12.42% 74.84% | 37941 12.66% 87.50% | 37463 12.50% 100.00%
+system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack::total 299646
+
+system.ruby.l2_cntrl0.L1_GETS 398575 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETX 215875 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX 21987 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX_old 305455 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement 8554 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement_clean 4607156 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Data 604993 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Ack 604984 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data 205698 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data_clean 193585 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack 3680 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack_all 186735 0.00% 0.00%
+system.ruby.l2_cntrl0.Unblock 1171 0.00% 0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock 604175 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS 393127 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX 211871 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_PUTX_old 283962 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GETS 4 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GETX 11 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_PUTX 456 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement 1087 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement_clean 2582 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETS 9 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETX 9 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement 7258 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement_clean 12885 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_GETS 1171 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_GETX 1663 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_PUTX 20161 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_PUTX_old 694 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement 5 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement_clean 581173 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.L1_GETS 226 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.L1_GETX 136 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.L1_PUTX_old 13952 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.Mem_Ack 604984 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.WB_Data 3 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_I.Ack_all 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.L1_GETS 67 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.L1_GETX 78 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 6266 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data 204606 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 193503 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.Ack_all 183064 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack 2590 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack_all 2582 0.00% 0.00%
+system.ruby.l2_cntrl0.S_I.Ack 1090 0.00% 0.00%
+system.ruby.l2_cntrl0.S_I.Ack_all 1087 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.L1_GETS 2509 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.L1_GETX 1307 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.L1_PUTX_old 266 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 2167226 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.Mem_Data 390615 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.L1_GETS 7 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.L1_GETX 3 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.L2_Replacement_clean 14533 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.Mem_Data 2509 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.L1_GETS 1302 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.L1_GETX 709 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.L1_PUTX_old 310 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.L2_Replacement_clean 1170224 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.Mem_Data 211869 0.00% 0.00%
+system.ruby.l2_cntrl0.SS_MB.L2_Replacement 5 0.00% 0.00%
+system.ruby.l2_cntrl0.SS_MB.L2_Replacement_clean 10 0.00% 0.00%
+system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 11 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_GETS 151 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_GETX 87 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_PUTX 840 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 655321 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 604164 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.L1_GETS 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.L1_GETX 1 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.L1_PUTX 527 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.L1_PUTX_old 1 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.L2_Replacement_clean 3164 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.WB_Data 727 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 53 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IIB.Unblock 391 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IB.L1_PUTX 1 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IB.L2_Replacement_clean 38 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IB.WB_Data 362 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_IB.WB_Data_clean 29 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_SB.L1_PUTX 2 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_SB.L2_Replacement 199 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_SB.Unblock 780 0.00% 0.00%
+system.ruby.dir_cntrl0.Fetch 604998 0.00% 0.00%
+system.ruby.dir_cntrl0.Data 212955 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Data 604995 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Ack 212951 0.00% 0.00%
+system.ruby.dir_cntrl0.CleanReplacement 392034 0.00% 0.00%
+system.ruby.dir_cntrl0.I.Fetch 604998 0.00% 0.00%
+system.ruby.dir_cntrl0.M.Data 212955 0.00% 0.00%
+system.ruby.dir_cntrl0.M.CleanReplacement 392034 0.00% 0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data 604995 0.00% 0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack 212951 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
+++ /dev/null
-[root]
-type=Root
-children=system
-full_system=false
-time_sync_enable=false
-time_sync_period=100000000
-time_sync_spin_threshold=100000
-
-[system]
-type=System
-children=clk_domain physmem ruby sys_port_proxy tester voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-init_param=0
-kernel=
-load_addr_mask=1099511627775
-mem_mode=timing
-mem_ranges=0:268435455
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.sys_port_proxy.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.physmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-in_addr_map=true
-latency=30
-latency_var=0
-null=true
-range=0:134217727
-
-[system.ruby]
-type=RubySystem
-children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
-block_size_bytes=64
-clk_domain=system.ruby.clk_domain
-mem_size=268435456
-no_mem_vec=false
-random_seed=1234
-randomization=true
-stats_filename=ruby.stats
-
-[system.ruby.clk_domain]
-type=SrcClockDomain
-clock=1
-voltage_domain=system.voltage_domain
-
-[system.ruby.dir_cntrl0]
-type=Directory_Controller
-children=directory memBuffer
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=2
-directory=system.ruby.dir_cntrl0.directory
-directory_latency=6
-memBuffer=system.ruby.dir_cntrl0.memBuffer
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_mem_ctrl_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.dir_cntrl0.directory]
-type=RubyDirectoryMemory
-map_levels=4
-numa_high_bit=5
-size=268435456
-use_map=false
-version=0
-
-[system.ruby.dir_cntrl0.memBuffer]
-type=RubyMemoryControl
-bank_bit_0=8
-bank_busy_time=11
-bank_queue_size=12
-banks_per_rank=8
-basic_bus_busy_time=2
-clk_domain=system.ruby.memctrl_clk_domain
-dimm_bit_0=12
-dimms_per_channel=2
-mem_ctl_latency=12
-mem_fixed_delay=0
-mem_random_arbitrate=0
-rank_bit_0=11
-rank_rank_delay=1
-ranks_per_dimm=2
-read_write_delay=2
-refresh_period=1560
-ruby_system=system.ruby
-tFaw=0
-version=0
-
-[system.ruby.l1_cntrl0]
-type=L1Cache_Controller
-children=L1Dcache L1Icache prefetcher sequencer
-L1Dcache=system.ruby.l1_cntrl0.L1Dcache
-L1Icache=system.ruby.l1_cntrl0.L1Icache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=0
-enable_prefetch=false
-l1_request_latency=2
-l1_response_latency=2
-l2_select_num_bits=0
-number_of_TBEs=256
-peer=Null
-prefetcher=system.ruby.l1_cntrl0.prefetcher
-recycle_latency=10
-ruby_system=system.ruby
-send_evictions=false
-sequencer=system.ruby.l1_cntrl0.sequencer
-to_l2_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.l1_cntrl0.L1Dcache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.L1Icache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=true
-latency=3
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=256
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.l1_cntrl0.prefetcher]
-type=Prefetcher
-cross_page=false
-nonunit_filter=8
-num_startup_pfs=1
-num_streams=4
-pf_per_stream=1
-train_misses=4
-unit_filter=8
-
-[system.ruby.l1_cntrl0.sequencer]
-type=RubySequencer
-access_phys_mem=false
-clk_domain=system.ruby.clk_domain
-dcache=system.ruby.l1_cntrl0.L1Dcache
-deadlock_threshold=500000
-icache=system.ruby.l1_cntrl0.L1Icache
-max_outstanding_requests=16
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=true
-version=0
-slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
-
-[system.ruby.l2_cntrl0]
-type=L2Cache_Controller
-children=L2cache
-L2cache=system.ruby.l2_cntrl0.L2cache
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-cntrl_id=1
-l2_request_latency=2
-l2_response_latency=2
-number_of_TBEs=256
-peer=Null
-recycle_latency=10
-ruby_system=system.ruby
-to_l1_latency=1
-transitions_per_cycle=32
-version=0
-
-[system.ruby.l2_cntrl0.L2cache]
-type=RubyCache
-assoc=2
-dataAccessLatency=1
-dataArrayBanks=1
-is_icache=false
-latency=15
-replacement_policy=PSEUDO_LRU
-resourceStalls=false
-size=512
-start_index_bit=6
-tagAccessLatency=1
-tagArrayBanks=1
-
-[system.ruby.memctrl_clk_domain]
-type=DerivedClockDomain
-clk_divider=3
-clk_domain=system.ruby.clk_domain
-
-[system.ruby.network]
-type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
-adaptive_routing=false
-buffer_size=0
-clk_domain=system.ruby.clk_domain
-control_msg_size=8
-endpoint_bandwidth=1000
-ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
-number_of_virtual_networks=10
-routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
-ruby_system=system.ruby
-topology=Crossbar
-
-[system.ruby.network.ext_links0]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l1_cntrl0
-int_node=system.ruby.network.routers0
-latency=1
-link_id=0
-weight=1
-
-[system.ruby.network.ext_links1]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.l2_cntrl0
-int_node=system.ruby.network.routers1
-latency=1
-link_id=1
-weight=1
-
-[system.ruby.network.ext_links2]
-type=SimpleExtLink
-bandwidth_factor=16
-ext_node=system.ruby.dir_cntrl0
-int_node=system.ruby.network.routers2
-latency=1
-link_id=2
-weight=1
-
-[system.ruby.network.int_links0]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.int_links1]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.int_links2]
-type=SimpleIntLink
-bandwidth_factor=16
-latency=1
-link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
-weight=1
-
-[system.ruby.network.routers0]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=0
-virt_nets=10
-
-[system.ruby.network.routers1]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=1
-virt_nets=10
-
-[system.ruby.network.routers2]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=2
-virt_nets=10
-
-[system.ruby.network.routers3]
-type=Switch
-clk_domain=system.ruby.clk_domain
-router_id=3
-virt_nets=10
-
-[system.ruby.profiler]
-type=RubyProfiler
-all_instructions=false
-hot_lines=false
-num_of_sequencers=1
-ruby_system=system.ruby
-
-[system.sys_port_proxy]
-type=RubyPortProxy
-access_phys_mem=true
-clk_domain=system.clk_domain
-ruby_system=system.ruby
-support_data_reqs=true
-support_inst_reqs=true
-system=system
-using_network_tester=false
-using_ruby_tester=false
-version=0
-slave=system.system_port
-
-[system.tester]
-type=RubyTester
-check_flush=false
-checks_to_complete=100
-clk_domain=system.clk_domain
-deadlock_threshold=50000
-num_cpus=1
-system=system
-wakeup_frequency=10
-cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
-cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
-
-[system.voltage_domain]
-type=VoltageDomain
-voltage=1.000000
-
+++ /dev/null
-Real time: Sep/22/2013 05:27:12
-
-Profiler Stats
---------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
-
-Virtual_time_in_seconds: 0.46
-Virtual_time_in_minutes: 0.00766667
-Virtual_time_in_hours: 0.000127778
-Virtual_time_in_days: 5.32407e-06
-
-Ruby_current_time: 318321
-Ruby_start_time: 0
-Ruby_cycles: 318321
-
-mbytes_resident: 65.1133
-mbytes_total: 120.422
-resident_ratio: 0.54071
-
-Busy Controller Counts:
-L1Cache-0:0
-L2Cache-0:0
-Directory-0:0
-
-
-Busy Bank Count:0
-
-sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1012 average: 15.8221 | standard deviation: 1.11991 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 61 937 ]
-
-All Non-Zero Cycle Demand Cache Accesses
-----------------------------------------
-latency: [binsize: 512 max: 8110 count: 997 average: 5056.15 | standard deviation: 2131.53 | 105 35 13 5 2 2 0 2 6 67 198 244 208 75 24 11 ]
-latency: LD: [binsize: 512 max: 7764 count: 44 average: 5504.89 | standard deviation: 1648.56 | 3 0 0 0 0 0 0 0 1 4 10 11 10 3 1 1 ]
-latency: ST: [binsize: 512 max: 8110 count: 897 average: 5296.67 | standard deviation: 1932.9 | 90 4 4 1 2 2 0 2 5 63 188 233 198 72 23 10 ]
-latency: IFETCH: [binsize: 128 max: 2021 count: 56 average: 850.893 | standard deviation: 421.128 | 0 1 4 7 3 15 11 2 1 0 4 4 0 3 0 1 ]
-hit latency: [binsize: 8 max: 117 count: 81 average: 19.5556 | standard deviation: 39.6538 | 68 0 0 0 0 0 0 0 0 0 0 0 2 6 5 ]
-hit latency: LD: [binsize: 1 max: 3 count: 2 average: 2 | standard deviation: 1.41421 | 0 1 0 1 ]
-hit latency: ST: [binsize: 8 max: 117 count: 79 average: 20 | standard deviation: 40.0577 | 66 0 0 0 0 0 0 0 0 0 0 0 2 6 5 ]
-miss latency: [binsize: 512 max: 8110 count: 916 average: 5501.52 | standard deviation: 1581.55 | 24 35 13 5 2 2 0 2 6 67 198 244 208 75 24 11 ]
-miss latency: LD: [binsize: 512 max: 7764 count: 42 average: 5766.93 | standard deviation: 1141.41 | 1 0 0 0 0 0 0 0 1 4 10 11 10 3 1 1 ]
-miss latency: ST: [binsize: 512 max: 8110 count: 818 average: 5806.28 | standard deviation: 1070 | 11 4 4 1 2 2 0 2 5 63 188 233 198 72 23 10 ]
-miss latency: IFETCH: [binsize: 128 max: 2021 count: 56 average: 850.893 | standard deviation: 421.128 | 0 1 4 7 3 15 11 2 1 0 4 4 0 3 0 1 ]
-
-Request vs. RubySystem State Profile
---------------------------------
-
-
-
-Message Delayed Cycles
-----------------------
-Total_delay_cycles: [binsize: 32 max: 1572 count: 7069 average: 39.9154 | standard deviation: 159.247 | 6421 15 38 124 13 11 58 12 11 21 23 10 10 30 13 21 26 16 8 26 17 12 9 25 16 4 10 11 7 8 1 4 2 4 7 1 2 4 1 2 2 1 1 4 2 0 0 3 1 1 ]
- virtual_network_0_delay_cycles: [binsize: 32 max: 1572 count: 2530 average: 110.951 | standard deviation: 251.02 | 1882 15 38 124 13 11 58 12 11 21 23 10 10 30 13 21 26 16 8 26 17 12 9 25 16 4 10 11 7 8 1 4 2 4 7 1 2 4 1 2 2 1 1 4 2 0 0 3 1 1 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 3976 average: 0.342807 | standard deviation: 1.04899 | 3455 133 152 135 45 25 14 8 5 4 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 11 count: 563 average: 0.166963 | standard deviation: 0.907658 | 538 3 6 2 7 4 1 0 1 0 0 1 ]
- virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
- virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+++ /dev/null
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-warn: rounding error > tolerance
- 0.072760 rounded to 0
-hack: be nice to actually delete the event here
+++ /dev/null
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Sep 22 2013 05:27:02
-gem5 started Sep 22 2013 05:27:12
-gem5 executing on zizzer
-command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
-Global frequency set at 1000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 318321 because Ruby Tester completed
+++ /dev/null
-
----------- Begin Simulation Statistics ----------
-sim_seconds 0.000318 # Number of seconds simulated
-sim_ticks 318321 # Number of ticks simulated
-final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 1986485 # Simulator tick rate (ticks/s)
-host_mem_usage 123316 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
-system.ruby.l1_cntrl0.L1Dcache.demand_hits 81 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Dcache.demand_misses 861 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses 942 # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
-system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 # Number of cache demand accesses
-system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
-system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
-system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
-system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
-system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
-system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
-system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
-system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
-system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.network.routers0.percent_links_utilized 1.769362
-system.ruby.network.routers0.msg_count.Control::0 917
-system.ruby.network.routers0.msg_count.Request_Control::0 563
-system.ruby.network.routers0.msg_count.Response_Data::1 915
-system.ruby.network.routers0.msg_count.Response_Control::1 806
-system.ruby.network.routers0.msg_count.Response_Control::2 859
-system.ruby.network.routers0.msg_count.Writeback_Data::0 722
-system.ruby.network.routers0.msg_count.Writeback_Data::1 513
-system.ruby.network.routers0.msg_count.Writeback_Control::0 34
-system.ruby.network.routers0.msg_bytes.Control::0 7336
-system.ruby.network.routers0.msg_bytes.Request_Control::0 4504
-system.ruby.network.routers0.msg_bytes.Response_Data::1 65880
-system.ruby.network.routers0.msg_bytes.Response_Control::1 6448
-system.ruby.network.routers0.msg_bytes.Response_Control::2 6872
-system.ruby.network.routers0.msg_bytes.Writeback_Data::0 51984
-system.ruby.network.routers0.msg_bytes.Writeback_Data::1 36936
-system.ruby.network.routers0.msg_bytes.Writeback_Control::0 272
-system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits
-system.ruby.l2_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses
-system.ruby.l2_cntrl0.L2cache.demand_accesses 917 # Number of cache demand accesses
-system.ruby.network.routers1.percent_links_utilized 3.085407
-system.ruby.network.routers1.msg_count.Control::0 1791
-system.ruby.network.routers1.msg_count.Request_Control::0 563
-system.ruby.network.routers1.msg_count.Response_Data::1 2574
-system.ruby.network.routers1.msg_count.Response_Control::1 1759
-system.ruby.network.routers1.msg_count.Response_Control::2 858
-system.ruby.network.routers1.msg_count.Writeback_Data::0 722
-system.ruby.network.routers1.msg_count.Writeback_Data::1 513
-system.ruby.network.routers1.msg_count.Writeback_Control::0 34
-system.ruby.network.routers1.msg_bytes.Control::0 14328
-system.ruby.network.routers1.msg_bytes.Request_Control::0 4504
-system.ruby.network.routers1.msg_bytes.Response_Data::1 185328
-system.ruby.network.routers1.msg_bytes.Response_Control::1 14072
-system.ruby.network.routers1.msg_bytes.Response_Control::2 6864
-system.ruby.network.routers1.msg_bytes.Writeback_Data::0 51984
-system.ruby.network.routers1.msg_bytes.Writeback_Data::1 36936
-system.ruby.network.routers1.msg_bytes.Writeback_Control::0 272
-system.ruby.dir_cntrl0.memBuffer.memReq 1660 # Total number of memory requests
-system.ruby.dir_cntrl0.memBuffer.memRead 874 # Number of memory reads
-system.ruby.dir_cntrl0.memBuffer.memWrite 786 # Number of memory writes
-system.ruby.dir_cntrl0.memBuffer.memRefresh 2210 # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles 555 # Delay stalled at the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.memInputQ 44 # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls 601 # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.362048 # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy 169 # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy 188 # memory stalls due to busy bus
-system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 104 # memory stalls due to read write turnaround
-system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 64 # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait 30 # memory stalls due to arbitration
-system.ruby.dir_cntrl0.memBuffer.memBankCount | 42 2.53% 2.53% | 51 3.07% 5.60% | 50 3.01% 8.61% | 73 4.40% 13.01% | 73 4.40% 17.41% | 71 4.28% 21.69% | 65 3.92% 25.60% | 49 2.95% 28.55% | 54 3.25% 31.81% | 41 2.47% 34.28% | 50 3.01% 37.29% | 44 2.65% 39.94% | 58 3.49% 43.43% | 48 2.89% 46.33% | 47 2.83% 49.16% | 63 3.80% 52.95% | 57 3.43% 56.39% | 47 2.83% 59.22% | 58 3.49% 62.71% | 57 3.43% 66.14% | 41 2.47% 68.61% | 49 2.95% 71.57% | 46 2.77% 74.34% | 49 2.95% 77.29% | 57 3.43% 80.72% | 45 2.71% 83.43% | 42 2.53% 85.96% | 49 2.95% 88.92% | 45 2.71% 91.63% | 53 3.19% 94.82% | 48 2.89% 97.71% | 38 2.29% 100.00% # Number of accesses per bank
-system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1660 # Number of accesses per bank
-
-system.ruby.network.routers2.percent_links_utilized 1.316910
-system.ruby.network.routers2.msg_count.Control::0 874
-system.ruby.network.routers2.msg_count.Response_Data::1 1660
-system.ruby.network.routers2.msg_count.Response_Control::1 954
-system.ruby.network.routers2.msg_bytes.Control::0 6992
-system.ruby.network.routers2.msg_bytes.Response_Data::1 119520
-system.ruby.network.routers2.msg_bytes.Response_Control::1 7632
-system.ruby.network.routers3.percent_links_utilized 2.057462
-system.ruby.network.routers3.msg_count.Control::0 1791
-system.ruby.network.routers3.msg_count.Request_Control::0 563
-system.ruby.network.routers3.msg_count.Response_Data::1 2575
-system.ruby.network.routers3.msg_count.Response_Control::1 1760
-system.ruby.network.routers3.msg_count.Response_Control::2 858
-system.ruby.network.routers3.msg_count.Writeback_Data::0 722
-system.ruby.network.routers3.msg_count.Writeback_Data::1 513
-system.ruby.network.routers3.msg_count.Writeback_Control::0 34
-system.ruby.network.routers3.msg_bytes.Control::0 14328
-system.ruby.network.routers3.msg_bytes.Request_Control::0 4504
-system.ruby.network.routers3.msg_bytes.Response_Data::1 185400
-system.ruby.network.routers3.msg_bytes.Response_Control::1 14080
-system.ruby.network.routers3.msg_bytes.Response_Control::2 6864
-system.ruby.network.routers3.msg_bytes.Writeback_Data::0 51984
-system.ruby.network.routers3.msg_bytes.Writeback_Data::1 36936
-system.ruby.network.routers3.msg_bytes.Writeback_Control::0 272
-system.ruby.network.msg_count.Control 5373
-system.ruby.network.msg_count.Request_Control 1689
-system.ruby.network.msg_count.Response_Data 7724
-system.ruby.network.msg_count.Response_Control 7854
-system.ruby.network.msg_count.Writeback_Data 3705
-system.ruby.network.msg_count.Writeback_Control 102
-system.ruby.network.msg_byte.Control 42984
-system.ruby.network.msg_byte.Request_Control 13512
-system.ruby.network.msg_byte.Response_Data 556128
-system.ruby.network.msg_byte.Response_Control 62832
-system.ruby.network.msg_byte.Writeback_Data 266760
-system.ruby.network.msg_byte.Writeback_Control 816
-system.ruby.network.routers0.throttle0.link_utilization 1.500686
-system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 563
-system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 915
-system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 756
-system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 4504
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 65880
-system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6048
-system.ruby.network.routers0.throttle1.link_utilization 2.038037
-system.ruby.network.routers0.throttle1.msg_count.Control::0 917
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 50
-system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 859
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 722
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 513
-system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 34
-system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7336
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 400
-system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6872
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 51984
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 36936
-system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 272
-system.ruby.network.routers1.throttle0.link_utilization 3.408509
-system.ruby.network.routers1.throttle0.msg_count.Control::0 917
-system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 873
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 919
-system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 858
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 722
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 513
-system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 34
-system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7336
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62856
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7352
-system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6864
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 51984
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 36936
-system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 272
-system.ruby.network.routers1.throttle1.link_utilization 2.762306
-system.ruby.network.routers1.throttle1.msg_count.Control::0 874
-system.ruby.network.routers1.throttle1.msg_count.Request_Control::0 563
-system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1701
-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 840
-system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6992
-system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::0 4504
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 122472
-system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6720
-system.ruby.network.routers2.throttle0.link_utilization 1.261620
-system.ruby.network.routers2.throttle0.msg_count.Control::0 874
-system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 786
-system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 84
-system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6992
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 56592
-system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 672
-system.ruby.network.routers2.throttle1.link_utilization 1.372200
-system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 874
-system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 870
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62928
-system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6960
-system.ruby.network.routers3.throttle0.link_utilization 1.500686
-system.ruby.network.routers3.throttle0.msg_count.Request_Control::0 563
-system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 915
-system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 756
-system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::0 4504
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 65880
-system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6048
-system.ruby.network.routers3.throttle1.link_utilization 3.410080
-system.ruby.network.routers3.throttle1.msg_count.Control::0 917
-system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 874
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 920
-system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 858
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 722
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 513
-system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 34
-system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7336
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62928
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7360
-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6864
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 51984
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 36936
-system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 272
-system.ruby.network.routers3.throttle2.link_utilization 1.261620
-system.ruby.network.routers3.throttle2.msg_count.Control::0 874
-system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 786
-system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 84
-system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6992
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 56592
-system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 672
-system.ruby.l1_cntrl0.Load 44 0.00% 0.00%
-system.ruby.l1_cntrl0.Ifetch 67 0.00% 0.00%
-system.ruby.l1_cntrl0.Store 898 0.00% 0.00%
-system.ruby.l1_cntrl0.Inv 563 0.00% 0.00%
-system.ruby.l1_cntrl0.L1_Replacement 10398 0.00% 0.00%
-system.ruby.l1_cntrl0.Data_Exclusive 41 0.00% 0.00%
-system.ruby.l1_cntrl0.Data_all_Acks 874 0.00% 0.00%
-system.ruby.l1_cntrl0.Ack_all 1 0.00% 0.00%
-system.ruby.l1_cntrl0.WB_Ack 755 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Load 42 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Ifetch 56 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Store 818 0.00% 0.00%
-system.ruby.l1_cntrl0.NP.Inv 1 0.00% 0.00%
-system.ruby.l1_cntrl0.I.L1_Replacement 145 0.00% 0.00%
-system.ruby.l1_cntrl0.S.Store 1 0.00% 0.00%
-system.ruby.l1_cntrl0.S.Inv 31 0.00% 0.00%
-system.ruby.l1_cntrl0.S.L1_Replacement 11 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Store 2 0.00% 0.00%
-system.ruby.l1_cntrl0.E.Inv 4 0.00% 0.00%
-system.ruby.l1_cntrl0.E.L1_Replacement 34 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Load 2 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Store 77 0.00% 0.00%
-system.ruby.l1_cntrl0.M.Inv 97 0.00% 0.00%
-system.ruby.l1_cntrl0.M.L1_Replacement 722 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.Inv 14 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.L1_Replacement 374 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.Data_Exclusive 41 0.00% 0.00%
-system.ruby.l1_cntrl0.IS.Data_all_Acks 43 0.00% 0.00%
-system.ruby.l1_cntrl0.IM.L1_Replacement 9112 0.00% 0.00%
-system.ruby.l1_cntrl0.IM.Data_all_Acks 817 0.00% 0.00%
-system.ruby.l1_cntrl0.SM.Ack_all 1 0.00% 0.00%
-system.ruby.l1_cntrl0.IS_I.Data_all_Acks 14 0.00% 0.00%
-system.ruby.l1_cntrl0.M_I.Ifetch 10 0.00% 0.00%
-system.ruby.l1_cntrl0.M_I.Inv 416 0.00% 0.00%
-system.ruby.l1_cntrl0.M_I.WB_Ack 340 0.00% 0.00%
-system.ruby.l1_cntrl0.SINK_WB_ACK.Ifetch 1 0.00% 0.00%
-system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack 415 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GET_INSTR 56 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETS 42 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_GETX 818 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_UPGRADE 1 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_PUTX 345 0.00% 0.00%
-system.ruby.l2_cntrl0.L1_PUTX_old 796 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement 291 0.00% 0.00%
-system.ruby.l2_cntrl0.L2_Replacement_clean 1216 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Data 873 0.00% 0.00%
-system.ruby.l2_cntrl0.Mem_Ack 869 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data 495 0.00% 0.00%
-system.ruby.l2_cntrl0.WB_Data_clean 18 0.00% 0.00%
-system.ruby.l2_cntrl0.Ack_all 50 0.00% 0.00%
-system.ruby.l2_cntrl0.Exclusive_Unblock 858 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GET_INSTR 46 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETS 41 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_GETX 787 0.00% 0.00%
-system.ruby.l2_cntrl0.NP.L1_PUTX_old 302 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GETS 1 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_GETX 9 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L1_UPGRADE 1 0.00% 0.00%
-system.ruby.l2_cntrl0.SS.L2_Replacement_clean 46 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GET_INSTR 10 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L1_GETX 22 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement 291 0.00% 0.00%
-system.ruby.l2_cntrl0.M.L2_Replacement_clean 16 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L1_PUTX 340 0.00% 0.00%
-system.ruby.l2_cntrl0.MT.L2_Replacement_clean 517 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.L1_PUTX_old 113 0.00% 0.00%
-system.ruby.l2_cntrl0.M_I.Mem_Ack 869 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 210 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.WB_Data 495 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 18 0.00% 0.00%
-system.ruby.l2_cntrl0.MCT_I.Ack_all 4 0.00% 0.00%
-system.ruby.l2_cntrl0.I_I.Ack_all 46 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 11 0.00% 0.00%
-system.ruby.l2_cntrl0.ISS.Mem_Data 41 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.L2_Replacement_clean 57 0.00% 0.00%
-system.ruby.l2_cntrl0.IS.Mem_Data 46 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.L2_Replacement_clean 219 0.00% 0.00%
-system.ruby.l2_cntrl0.IM.Mem_Data 786 0.00% 0.00%
-system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 10 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_PUTX 5 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 171 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 350 0.00% 0.00%
-system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 848 0.00% 0.00%
-system.ruby.dir_cntrl0.Fetch 874 0.00% 0.00%
-system.ruby.dir_cntrl0.Data 786 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Data 874 0.00% 0.00%
-system.ruby.dir_cntrl0.Memory_Ack 786 0.00% 0.00%
-system.ruby.dir_cntrl0.CleanReplacement 84 0.00% 0.00%
-system.ruby.dir_cntrl0.I.Fetch 874 0.00% 0.00%
-system.ruby.dir_cntrl0.M.Data 786 0.00% 0.00%
-system.ruby.dir_cntrl0.M.CleanReplacement 84 0.00% 0.00%
-system.ruby.dir_cntrl0.IM.Memory_Data 874 0.00% 0.00%
-system.ruby.dir_cntrl0.MI.Memory_Ack 786 0.00% 0.00%
-
----------- End Simulation Statistics ----------
--- /dev/null
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=clk_domain physmem ruby sys_port_proxy tester voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=timing
+mem_ranges=0:268435455
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=0.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+in_addr_map=true
+latency=30
+latency_var=0
+null=true
+range=0:134217727
+
+[system.ruby]
+type=RubySystem
+children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network profiler
+block_size_bytes=64
+clk_domain=system.ruby.clk_domain
+mem_size=268435456
+no_mem_vec=false
+random_seed=1234
+randomization=true
+stats_filename=ruby.stats
+
+[system.ruby.clk_domain]
+type=SrcClockDomain
+clock=1
+voltage_domain=system.voltage_domain
+
+[system.ruby.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=2
+directory=system.ruby.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.ruby.dir_cntrl0.memBuffer
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=5
+size=268435456
+use_map=false
+version=0
+
+[system.ruby.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+clk_domain=system.ruby.memctrl_clk_domain
+dimm_bit_0=12
+dimms_per_channel=2
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+ruby_system=system.ruby
+tFaw=0
+version=0
+
+[system.ruby.l1_cntrl0]
+type=L1Cache_Controller
+children=L1Dcache L1Icache prefetcher sequencer
+L1Dcache=system.ruby.l1_cntrl0.L1Dcache
+L1Icache=system.ruby.l1_cntrl0.L1Icache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=0
+enable_prefetch=false
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+peer=Null
+prefetcher=system.ruby.l1_cntrl0.prefetcher
+recycle_latency=10
+ruby_system=system.ruby
+send_evictions=false
+sequencer=system.ruby.l1_cntrl0.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.l1_cntrl0.L1Dcache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.L1Icache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=true
+latency=3
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=256
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.l1_cntrl0.prefetcher]
+type=Prefetcher
+cross_page=false
+nonunit_filter=8
+num_startup_pfs=1
+num_streams=4
+pf_per_stream=1
+train_misses=4
+unit_filter=8
+
+[system.ruby.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+clk_domain=system.ruby.clk_domain
+dcache=system.ruby.l1_cntrl0.L1Dcache
+deadlock_threshold=500000
+icache=system.ruby.l1_cntrl0.L1Icache
+max_outstanding_requests=16
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=true
+version=0
+slave=system.tester.cpuDataPort[0] system.tester.cpuInstPort[0]
+
+[system.ruby.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cache
+L2cache=system.ruby.l2_cntrl0.L2cache
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+cntrl_id=1
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+peer=Null
+recycle_latency=10
+ruby_system=system.ruby
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.ruby.l2_cntrl0.L2cache]
+type=RubyCache
+assoc=2
+dataAccessLatency=1
+dataArrayBanks=1
+is_icache=false
+latency=15
+replacement_policy=PSEUDO_LRU
+resourceStalls=false
+size=512
+start_index_bit=6
+tagAccessLatency=1
+tagArrayBanks=1
+
+[system.ruby.memctrl_clk_domain]
+type=DerivedClockDomain
+clk_divider=3
+clk_domain=system.ruby.clk_domain
+
+[system.ruby.network]
+type=SimpleNetwork
+children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+adaptive_routing=false
+buffer_size=0
+clk_domain=system.ruby.clk_domain
+control_msg_size=8
+endpoint_bandwidth=1000
+ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+number_of_virtual_networks=10
+routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
+ruby_system=system.ruby
+topology=Crossbar
+
+[system.ruby.network.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l1_cntrl0
+int_node=system.ruby.network.routers0
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.l2_cntrl0
+int_node=system.ruby.network.routers1
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.ruby.dir_cntrl0
+int_node=system.ruby.network.routers2
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=3
+node_a=system.ruby.network.routers0
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=4
+node_a=system.ruby.network.routers1
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=5
+node_a=system.ruby.network.routers2
+node_b=system.ruby.network.routers3
+weight=1
+
+[system.ruby.network.routers0]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=0
+virt_nets=10
+
+[system.ruby.network.routers1]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=1
+virt_nets=10
+
+[system.ruby.network.routers2]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=2
+virt_nets=10
+
+[system.ruby.network.routers3]
+type=Switch
+clk_domain=system.ruby.clk_domain
+router_id=3
+virt_nets=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=1
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+clk_domain=system.clk_domain
+ruby_system=system.ruby
+support_data_reqs=true
+support_inst_reqs=true
+system=system
+using_network_tester=false
+using_ruby_tester=false
+version=0
+slave=system.system_port
+
+[system.tester]
+type=RubyTester
+check_flush=false
+checks_to_complete=100
+clk_domain=system.clk_domain
+deadlock_threshold=50000
+num_cpus=1
+system=system
+wakeup_frequency=10
+cpuDataPort=system.ruby.l1_cntrl0.sequencer.slave[0]
+cpuInstPort=system.ruby.l1_cntrl0.sequencer.slave[1]
+
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
--- /dev/null
+Real time: Sep/22/2013 05:27:12
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
+
+Virtual_time_in_seconds: 0.46
+Virtual_time_in_minutes: 0.00766667
+Virtual_time_in_hours: 0.000127778
+Virtual_time_in_days: 5.32407e-06
+
+Ruby_current_time: 318321
+Ruby_start_time: 0
+Ruby_cycles: 318321
+
+mbytes_resident: 65.1133
+mbytes_total: 120.422
+resident_ratio: 0.54071
+
+Busy Controller Counts:
+L1Cache-0:0
+L2Cache-0:0
+Directory-0:0
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1012 average: 15.8221 | standard deviation: 1.11991 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 61 937 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+latency: [binsize: 512 max: 8110 count: 997 average: 5056.15 | standard deviation: 2131.53 | 105 35 13 5 2 2 0 2 6 67 198 244 208 75 24 11 ]
+latency: LD: [binsize: 512 max: 7764 count: 44 average: 5504.89 | standard deviation: 1648.56 | 3 0 0 0 0 0 0 0 1 4 10 11 10 3 1 1 ]
+latency: ST: [binsize: 512 max: 8110 count: 897 average: 5296.67 | standard deviation: 1932.9 | 90 4 4 1 2 2 0 2 5 63 188 233 198 72 23 10 ]
+latency: IFETCH: [binsize: 128 max: 2021 count: 56 average: 850.893 | standard deviation: 421.128 | 0 1 4 7 3 15 11 2 1 0 4 4 0 3 0 1 ]
+hit latency: [binsize: 8 max: 117 count: 81 average: 19.5556 | standard deviation: 39.6538 | 68 0 0 0 0 0 0 0 0 0 0 0 2 6 5 ]
+hit latency: LD: [binsize: 1 max: 3 count: 2 average: 2 | standard deviation: 1.41421 | 0 1 0 1 ]
+hit latency: ST: [binsize: 8 max: 117 count: 79 average: 20 | standard deviation: 40.0577 | 66 0 0 0 0 0 0 0 0 0 0 0 2 6 5 ]
+miss latency: [binsize: 512 max: 8110 count: 916 average: 5501.52 | standard deviation: 1581.55 | 24 35 13 5 2 2 0 2 6 67 198 244 208 75 24 11 ]
+miss latency: LD: [binsize: 512 max: 7764 count: 42 average: 5766.93 | standard deviation: 1141.41 | 1 0 0 0 0 0 0 0 1 4 10 11 10 3 1 1 ]
+miss latency: ST: [binsize: 512 max: 8110 count: 818 average: 5806.28 | standard deviation: 1070 | 11 4 4 1 2 2 0 2 5 63 188 233 198 72 23 10 ]
+miss latency: IFETCH: [binsize: 128 max: 2021 count: 56 average: 850.893 | standard deviation: 421.128 | 0 1 4 7 3 15 11 2 1 0 4 4 0 3 0 1 ]
+
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 32 max: 1572 count: 7069 average: 39.9154 | standard deviation: 159.247 | 6421 15 38 124 13 11 58 12 11 21 23 10 10 30 13 21 26 16 8 26 17 12 9 25 16 4 10 11 7 8 1 4 2 4 7 1 2 4 1 2 2 1 1 4 2 0 0 3 1 1 ]
+ virtual_network_0_delay_cycles: [binsize: 32 max: 1572 count: 2530 average: 110.951 | standard deviation: 251.02 | 1882 15 38 124 13 11 58 12 11 21 23 10 10 30 13 21 26 16 8 26 17 12 9 25 16 4 10 11 7 8 1 4 2 4 7 1 2 4 1 2 2 1 1 4 2 0 0 3 1 1 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 3976 average: 0.342807 | standard deviation: 1.04899 | 3455 133 152 135 45 25 14 8 5 4 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 11 count: 563 average: 0.166963 | standard deviation: 0.907658 | 538 3 6 2 7 4 1 0 1 0 0 1 ]
+ virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+ virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
--- /dev/null
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+warn: rounding error > tolerance
+ 0.072760 rounded to 0
+hack: be nice to actually delete the event here
--- /dev/null
+Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:12
+gem5 executing on zizzer
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 318321 because Ruby Tester completed
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000318 # Number of seconds simulated
+sim_ticks 318321 # Number of ticks simulated
+final_tick 318321 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000 # Frequency of simulated ticks
+host_tick_rate 1986485 # Simulator tick rate (ticks/s)
+host_mem_usage 123316 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
+system.ruby.l1_cntrl0.L1Dcache.demand_hits 81 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_misses 861 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses 942 # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 # Number of cache demand accesses
+system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
+system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
+system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
+system.ruby.l1_cntrl0.prefetcher.prefetches_accepted 0 # number of prefetch requests accepted
+system.ruby.l1_cntrl0.prefetcher.dropped_prefetches 0 # number of prefetch requests dropped
+system.ruby.l1_cntrl0.prefetcher.hits 0 # number of prefetched blocks accessed
+system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
+system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
+system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
+system.ruby.network.routers0.percent_links_utilized 1.769362
+system.ruby.network.routers0.msg_count.Control::0 917
+system.ruby.network.routers0.msg_count.Request_Control::0 563
+system.ruby.network.routers0.msg_count.Response_Data::1 915
+system.ruby.network.routers0.msg_count.Response_Control::1 806
+system.ruby.network.routers0.msg_count.Response_Control::2 859
+system.ruby.network.routers0.msg_count.Writeback_Data::0 722
+system.ruby.network.routers0.msg_count.Writeback_Data::1 513
+system.ruby.network.routers0.msg_count.Writeback_Control::0 34
+system.ruby.network.routers0.msg_bytes.Control::0 7336
+system.ruby.network.routers0.msg_bytes.Request_Control::0 4504
+system.ruby.network.routers0.msg_bytes.Response_Data::1 65880
+system.ruby.network.routers0.msg_bytes.Response_Control::1 6448
+system.ruby.network.routers0.msg_bytes.Response_Control::2 6872
+system.ruby.network.routers0.msg_bytes.Writeback_Data::0 51984
+system.ruby.network.routers0.msg_bytes.Writeback_Data::1 36936
+system.ruby.network.routers0.msg_bytes.Writeback_Control::0 272
+system.ruby.l2_cntrl0.L2cache.demand_hits 43 # Number of cache demand hits
+system.ruby.l2_cntrl0.L2cache.demand_misses 874 # Number of cache demand misses
+system.ruby.l2_cntrl0.L2cache.demand_accesses 917 # Number of cache demand accesses
+system.ruby.network.routers1.percent_links_utilized 3.085407
+system.ruby.network.routers1.msg_count.Control::0 1791
+system.ruby.network.routers1.msg_count.Request_Control::0 563
+system.ruby.network.routers1.msg_count.Response_Data::1 2574
+system.ruby.network.routers1.msg_count.Response_Control::1 1759
+system.ruby.network.routers1.msg_count.Response_Control::2 858
+system.ruby.network.routers1.msg_count.Writeback_Data::0 722
+system.ruby.network.routers1.msg_count.Writeback_Data::1 513
+system.ruby.network.routers1.msg_count.Writeback_Control::0 34
+system.ruby.network.routers1.msg_bytes.Control::0 14328
+system.ruby.network.routers1.msg_bytes.Request_Control::0 4504
+system.ruby.network.routers1.msg_bytes.Response_Data::1 185328
+system.ruby.network.routers1.msg_bytes.Response_Control::1 14072
+system.ruby.network.routers1.msg_bytes.Response_Control::2 6864
+system.ruby.network.routers1.msg_bytes.Writeback_Data::0 51984
+system.ruby.network.routers1.msg_bytes.Writeback_Data::1 36936
+system.ruby.network.routers1.msg_bytes.Writeback_Control::0 272
+system.ruby.dir_cntrl0.memBuffer.memReq 1660 # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead 874 # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite 786 # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh 2210 # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles 555 # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ 44 # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls 601 # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.362048 # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy 169 # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy 188 # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 104 # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 64 # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait 30 # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount | 42 2.53% 2.53% | 51 3.07% 5.60% | 50 3.01% 8.61% | 73 4.40% 13.01% | 73 4.40% 17.41% | 71 4.28% 21.69% | 65 3.92% 25.60% | 49 2.95% 28.55% | 54 3.25% 31.81% | 41 2.47% 34.28% | 50 3.01% 37.29% | 44 2.65% 39.94% | 58 3.49% 43.43% | 48 2.89% 46.33% | 47 2.83% 49.16% | 63 3.80% 52.95% | 57 3.43% 56.39% | 47 2.83% 59.22% | 58 3.49% 62.71% | 57 3.43% 66.14% | 41 2.47% 68.61% | 49 2.95% 71.57% | 46 2.77% 74.34% | 49 2.95% 77.29% | 57 3.43% 80.72% | 45 2.71% 83.43% | 42 2.53% 85.96% | 49 2.95% 88.92% | 45 2.71% 91.63% | 53 3.19% 94.82% | 48 2.89% 97.71% | 38 2.29% 100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1660 # Number of accesses per bank
+
+system.ruby.network.routers2.percent_links_utilized 1.316910
+system.ruby.network.routers2.msg_count.Control::0 874
+system.ruby.network.routers2.msg_count.Response_Data::1 1660
+system.ruby.network.routers2.msg_count.Response_Control::1 954
+system.ruby.network.routers2.msg_bytes.Control::0 6992
+system.ruby.network.routers2.msg_bytes.Response_Data::1 119520
+system.ruby.network.routers2.msg_bytes.Response_Control::1 7632
+system.ruby.network.routers3.percent_links_utilized 2.057462
+system.ruby.network.routers3.msg_count.Control::0 1791
+system.ruby.network.routers3.msg_count.Request_Control::0 563
+system.ruby.network.routers3.msg_count.Response_Data::1 2575
+system.ruby.network.routers3.msg_count.Response_Control::1 1760
+system.ruby.network.routers3.msg_count.Response_Control::2 858
+system.ruby.network.routers3.msg_count.Writeback_Data::0 722
+system.ruby.network.routers3.msg_count.Writeback_Data::1 513
+system.ruby.network.routers3.msg_count.Writeback_Control::0 34
+system.ruby.network.routers3.msg_bytes.Control::0 14328
+system.ruby.network.routers3.msg_bytes.Request_Control::0 4504
+system.ruby.network.routers3.msg_bytes.Response_Data::1 185400
+system.ruby.network.routers3.msg_bytes.Response_Control::1 14080
+system.ruby.network.routers3.msg_bytes.Response_Control::2 6864
+system.ruby.network.routers3.msg_bytes.Writeback_Data::0 51984
+system.ruby.network.routers3.msg_bytes.Writeback_Data::1 36936
+system.ruby.network.routers3.msg_bytes.Writeback_Control::0 272
+system.ruby.network.msg_count.Control 5373
+system.ruby.network.msg_count.Request_Control 1689
+system.ruby.network.msg_count.Response_Data 7724
+system.ruby.network.msg_count.Response_Control 7854
+system.ruby.network.msg_count.Writeback_Data 3705
+system.ruby.network.msg_count.Writeback_Control 102
+system.ruby.network.msg_byte.Control 42984
+system.ruby.network.msg_byte.Request_Control 13512
+system.ruby.network.msg_byte.Response_Data 556128
+system.ruby.network.msg_byte.Response_Control 62832
+system.ruby.network.msg_byte.Writeback_Data 266760
+system.ruby.network.msg_byte.Writeback_Control 816
+system.ruby.network.routers0.throttle0.link_utilization 1.500686
+system.ruby.network.routers0.throttle0.msg_count.Request_Control::0 563
+system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 915
+system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 756
+system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::0 4504
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 65880
+system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6048
+system.ruby.network.routers0.throttle1.link_utilization 2.038037
+system.ruby.network.routers0.throttle1.msg_count.Control::0 917
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 50
+system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 859
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 722
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 513
+system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 34
+system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7336
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 400
+system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6872
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 51984
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 36936
+system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 272
+system.ruby.network.routers1.throttle0.link_utilization 3.408509
+system.ruby.network.routers1.throttle0.msg_count.Control::0 917
+system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 873
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 919
+system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 858
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 722
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 513
+system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 34
+system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7336
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62856
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7352
+system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6864
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 51984
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 36936
+system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 272
+system.ruby.network.routers1.throttle1.link_utilization 2.762306
+system.ruby.network.routers1.throttle1.msg_count.Control::0 874
+system.ruby.network.routers1.throttle1.msg_count.Request_Control::0 563
+system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1701
+system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 840
+system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6992
+system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::0 4504
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 122472
+system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6720
+system.ruby.network.routers2.throttle0.link_utilization 1.261620
+system.ruby.network.routers2.throttle0.msg_count.Control::0 874
+system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 786
+system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 84
+system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6992
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 56592
+system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 672
+system.ruby.network.routers2.throttle1.link_utilization 1.372200
+system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 874
+system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 870
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62928
+system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6960
+system.ruby.network.routers3.throttle0.link_utilization 1.500686
+system.ruby.network.routers3.throttle0.msg_count.Request_Control::0 563
+system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 915
+system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 756
+system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::0 4504
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 65880
+system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6048
+system.ruby.network.routers3.throttle1.link_utilization 3.410080
+system.ruby.network.routers3.throttle1.msg_count.Control::0 917
+system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 874
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 920
+system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 858
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 722
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 513
+system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 34
+system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7336
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62928
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7360
+system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6864
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 51984
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 36936
+system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 272
+system.ruby.network.routers3.throttle2.link_utilization 1.261620
+system.ruby.network.routers3.throttle2.msg_count.Control::0 874
+system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 786
+system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 84
+system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6992
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 56592
+system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 672
+system.ruby.l1_cntrl0.Load 44 0.00% 0.00%
+system.ruby.l1_cntrl0.Ifetch 67 0.00% 0.00%
+system.ruby.l1_cntrl0.Store 898 0.00% 0.00%
+system.ruby.l1_cntrl0.Inv 563 0.00% 0.00%
+system.ruby.l1_cntrl0.L1_Replacement 10398 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_Exclusive 41 0.00% 0.00%
+system.ruby.l1_cntrl0.Data_all_Acks 874 0.00% 0.00%
+system.ruby.l1_cntrl0.Ack_all 1 0.00% 0.00%
+system.ruby.l1_cntrl0.WB_Ack 755 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Load 42 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Ifetch 56 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Store 818 0.00% 0.00%
+system.ruby.l1_cntrl0.NP.Inv 1 0.00% 0.00%
+system.ruby.l1_cntrl0.I.L1_Replacement 145 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Store 1 0.00% 0.00%
+system.ruby.l1_cntrl0.S.Inv 31 0.00% 0.00%
+system.ruby.l1_cntrl0.S.L1_Replacement 11 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Store 2 0.00% 0.00%
+system.ruby.l1_cntrl0.E.Inv 4 0.00% 0.00%
+system.ruby.l1_cntrl0.E.L1_Replacement 34 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Load 2 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Store 77 0.00% 0.00%
+system.ruby.l1_cntrl0.M.Inv 97 0.00% 0.00%
+system.ruby.l1_cntrl0.M.L1_Replacement 722 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Inv 14 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.L1_Replacement 374 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_Exclusive 41 0.00% 0.00%
+system.ruby.l1_cntrl0.IS.Data_all_Acks 43 0.00% 0.00%
+system.ruby.l1_cntrl0.IM.L1_Replacement 9112 0.00% 0.00%
+system.ruby.l1_cntrl0.IM.Data_all_Acks 817 0.00% 0.00%
+system.ruby.l1_cntrl0.SM.Ack_all 1 0.00% 0.00%
+system.ruby.l1_cntrl0.IS_I.Data_all_Acks 14 0.00% 0.00%
+system.ruby.l1_cntrl0.M_I.Ifetch 10 0.00% 0.00%
+system.ruby.l1_cntrl0.M_I.Inv 416 0.00% 0.00%
+system.ruby.l1_cntrl0.M_I.WB_Ack 340 0.00% 0.00%
+system.ruby.l1_cntrl0.SINK_WB_ACK.Ifetch 1 0.00% 0.00%
+system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack 415 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GET_INSTR 56 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETS 42 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_GETX 818 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_UPGRADE 1 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX 345 0.00% 0.00%
+system.ruby.l2_cntrl0.L1_PUTX_old 796 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement 291 0.00% 0.00%
+system.ruby.l2_cntrl0.L2_Replacement_clean 1216 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Data 873 0.00% 0.00%
+system.ruby.l2_cntrl0.Mem_Ack 869 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data 495 0.00% 0.00%
+system.ruby.l2_cntrl0.WB_Data_clean 18 0.00% 0.00%
+system.ruby.l2_cntrl0.Ack_all 50 0.00% 0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock 858 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GET_INSTR 46 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS 41 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX 787 0.00% 0.00%
+system.ruby.l2_cntrl0.NP.L1_PUTX_old 302 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GETS 1 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_GETX 9 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L1_UPGRADE 1 0.00% 0.00%
+system.ruby.l2_cntrl0.SS.L2_Replacement_clean 46 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GET_INSTR 10 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L1_GETX 22 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement 291 0.00% 0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement_clean 16 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L1_PUTX 340 0.00% 0.00%
+system.ruby.l2_cntrl0.MT.L2_Replacement_clean 517 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.L1_PUTX_old 113 0.00% 0.00%
+system.ruby.l2_cntrl0.M_I.Mem_Ack 869 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.L1_PUTX_old 210 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data 495 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.WB_Data_clean 18 0.00% 0.00%
+system.ruby.l2_cntrl0.MCT_I.Ack_all 4 0.00% 0.00%
+system.ruby.l2_cntrl0.I_I.Ack_all 46 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.L2_Replacement_clean 11 0.00% 0.00%
+system.ruby.l2_cntrl0.ISS.Mem_Data 41 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.L2_Replacement_clean 57 0.00% 0.00%
+system.ruby.l2_cntrl0.IS.Mem_Data 46 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.L2_Replacement_clean 219 0.00% 0.00%
+system.ruby.l2_cntrl0.IM.Mem_Data 786 0.00% 0.00%
+system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 10 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_PUTX 5 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L1_PUTX_old 171 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.L2_Replacement_clean 350 0.00% 0.00%
+system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 848 0.00% 0.00%
+system.ruby.dir_cntrl0.Fetch 874 0.00% 0.00%
+system.ruby.dir_cntrl0.Data 786 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Data 874 0.00% 0.00%
+system.ruby.dir_cntrl0.Memory_Ack 786 0.00% 0.00%
+system.ruby.dir_cntrl0.CleanReplacement 84 0.00% 0.00%
+system.ruby.dir_cntrl0.I.Fetch 874 0.00% 0.00%
+system.ruby.dir_cntrl0.M.Data 786 0.00% 0.00%
+system.ruby.dir_cntrl0.M.CleanReplacement 84 0.00% 0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data 874 0.00% 0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack 786 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
help='echo commands before executing')
add_option('--builds',
default='ALPHA,ALPHA_MOESI_hammer,' \
- 'ALPHA_MESI_CMP_directory,' \
+ 'ALPHA_MESI_Two_Level,' \
'ALPHA_MOESI_CMP_directory,' \
'ALPHA_MOESI_CMP_token,' \
'MIPS,' \
'NULL,' \
'POWER,' \
'SPARC,' \
- 'X86,X86_MESI_CMP_directory,' \
+ 'X86,X86_MESI_Two_Level,' \
'ARM',
help="comma-separated build targets to test (default: '%default')")
add_option('--modes',
projects / gem5.git / commitdiff