// write_o_buffer(0);
if (!box_list.empty() || !ff_bits.empty()) {
- RTLIL::Module *holes_module = module->design->addModule("$__holes__");
+ RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str()));
log_assert(holes_module);
dict<IdString, Cell*> cell_cache;
- int port_id = 1;
int box_count = 0;
for (auto cell : box_list) {
- RTLIL::Module* orig_box_module = module->design->module(cell->type);
- log_assert(orig_box_module);
- IdString derived_name = orig_box_module->derive(module->design, cell->parameters);
- RTLIL::Module* box_module = module->design->module(derived_name);
- if (box_module->has_processes())
- Pass::call_on_module(module->design, box_module, "proc");
-
- auto r = cell_cache.insert(std::make_pair(derived_name, nullptr));
- Cell *holes_cell = r.first->second;
- if (r.second && box_module->get_bool_attribute("\\whitebox")) {
- holes_cell = holes_module->addCell(cell->name, cell->type);
- holes_cell->parameters = cell->parameters;
- r.first->second = holes_cell;
- }
+ RTLIL::Module* box_module = module->design->module(cell->type);
+ log_assert(box_module);
int box_inputs = 0, box_outputs = 0;
- for (auto port_name : box_ports.at(cell->type)) {
+ for (auto port_name : box_module->ports) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
- RTLIL::Wire *holes_wire;
- RTLIL::SigSpec port_sig;
-
if (w->port_input)
- for (int i = 0; i < GetSize(w); i++) {
- box_inputs++;
- holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
- if (!holes_wire) {
- holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
- holes_wire->port_input = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- }
- if (holes_cell)
- port_sig.append(holes_wire);
- }
- if (w->port_output) {
+ box_inputs += GetSize(w);
+ if (w->port_output)
box_outputs += GetSize(w);
- for (int i = 0; i < GetSize(w); i++) {
- if (GetSize(w) == 1)
- holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
- else
- holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
- holes_wire->port_output = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- if (holes_cell)
- port_sig.append(holes_wire);
- else
- holes_module->connect(holes_wire, State::S0);
- }
- }
- if (!port_sig.empty()) {
- if (r.second)
- holes_cell->setPort(w->name, port_sig);
- else
- holes_module->connect(holes_cell->getPort(w->name), port_sig);
- }
}
// For flops only, create an extra 1-bit input that drives a new wire
// called "<cell>.abc9_ff.Q" that is used below
- if (box_module->get_bool_attribute("\\abc9_flop")) {
- log_assert(holes_cell);
-
+ if (box_module->get_bool_attribute("\\abc9_flop"))
box_inputs++;
- Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
- if (!holes_wire) {
- holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
- holes_wire->port_input = true;
- holes_wire->port_id = port_id++;
- holes_module->ports.push_back(holes_wire->name);
- }
- Wire *w = holes_module->addWire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
- log_assert(w);
- holes_module->connect(w, holes_wire);
- }
write_h_buffer(box_inputs);
write_h_buffer(box_outputs);
// Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
// since boxes may contain parameters in which case `flatten` would have
// created a new $paramod ...
+ Pass::call_on_module(holes_module->design, holes_module, "wbflip");
Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
dict<SigSig, SigSig> replace;
// Fully pad all unused input connections of this box cell with S0
// Fully pad all undriven output connections of this box cell with anonymous wires
- // NB: Assume box_module->ports are sorted alphabetically
- // (as RTLIL::Module::fixup_ports() would do)
for (const auto &port_name : box_module->ports) {
RTLIL::Wire* w = box_module->wire(port_name);
log_assert(w);
holes_module->set_bool_attribute("\\abc9_holes");
dict<IdString, Cell*> cell_cache;
+ dict<IdString, std::vector<IdString>> box_ports;
int port_id = 1;
for (auto cell : box_list) {
holes_cell = holes_module->addCell(cell->name, cell->type);
holes_cell->parameters = cell->parameters;
r.first->second = holes_cell;
+ }
- // Since Module::derive() will create a new module, there
- // is a chance that the ports will be alphabetically ordered
- // again, which is a problem when carry-chains are involved.
- // Inherit the port ordering from the original module here...
- // (and set the port_id below, when iterating through those)
- log_assert(GetSize(box_module->ports) == GetSize(orig_box_module->ports));
- box_module->ports = orig_box_module->ports;
+ auto r2 = box_ports.insert(cell->type);
+ if (r2.second) {
+ // Make carry in the last PI, and carry out the last PO
+ // since ABC requires it this way
+ IdString carry_in, carry_out;
+ for (const auto &port_name : box_module->ports) {
+ auto w = box_module->wire(port_name);
+ log_assert(w);
+ if (w->get_bool_attribute("\\abc9_carry")) {
+ if (w->port_input) {
+ if (carry_in != IdString())
+ log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
+ carry_in = port_name;
+ }
+ if (w->port_output) {
+ if (carry_out != IdString())
+ log_error("Module '%s' contains more than one 'abc9_carry' output port.\n", log_id(box_module));
+ carry_out = port_name;
+ }
+ }
+ else
+ r2.first->second.push_back(port_name);
+ }
+
+ if (carry_in != IdString() && carry_out == IdString())
+ log_error("Module '%s' contains an 'abc9_carry' input port but no output port.\n", log_id(box_module));
+ if (carry_in == IdString() && carry_out != IdString())
+ log_error("Module '%s' contains an 'abc9_carry' output port but no input port.\n", log_id(box_module));
+ if (carry_in != IdString()) {
+ r2.first->second.push_back(carry_in);
+ r2.first->second.push_back(carry_out);
+ }
}
// NB: Assume box_module->ports are sorted alphabetically
// (as RTLIL::Module::fixup_ports() would do)
- int box_port_id = 1;
- for (const auto &port_name : box_module->ports) {
+ for (const auto &port_name : box_ports.at(cell->type)) {
RTLIL::Wire *w = box_module->wire(port_name);
log_assert(w);
- if (r.second)
- w->port_id = box_port_id++;
RTLIL::Wire *holes_wire;
RTLIL::SigSpec port_sig;
if (w->port_input)
projects / yosys.git / commitdiff