X86: Plug in an IDE controller.

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 8ffd69a4047ec7f2de66af622aeb44701c54a281..45fdc80a16a287504100ba23e32440ddd378c143 100644 (file)
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -284,7 +284,7 @@ def makeLinuxX86System(mem_mode, mdesc = None):
 
     # Command line
     self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=9608015 ' + \
-                        'ide0=noprobe ide1=noprobe ' + \
+                        'ide1=noprobe ' + \
                         'ide2=noprobe ide3=noprobe ' + \
                         'ide4=noprobe ide5=noprobe'
     return self

diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 7211fa3f488e958f96b6d09b617d8a38f5437d20..6f315cbcba4461e6a9bf0b489a2938c5a1e186de 100644 (file)
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -67,7 +67,7 @@ class Pc(Platform):
     fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8)
 
     # A device to catch accesses to the non-existant floppy controller.
-    fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=4)
+    fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
 
     def attachIO(self, bus):
         self.south_bridge.attachIO(bus)

diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index a3db83610befb26b85710c896274bf9ff2911e77..be927614536749fc69a657022e75e36750b8876c 100644 (file)
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -34,6 +34,7 @@ from I82094AA import I82094AA
 from I8237 import I8237
 from I8254 import I8254
 from I8259 import I8259
+from Ide import IdeController
 from PcSpeaker import PcSpeaker
 from X86IntPin import X86IntLine
 from m5.SimObject import SimObject
@@ -72,6 +73,21 @@ class SouthBridge(SimObject):
     def connectPins(self, source, sink):
         self.int_lines.append(X86IntLine(source=source, sink=sink))
 
+    # IDE controller
+    ide = IdeController(disks=[], pci_func=0, pci_dev=4, pci_bus=0)
+    ide.BAR0 = 0x1f0
+    ide.BAR0LegacyIO = True
+    ide.BAR1 = 0x3f4
+    ide.BAR1Size = '3B'
+    ide.BAR1LegacyIO = True
+    ide.BAR2 = 0x170
+    ide.BAR2LegacyIO = True
+    ide.BAR3 = 0x374
+    ide.BAR3Size = '3B'
+    ide.BAR3LegacyIO = True
+    ide.BAR4 = 1
+    ide.Command = 1
+
     def attachIO(self, bus):
         # Route interupt signals
         self.connectPins(self.pic1.output, self.io_apic.pin(0))
@@ -94,6 +110,7 @@ class SouthBridge(SimObject):
         # Connect to the bus
         self.cmos.pio = bus.port
         self.dma1.pio = bus.port
+        self.ide.pio = bus.port
         self.keyboard.pio = bus.port
         self.pic1.pio = bus.port
         self.pic2.pio = bus.port