Use log in decoder/*

diff --git a/src/openpower/decoder/decode2execute1.py b/src/openpower/decoder/decode2execute1.py
index 628f2d475047a2e2310750b5c2dc431d0a768375..cd012f6fa58f6ba9012f54df84adea618fe6a437 100644 (file)
--- a/src/openpower/decoder/decode2execute1.py
+++ b/src/openpower/decoder/decode2execute1.py
@@ -11,6 +11,7 @@ from openpower.consts import TT
 from openpower.exceptions import LDSTException
 from openpower.decoder.power_svp64_rm import sv_input_record_layout
 
+from openpower.util import log
 
 class Data(Record):
 
@@ -128,7 +129,7 @@ class Decode2ToExecute1Type(RecordObject):
         self.write_cr = Data(7, name="cr_out")
 
         # decode operand data
-        print ("decode2execute init", name, opkls, do)
+        log ("decode2execute init", name, opkls, do)
         #assert name is not None, str(opkls)
         if do is not None:
             self.do = do

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 2ac2e468daf47840fbbd1bd71769deb9fca1b5ad..d53c06762a7ebce59983c4d0972dd715a90346a3 100644 (file)
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -101,6 +101,8 @@ from openpower.decoder.power_fields import DecodeFields
 from openpower.decoder.power_fieldsn import SigDecode, SignalBitRange
 from openpower.decoder.power_svp64 import SVP64RM
 
+from openpower.util import log
+
 # key data structure in which the POWER decoder is specified,
 # in a hierarchical fashion
 Subdecoder = namedtuple(  # fix autoformatter
@@ -210,12 +212,12 @@ class PowerOp:
             if row['CR in'] == '1':
                 import pdb
                 pdb.set_trace()
-                print(row)
+                log(row)
             if row['CR out'] == '0':
                 import pdb
                 pdb.set_trace()
-                print(row)
-            print(row)
+                log(row)
+            log(row)
         ldst_mode = row['upd']
         if ldst_mode.isdigit():
             row['upd'] = int(ldst_mode)
@@ -234,12 +236,12 @@ class PowerOp:
                 val = ptype[val]
             res.append(getattr(self, field).eq(val))
         if False:
-            print(row.keys())
+            log(row.keys())
         asmcode = row['comment']
         # process the comment field, strip out "equals" for FP
         if "=" in asmcode:
             asmcode = asmcode.split("=")[-1]
-            print ("asmcode stripping =", asmcode,
+            log ("asmcode stripping =", asmcode,
                     asmcode in asmidx, hasattr(self, "asmcode"))
         if hasattr(self, "asmcode") and asmcode in asmidx:
             res.append(self.asmcode.eq(asmidx[asmcode]))
@@ -429,9 +431,9 @@ class PowerDecoder(Elaboratable):
                                           name=mname,
                                           col_subset=self.col_subset,
                                           row_subset=self.row_subsetfn)
-                print ("subdecoder", mname, subdecoder)
+                log ("subdecoder", mname, subdecoder)
                 if not subdecoder.tree_analyse():  # doesn't do anything
-                    print ("analysed, DELETING", mname)
+                    log ("analysed, DELETING", mname)
                     del subdecoder
                     continue                      # skip
                 submodules[mname] = subdecoder
@@ -547,7 +549,7 @@ def create_pdecode(name=None, col_subset=None, row_subset=None,
 
     subsetting of the PowerOp decoding is possible by setting col_subset
     """
-    print ("create_pdecode", name, col_subset, row_subset, include_fp)
+    log ("create_pdecode", name, col_subset, row_subset, include_fp)
 
     # some alteration to the CSV files is required for SV so we use
     # a class to do it
@@ -612,7 +614,7 @@ if __name__ == '__main__':
         # row subset
 
         def rowsubsetfn(opcode, row):
-            print("row_subset", opcode, row)
+            log("row_subset", opcode, row)
             return row['unit'] == 'FPU'
 
         pdecode = create_pdecode(name="rowsub",

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index f54bd107150a5cd949a3cd9f6e758d35e48e29e6..3133c52cfd5c2756220b539c5d14782b01751744 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -38,7 +38,7 @@ from openpower.consts import (MSR, SPEC, EXTRA2, EXTRA3, SVP64P, field,
                               FastRegsEnum, XERRegsEnum, TT)
 
 from openpower.state import CoreState
-from openpower.util import spr_to_fast
+from openpower.util import (spr_to_fast, log)
 
 
 def decode_spr_num(spr):
@@ -774,7 +774,7 @@ class PowerDecodeSubset(Elaboratable):
         for k, v in record_names.items():
             if hasattr(do, k):
                 subset.add(v)
-        print ("get_col_subset", self.fn_name, do.fields, subset)
+        log ("get_col_subset", self.fn_name, do.fields, subset)
         return subset
 
     def rowsubsetfn(self, opcode, row):
@@ -1409,7 +1409,7 @@ def get_rdflags(e, cu):
         regfile, regname, _ = cu.get_in_spec(idx)
         rdflag, read = regspec_decode_read(e, regfile, regname)
         rdl.append(rdflag)
-    print("rdflags", rdl)
+    log("rdflags", rdl)
     return Cat(*rdl)