+2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * machmode.h (mode_precision): Change from unsigned short to
+ poly_uint16_pod.
+ (mode_to_precision): Return a poly_uint16 rather than an unsigned
+ short.
+ (GET_MODE_PRECISION): Return a constant if ONLY_FIXED_SIZE_MODES,
+ or if measurement_type is not polynomial.
+ (HWI_COMPUTABLE_MODE_P): Turn into a function. Optimize the case
+ in which the mode is already known to be a scalar_int_mode.
+ * genmodes.c (emit_mode_precision): Change the type of mode_precision
+ from unsigned short to poly_uint16_pod. Use ZERO_COEFFS for the
+ initializer.
+ * lto-streamer-in.c (lto_input_mode_table): Use bp_unpack_poly_value
+ for GET_MODE_PRECISION.
+ * lto-streamer-out.c (lto_write_mode_table): Use bp_pack_poly_value
+ for GET_MODE_PRECISION.
+ * combine.c (update_rsp_from_reg_equal): Treat GET_MODE_PRECISION
+ as polynomial.
+ (try_combine, find_split_point, combine_simplify_rtx): Likewise.
+ (expand_field_assignment, make_extraction): Likewise.
+ (make_compound_operation_int, record_dead_and_set_regs_1): Likewise.
+ (get_last_value): Likewise.
+ * convert.c (convert_to_integer_1): Likewise.
+ * cse.c (cse_insn): Likewise.
+ * expr.c (expand_expr_real_1): Likewise.
+ * lra-constraints.c (simplify_operand_subreg): Likewise.
+ * optabs-query.c (can_atomic_load_p): Likewise.
+ * optabs.c (expand_atomic_load): Likewise.
+ (expand_atomic_store): Likewise.
+ * ree.c (combine_reaching_defs): Likewise.
+ * rtl.h (partial_subreg_p, paradoxical_subreg_p): Likewise.
+ * rtlanal.c (nonzero_bits1, lsb_bitfield_op_p): Likewise.
+ * tree.h (type_has_mode_precision_p): Likewise.
+ * ubsan.c (instrument_si_overflow): Likewise.
+
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
+2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
+ Alan Hayward <alan.hayward@arm.com>
+ David Sherwood <david.sherwood@arm.com>
+
+ * gcc-interface/misc.c (enumerate_modes): Treat GET_MODE_PRECISION
+ as polynomial.
+
2018-01-03 Richard Sandiford <richard.sandiford@linaro.org>
Alan Hayward <alan.hayward@arm.com>
David Sherwood <david.sherwood@arm.com>
}
/* If no predefined C types were found, register the mode itself. */
- int nunits;
- if (!skip_p && GET_MODE_NUNITS (i).is_constant (&nunits))
+ int nunits, precision;
+ if (!skip_p
+ && GET_MODE_NUNITS (i).is_constant (&nunits)
+ && GET_MODE_PRECISION (i).is_constant (&precision))
f (GET_MODE_NAME (i), digs, complex_p,
vector_p ? nunits : 0, float_rep,
- GET_MODE_PRECISION (i), GET_MODE_BITSIZE (i),
+ precision, GET_MODE_BITSIZE (i),
GET_MODE_ALIGNMENT (i));
}
}
if (rsp->sign_bit_copies != 1)
{
num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
- if (reg_equal && num != GET_MODE_PRECISION (GET_MODE (x)))
+ if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
{
unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
if (num == 0 || numeq > num)
&& ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
(REG_P (temp_expr)
&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
- && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
- && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
+ && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
+ BITS_PER_WORD)
+ && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
+ HOST_BITS_PER_INT)
&& (reg_stat[REGNO (temp_expr)].nonzero_bits
!= GET_MODE_MASK (word_mode))))
&& ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
&& (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
(REG_P (temp_expr)
&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
- && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
- && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
+ && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
+ BITS_PER_WORD)
+ && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
+ HOST_BITS_PER_INT)
&& (reg_stat[REGNO (temp_expr)].nonzero_bits
!= GET_MODE_MASK (word_mode)))))
&& ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
break;
}
- if (len && pos >= 0
- && pos + len <= GET_MODE_PRECISION (GET_MODE (inner))
+ if (len
+ && known_subrange_p (pos, len,
+ 0, GET_MODE_PRECISION (GET_MODE (inner)))
&& is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
{
/* For unsigned, we have a choice of a shift followed by an
&& (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
== (HOST_WIDE_INT_1U << (i + 1)) - 1))
|| (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
- && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
- == (unsigned int) i + 1))))
+ && known_eq ((GET_MODE_PRECISION
+ (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
+ (unsigned int) i + 1))))
return simplify_shift_const
(NULL_RTX, ASHIFTRT, int_mode,
simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
{
rtx inner;
rtx pos; /* Always counts from low bit. */
- int len;
+ int len, inner_len;
rtx mask, cleared, masked;
scalar_int_mode compute_mode;
if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
&& GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
{
+ rtx x0 = XEXP (SET_DEST (x), 0);
+ if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
+ break;
inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
- len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
MAX_MODE_INT);
}
&& CONST_INT_P (XEXP (SET_DEST (x), 1)))
{
inner = XEXP (SET_DEST (x), 0);
+ if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
+ break;
+
len = INTVAL (XEXP (SET_DEST (x), 1));
pos = XEXP (SET_DEST (x), 2);
/* A constant position should stay within the width of INNER. */
- if (CONST_INT_P (pos)
- && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
+ if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
break;
if (BITS_BIG_ENDIAN)
{
if (CONST_INT_P (pos))
- pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
- - INTVAL (pos));
+ pos = GEN_INT (inner_len - len - INTVAL (pos));
else if (GET_CODE (pos) == MINUS
&& CONST_INT_P (XEXP (pos, 1))
- && (INTVAL (XEXP (pos, 1))
- == GET_MODE_PRECISION (GET_MODE (inner)) - len))
+ && INTVAL (XEXP (pos, 1)) == inner_len - len)
/* If position is ADJUST - X, new position is X. */
pos = XEXP (pos, 0);
else
- {
- HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
- pos = simplify_gen_binary (MINUS, GET_MODE (pos),
- gen_int_mode (prec - len,
- GET_MODE (pos)),
- pos);
- }
+ pos = simplify_gen_binary (MINUS, GET_MODE (pos),
+ gen_int_mode (inner_len - len,
+ GET_MODE (pos)),
+ pos);
}
}
bits outside of is_mode, don't look through
non-paradoxical SUBREGs. See PR82192. */
|| (pos_rtx == NULL_RTX
- && pos + len <= GET_MODE_PRECISION (is_mode))))
+ && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
{
/* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
consider just the QI as the memory to extract from.
bits outside of is_mode, don't look through
TRUNCATE. See PR82192. */
&& pos_rtx == NULL_RTX
- && pos + len <= GET_MODE_PRECISION (is_mode))
+ && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
inner = XEXP (inner, 0);
inner_mode = GET_MODE (inner);
if (MEM_P (inner))
{
- HOST_WIDE_INT offset;
+ poly_int64 offset;
/* POS counts from lsb, but make OFFSET count in memory order. */
if (BYTES_BIG_ENDIAN)
- offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
+ offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
+ - len - pos);
else
offset = pos / BITS_PER_UNIT;
other cases, we would only be going outside our object in cases when
an original shift would have been undefined. */
if (MEM_P (inner)
- && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
+ && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
|| (pos_rtx != 0 && len != 1)))
return 0;
sub = XEXP (XEXP (x, 0), 0);
machine_mode sub_mode = GET_MODE (sub);
+ int sub_width;
if ((REG_P (sub) || MEM_P (sub))
- && GET_MODE_PRECISION (sub_mode) < mode_width)
+ && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
+ && sub_width < mode_width)
{
unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
unsigned HOST_WIDE_INT mask;
if ((mask & mode_mask) == mode_mask)
{
new_rtx = make_compound_operation (sub, next_code);
- new_rtx = make_extraction (mode, new_rtx, 0, 0,
- GET_MODE_PRECISION (sub_mode),
+ new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
1, 0, in_code == COMPARE);
}
}
else if (GET_CODE (setter) == SET
&& GET_CODE (SET_DEST (setter)) == SUBREG
&& SUBREG_REG (SET_DEST (setter)) == dest
- && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
+ && known_le (GET_MODE_PRECISION (GET_MODE (dest)), BITS_PER_WORD)
&& subreg_lowpart_p (SET_DEST (setter)))
record_value_for_reg (dest, record_dead_insn,
gen_lowpart (GET_MODE (dest),
/* If fewer bits were set than what we are asked for now, we cannot use
the value. */
- if (GET_MODE_PRECISION (rsp->last_set_mode)
- < GET_MODE_PRECISION (GET_MODE (x)))
+ if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
+ GET_MODE_PRECISION (GET_MODE (x))))
return 0;
/* If the value has all its registers valid, return it. */
type corresponding to its mode, then do a nop conversion
to TYPE. */
else if (TREE_CODE (type) == ENUMERAL_TYPE
- || outprec != GET_MODE_PRECISION (TYPE_MODE (type)))
+ || maybe_ne (outprec, GET_MODE_PRECISION (TYPE_MODE (type))))
{
expr = convert (lang_hooks.types.type_for_mode
(TYPE_MODE (type), TYPE_UNSIGNED (type)), expr);
&& CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 1))
&& CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 2))
&& REG_P (XEXP (SET_DEST (sets[i].rtl), 0))
- && (GET_MODE_PRECISION (GET_MODE (SET_DEST (sets[i].rtl)))
- >= INTVAL (XEXP (SET_DEST (sets[i].rtl), 1)))
+ && (known_ge
+ (GET_MODE_PRECISION (GET_MODE (SET_DEST (sets[i].rtl))),
+ INTVAL (XEXP (SET_DEST (sets[i].rtl), 1))))
&& ((unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 1))
+ (unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 2))
<= HOST_BITS_PER_WIDE_INT))
;
/* If neither mode is BLKmode, and both modes are the same size
then we can use gen_lowpart. */
- else if (mode != BLKmode && GET_MODE (op0) != BLKmode
- && (GET_MODE_PRECISION (mode)
- == GET_MODE_PRECISION (GET_MODE (op0)))
+ else if (mode != BLKmode
+ && GET_MODE (op0) != BLKmode
+ && known_eq (GET_MODE_PRECISION (mode),
+ GET_MODE_PRECISION (GET_MODE (op0)))
&& !COMPLEX_MODE_P (GET_MODE (op0)))
{
if (GET_CODE (op0) == SUBREG)
int c;
struct mode_data *m;
- print_decl ("unsigned short", "mode_precision", "NUM_MACHINE_MODES");
+ print_decl ("poly_uint16_pod", "mode_precision", "NUM_MACHINE_MODES");
for_all_modes (c, m)
if (m->precision != (unsigned int)-1)
- tagged_printf ("%u", m->precision, m->name);
+ tagged_printf ("{ %u" ZERO_COEFFS " }", m->precision, m->name);
else
- tagged_printf ("%u*BITS_PER_UNIT", m->bytesize, m->name);
+ tagged_printf ("{ %u * BITS_PER_UNIT" ZERO_COEFFS " }",
+ m->bytesize, m->name);
print_closer ();
}
missing important data from memory when the inner is wider than
outer. This rule only applies to modes that are no wider than
a word. */
- if (!(GET_MODE_PRECISION (mode) != GET_MODE_PRECISION (innermode)
+ if (!(maybe_ne (GET_MODE_PRECISION (mode),
+ GET_MODE_PRECISION (innermode))
&& GET_MODE_SIZE (mode) <= UNITS_PER_WORD
&& GET_MODE_SIZE (innermode) <= UNITS_PER_WORD
&& WORD_REGISTER_OPERATIONS)
enum mode_class mclass
= bp_unpack_enum (&bp, mode_class, MAX_MODE_CLASS);
unsigned int size = bp_unpack_value (&bp, 8);
- unsigned int prec = bp_unpack_value (&bp, 16);
+ poly_uint16 prec = bp_unpack_poly_value (&bp, 16);
machine_mode inner = (machine_mode) bp_unpack_value (&bp, 8);
poly_uint16 nunits = bp_unpack_poly_value (&bp, 16);
unsigned int ibit = 0, fbit = 0;
: mr = GET_MODE_WIDER_MODE (mr).else_void ())
if (GET_MODE_CLASS (mr) != mclass
|| GET_MODE_SIZE (mr) != size
- || GET_MODE_PRECISION (mr) != prec
+ || maybe_ne (GET_MODE_PRECISION (mr), prec)
|| (inner == m
? GET_MODE_INNER (mr) != mr
: GET_MODE_INNER (mr) != table[(int) inner])
bp_pack_value (&bp, m, 8);
bp_pack_enum (&bp, mode_class, MAX_MODE_CLASS, GET_MODE_CLASS (m));
bp_pack_value (&bp, GET_MODE_SIZE (m), 8);
- bp_pack_value (&bp, GET_MODE_PRECISION (m), 16);
+ bp_pack_poly_value (&bp, GET_MODE_PRECISION (m), 16);
bp_pack_value (&bp, GET_MODE_INNER (m), 8);
bp_pack_poly_value (&bp, GET_MODE_NUNITS (m), 16);
switch (GET_MODE_CLASS (m))
typedef opt_mode<machine_mode> opt_machine_mode;
extern CONST_MODE_SIZE unsigned short mode_size[NUM_MACHINE_MODES];
-extern const unsigned short mode_precision[NUM_MACHINE_MODES];
+extern const poly_uint16_pod mode_precision[NUM_MACHINE_MODES];
extern const unsigned char mode_inner[NUM_MACHINE_MODES];
extern const poly_uint16_pod mode_nunits[NUM_MACHINE_MODES];
extern CONST_MODE_UNIT_SIZE unsigned char mode_unit_size[NUM_MACHINE_MODES];
/* Return the base GET_MODE_PRECISION value for MODE. */
-ALWAYS_INLINE unsigned short
+ALWAYS_INLINE poly_uint16
mode_to_precision (machine_mode mode)
{
return mode_precision[mode];
/* Get the number of value bits of an object of mode MODE. */
-#define GET_MODE_PRECISION(MODE) (mode_to_precision (MODE))
+#if ONLY_FIXED_SIZE_MODES
+#define GET_MODE_PRECISION(MODE) \
+ ((unsigned short) mode_to_precision (MODE).coeffs[0])
+#else
+ALWAYS_INLINE poly_uint16
+GET_MODE_PRECISION (machine_mode mode)
+{
+ return mode_to_precision (mode);
+}
+
+template<typename T>
+ALWAYS_INLINE typename if_poly<typename T::measurement_type>::type
+GET_MODE_PRECISION (const T &mode)
+{
+ return mode_to_precision (mode);
+}
+
+template<typename T>
+ALWAYS_INLINE typename if_nonpoly<typename T::measurement_type>::type
+GET_MODE_PRECISION (const T &mode)
+{
+ return mode_to_precision (mode).coeffs[0];
+}
+#endif
/* Get the number of integral bits of an object of mode MODE. */
extern CONST_MODE_IBIT unsigned char mode_ibit[NUM_MACHINE_MODES];
(targetm.truly_noop_truncation (GET_MODE_PRECISION (MODE1), \
GET_MODE_PRECISION (MODE2)))
-#define HWI_COMPUTABLE_MODE_P(MODE) \
- (SCALAR_INT_MODE_P (MODE) \
- && GET_MODE_PRECISION (MODE) <= HOST_BITS_PER_WIDE_INT)
+/* Return true if MODE is a scalar integer mode that fits in a
+ HOST_WIDE_INT. */
+
+inline bool
+HWI_COMPUTABLE_MODE_P (machine_mode mode)
+{
+ machine_mode mme = mode;
+ return (SCALAR_INT_MODE_P (mme)
+ && mode_to_precision (mme).coeffs[0] <= HOST_BITS_PER_WIDE_INT);
+}
+
+inline bool
+HWI_COMPUTABLE_MODE_P (scalar_int_mode mode)
+{
+ return GET_MODE_PRECISION (mode) <= HOST_BITS_PER_WIDE_INT;
+}
struct int_n_data_t {
/* These parts are initailized by genmodes output */
/* If the size of the object is greater than word size on this target,
then we assume that a load will not be atomic. Also see
expand_atomic_load. */
- return GET_MODE_PRECISION (mode) <= BITS_PER_WORD;
+ return known_le (GET_MODE_PRECISION (mode), BITS_PER_WORD);
}
/* Determine whether "1 << x" is relatively cheap in word_mode. */
emulate a load with a compare-and-swap operation, but the store that
doing this could result in would be incorrect if this is a volatile
atomic load or targetting read-only-mapped memory. */
- if (GET_MODE_PRECISION (mode) > BITS_PER_WORD)
+ if (maybe_gt (GET_MODE_PRECISION (mode), BITS_PER_WORD))
/* If there is no atomic load, leave the library call. */
return NULL_RTX;
/* If the size of the object is greater than word size on this target,
a default store will not be atomic. */
- if (GET_MODE_PRECISION (mode) > BITS_PER_WORD)
+ if (maybe_gt (GET_MODE_PRECISION (mode), BITS_PER_WORD))
{
/* If loads are atomic or we are called to provide a __sync builtin,
we can try a atomic_exchange and throw away the result. Otherwise,
as destination register will not affect its reaching uses, which may
read its value in a larger mode because DEF_INSN implicitly sets it
in word mode. */
- const unsigned int prec
+ poly_int64 prec
= GET_MODE_PRECISION (GET_MODE (SET_DEST (*dest_sub_rtx)));
- if (WORD_REGISTER_OPERATIONS && prec < BITS_PER_WORD)
+ if (WORD_REGISTER_OPERATIONS && known_lt (prec, BITS_PER_WORD))
{
struct df_link *uses = get_uses (def_insn, src_reg);
if (!uses)
inline bool
partial_subreg_p (machine_mode outermode, machine_mode innermode)
{
- return GET_MODE_PRECISION (outermode) < GET_MODE_PRECISION (innermode);
+ /* Modes involved in a subreg must be ordered. In particular, we must
+ always know at compile time whether the subreg is paradoxical. */
+ poly_int64 outer_prec = GET_MODE_PRECISION (outermode);
+ poly_int64 inner_prec = GET_MODE_PRECISION (innermode);
+ gcc_checking_assert (ordered_p (outer_prec, inner_prec));
+ return maybe_lt (outer_prec, inner_prec);
}
/* Likewise return true if X is a subreg that is smaller than the inner
inline bool
paradoxical_subreg_p (machine_mode outermode, machine_mode innermode)
{
- return GET_MODE_PRECISION (outermode) > GET_MODE_PRECISION (innermode);
+ /* Modes involved in a subreg must be ordered. In particular, we must
+ always know at compile time whether the subreg is paradoxical. */
+ poly_int64 outer_prec = GET_MODE_PRECISION (outermode);
+ poly_int64 inner_prec = GET_MODE_PRECISION (innermode);
+ gcc_checking_assert (ordered_p (outer_prec, inner_prec));
+ return maybe_gt (outer_prec, inner_prec);
}
/* Return true if X is a paradoxical subreg, false otherwise. */
unsigned HOST_WIDE_INT inner_nz;
enum rtx_code code;
machine_mode inner_mode;
+ unsigned int inner_width;
scalar_int_mode xmode;
unsigned int mode_width = GET_MODE_PRECISION (mode);
machines, we can compute this from which bits of the inner
object might be nonzero. */
inner_mode = GET_MODE (SUBREG_REG (x));
- if (GET_MODE_PRECISION (inner_mode) <= BITS_PER_WORD
- && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT)
+ if (GET_MODE_PRECISION (inner_mode).is_constant (&inner_width)
+ && inner_width <= BITS_PER_WORD
+ && inner_width <= HOST_BITS_PER_WIDE_INT)
{
nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
known_x, known_mode, known_ret);
? val_signbit_known_set_p (inner_mode, nonzero)
: extend_op != ZERO_EXTEND)
|| (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x))))
- && xmode_width > GET_MODE_PRECISION (inner_mode))
- nonzero |= (GET_MODE_MASK (xmode) & ~GET_MODE_MASK (inner_mode));
+ && xmode_width > inner_width)
+ nonzero
+ |= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode));
}
break;
machine_mode mode = GET_MODE (XEXP (x, 0));
HOST_WIDE_INT len = INTVAL (XEXP (x, 1));
HOST_WIDE_INT pos = INTVAL (XEXP (x, 2));
+ poly_int64 remaining_bits = GET_MODE_PRECISION (mode) - len;
- return (pos == (BITS_BIG_ENDIAN ? GET_MODE_PRECISION (mode) - len : 0));
+ return known_eq (pos, BITS_BIG_ENDIAN ? remaining_bits : 0);
}
return false;
}
inline bool
type_has_mode_precision_p (const_tree t)
{
- return TYPE_PRECISION (t) == GET_MODE_PRECISION (TYPE_MODE (t));
+ return known_eq (TYPE_PRECISION (t), GET_MODE_PRECISION (TYPE_MODE (t)));
}
#endif /* GCC_TREE_H */
Also punt on bit-fields. */
if (!INTEGRAL_TYPE_P (lhsinner)
|| TYPE_OVERFLOW_WRAPS (lhsinner)
- || GET_MODE_BITSIZE (TYPE_MODE (lhsinner)) != TYPE_PRECISION (lhsinner))
+ || maybe_ne (GET_MODE_BITSIZE (TYPE_MODE (lhsinner)),
+ TYPE_PRECISION (lhsinner)))
return;
switch (code)
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