PowerPC: Add support for RFC02658 - MMA+ Outer-Product Instructions

gas/
	* config/tc-ppc.c (md_assemble): Only check for prefix opcodes.
	* testsuite/gas/ppc/rfc02658.s: New test.
	* testsuite/gas/ppc/rfc02658.d: Likewise.
	* testsuite/gas/ppc/ppc.exp: Run it.

opcodes/
	* ppc-opc.c (XMSK8, P_GERX4_MASK, P_GERX2_MASK, XX3GERX_MASK): New.
	(powerpc_opcodes): Add dmxvi8gerx4pp, dmxvi8gerx4, dmxvf16gerx2pp,
	dmxvf16gerx2, dmxvbf16gerx2pp, dmxvf16gerx2np, dmxvbf16gerx2,
	dmxvi8gerx4spp, dmxvbf16gerx2np, dmxvf16gerx2pn, dmxvbf16gerx2pn,
	dmxvf16gerx2nn, dmxvbf16gerx2nn, pmdmxvi8gerx4pp, pmdmxvi8gerx4,
	pmdmxvf16gerx2pp, pmdmxvf16gerx2, pmdmxvbf16gerx2pp, pmdmxvf16gerx2np,
	pmdmxvbf16gerx2, pmdmxvi8gerx4spp, pmdmxvbf16gerx2np, pmdmxvf16gerx2pn,
	pmdmxvbf16gerx2pn, pmdmxvf16gerx2nn, pmdmxvbf16gerx2nn.

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 1acbba1791aaa8258261ea741be3eff89b0ba4ac..0868655f40d4e36c6c7706e78796c1194edd6855 100644 (file)
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -4065,8 +4065,7 @@ md_assemble (char *str)
   insn_length = 4;
   if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn))
     insn_length = 2;
-  else if ((opcode->flags & PPC_OPCODE_POWER10) != 0
-          && PPC_PREFIX_P (insn))
+  else if (PPC_PREFIX_P (insn))
     {
       struct insn_label_list *l;
 

diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index f27a79cfd73b4405f7259c497f220fd6054578ab..500738a06ab1034b078f4e3bc0a75a5246dd1ecd 100644 (file)
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -146,6 +146,7 @@ run_dump_test "scalarquad"
 run_dump_test "rop"
 run_dump_test "rop-checks"
 run_dump_test "rfc02653"
+run_dump_test "rfc02658"
 
 run_dump_test "dcbt"
 run_dump_test "pr27676"

diff --git a/gas/testsuite/gas/ppc/rfc02658.d b/gas/testsuite/gas/ppc/rfc02658.d
new file mode 100644 (file)
index 0000000..7af7b86
--- /dev/null
+++ b/gas/testsuite/gas/ppc/rfc02658.d
@@ -0,0 +1,51 @@
+#as: -mfuture
+#objdump: -dr -Mfuture
+#name: RFC02658 tests
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*:    (d8 12 00 ec|ec 00 12 d8)       dmxvbf16gerx2 dm0,vs0,vs2
+.*:    (50 67 8a ec|ec 8a 67 50)       dmxvbf16gerx2nn dm1,vs10,vs12
+.*:    (98 b3 14 ed|ed 14 b3 98)       dmxvbf16gerx2np dm2,vs20,vs22
+.*:    (9a 05 9e ed|ed 9e 05 9a)       dmxvbf16gerx2pn dm3,vs30,vs32
+.*:    (56 52 08 ee|ee 08 52 56)       dmxvbf16gerx2pp dm4,vs40,vs42
+.*:    (1e a2 92 ee|ee 92 a2 1e)       dmxvf16gerx2 dm5,vs50,vs52
+.*:    (56 f6 1c ef|ef 1c f6 56)       dmxvf16gerx2nn dm6,vs60,vs62
+.*:    (98 72 8c ef|ef 8c 72 98)       dmxvf16gerx2np dm7,vs12,vs14
+.*:    (98 84 0e ec|ec 0e 84 98)       dmxvf16gerx2pn dm0,vs14,vs16
+.*:    (10 92 90 ec|ec 90 92 10)       dmxvf16gerx2pp dm1,vs16,vs18
+.*:    (58 a0 12 ed|ed 12 a0 58)       dmxvi8gerx4 dm2,vs18,vs20
+.*:    (50 c0 96 ed|ed 96 c0 50)       dmxvi8gerx4pp dm3,vs22,vs24
+.*:    (10 d3 18 ee|ee 18 d3 10)       dmxvi8gerx4spp dm4,vs24,vs26
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvbf16gerx2nn dm0,vs0,vs2,255,15,3
+.*:    (50 17 00 ec|ec 00 17 50) 
+.*:    (00 00 00 60|60 00 00 00)       nop
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvbf16gerx2np dm1,vs10,vs12,255,15,3
+.*:    (98 63 8a ec|ec 8a 63 98) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvbf16gerx2 dm2,vs20,vs22,255,15,3
+.*:    (d8 b2 14 ed|ed 14 b2 d8) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvbf16gerx2pn dm3,vs30,vs32,255,15,3
+.*:    (9a 05 9e ed|ed 9e 05 9a) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvbf16gerx2pp dm4,vs40,vs42,255,15,3
+.*:    (56 52 08 ee|ee 08 52 56) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvf16gerx2nn dm5,vs50,vs52,255,15,3
+.*:    (56 a6 92 ee|ee 92 a6 56) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvf16gerx2np dm6,vs60,vs62,255,15,3
+.*:    (9e f2 1c ef|ef 1c f2 9e) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvf16gerx2 dm7,vs12,vs14,255,15,3
+.*:    (18 72 8c ef|ef 8c 72 18) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvf16gerx2pn dm0,vs14,vs16,255,15,3
+.*:    (98 84 0e ec|ec 0e 84 98) 
+.*:    (ff cf 90 07|07 90 cf ff)       pmdmxvf16gerx2pp dm1,vs16,vs18,255,15,3
+.*:    (10 92 90 ec|ec 90 92 10) 
+.*:    (ff ff 90 07|07 90 ff ff)       pmdmxvi8gerx4 dm2,vs18,vs20,255,15,15
+.*:    (58 a0 12 ed|ed 12 a0 58) 
+.*:    (ff ff 90 07|07 90 ff ff)       pmdmxvi8gerx4pp dm3,vs22,vs24,255,15,15
+.*:    (50 c0 96 ed|ed 96 c0 50) 
+.*:    (ff ff 90 07|07 90 ff ff)       pmdmxvi8gerx4spp dm4,vs24,vs26,255,15,15
+.*:    (10 d3 18 ee|ee 18 d3 10) 
+#pass

diff --git a/gas/testsuite/gas/ppc/rfc02658.s b/gas/testsuite/gas/ppc/rfc02658.s
new file mode 100644 (file)
index 0000000..b15fb5f
--- /dev/null
+++ b/gas/testsuite/gas/ppc/rfc02658.s
@@ -0,0 +1,28 @@
+        .text
+_start:
+       dmxvbf16gerx2   0,0,2
+       dmxvbf16gerx2nn 1,10,12
+       dmxvbf16gerx2np 2,20,22
+       dmxvbf16gerx2pn 3,30,32
+       dmxvbf16gerx2pp 4,40,42
+       dmxvf16gerx2    5,50,52
+       dmxvf16gerx2nn  6,60,62
+       dmxvf16gerx2np  7,12,14
+       dmxvf16gerx2pn  0,14,16
+       dmxvf16gerx2pp  1,16,18
+       dmxvi8gerx4     2,18,20
+       dmxvi8gerx4pp   3,22,24
+       dmxvi8gerx4spp  4,24,26
+       pmdmxvbf16gerx2nn       0,0,2,0xff,0xf,0x3
+       pmdmxvbf16gerx2np       1,10,12,0xff,0xf,0x3
+       pmdmxvbf16gerx2         2,20,22,0xff,0xf,0x3
+       pmdmxvbf16gerx2pn       3,30,32,0xff,0xf,0x3
+       pmdmxvbf16gerx2pp       4,40,42,0xff,0xf,0x3
+       pmdmxvf16gerx2nn        5,50,52,0xff,0xf,0x3
+       pmdmxvf16gerx2np        6,60,62,0xff,0xf,0x3
+       pmdmxvf16gerx2          7,12,14,0xff,0xf,0x3
+       pmdmxvf16gerx2pn        0,14,16,0xff,0xf,0x3
+       pmdmxvf16gerx2pp        1,16,18,0xff,0xf,0x3
+       pmdmxvi8gerx4           2,18,20,0xff,0xf,0xf
+       pmdmxvi8gerx4pp         3,22,24,0xff,0xf,0xf
+       pmdmxvi8gerx4spp        4,24,26,0xff,0xf,0xf

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index c323a2761e3e65176e858790f462996b61473edc..cf729029daca97e060e68dec78b825265021948c 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3083,8 +3083,12 @@ const struct powerpc_operand powerpc_operands[] =
 #define XMSK PMSK2 + 1
   { 0xf, 36, NULL, NULL, 0 },
 
+  /* The XMSK field in GERX prefix instructions.  */
+#define XMSK8 XMSK + 1
+  { 0xff, 36, NULL, NULL, 0 },
+
   /* The YMSK field in GER prefix instructions.  */
-#define YMSK XMSK + 1
+#define YMSK XMSK8 + 1
   { 0xf, 32, NULL, NULL, 0 },
 
   /* The YMSK field in 64-bit GER prefix instructions.  */
@@ -4014,6 +4018,8 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
 #define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44))
 #define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40))
 #define P_GER64_MASK (P_GER_MASK | (3ULL << 32))
+#define P_GERX4_MASK ((-1ULL << 48) | XX3GERX_MASK)
+#define P_GERX2_MASK (P_GERX4_MASK & ~(3ULL << 46))
 
 /* Vector splat immediate op.  */
 #define VSOP(op, xop) (OP (op) | (xop << 17))
@@ -4554,6 +4560,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
 #define XX3ACC_MASK (XX3_MASK | (3 << 21) | 1)
 #define XX3DMR_MASK (XX3ACC_MASK | (1 << 11))
 #define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))
+#define XX3GERX_MASK (XX3ACC_MASK | (1 << 16))
 
 /* The mask for an XX4 form instruction.  */
 #define XX4_MASK XX4 (0x3f, 0x3)
@@ -9036,6 +9043,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"drrnd",      ZRC(59,35,0),   Z2_MASK,     POWER6,    PPCVLE,         {FRT, FRA, FRB, RMC}},
 {"drrnd.",     ZRC(59,35,1),   Z2_MASK,     POWER6,    PPCVLE,         {FRT, FRA, FRB, RMC}},
 
+{"dmxvi8gerx4pp", XX3(59,10),  XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
+{"dmxvi8gerx4",   XX3(59,11),  XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
+
 {"dscli",      ZRC(59,66,0),   Z_MASK,      POWER6,    PPCVLE,         {FRT, FRA, SH16}},
 {"dscli.",     ZRC(59,66,1),   Z_MASK,      POWER6,    PPCVLE,         {FRT, FRA, SH16}},
 
@@ -9092,24 +9102,31 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dctdp",      XRC(59,258,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
 {"dctdp.",     XRC(59,258,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
 
+{"dmxvf16gerx2pp", XX3(59,66), XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
+{"dmxvf16gerx2",   XX3(59,67), XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
+
 {"dctfix",     XRC(59,290,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
 {"dctfix.",    XRC(59,290,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
 
 {"ddedpd",     XRC(59,322,0),  X_MASK,      POWER6,    PPCVLE,         {SP, FRT, FRB}},
 {"ddedpd.",    XRC(59,322,1),  X_MASK,      POWER6,    PPCVLE,         {SP, FRT, FRB}},
 
+{"dmxvbf16gerx2pp", XX3(59,74),        XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
 {"dmxvi16ger2",        XX3(59,75),     XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvi16ger2",  XX3(59,75),     XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 
 {"dmxvf16ger2np", XX3(59,82),  XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvf16ger2np",          XX3(59,82),   XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
+{"dmxvf16gerx2np",XX3(59,83),  XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
 
 {"dxex",       XRC(59,354,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
 {"dxex.",      XRC(59,354,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRB}},
 
 {"dmxvf32gernp",  XX3(59,90),  XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvf32gernp",   XX3(59,90),   XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
+{"dmxvbf16gerx2", XX3(59,91),  XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
 
+{"dmxvi8gerx4spp",XX3(59,98),  XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
 {"dmxvi8ger4spp", XX3(59,99),  XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvi8ger4spp",          XX3(59,99),   XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 
@@ -9118,6 +9135,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dmxvbf16ger2np",XX3(59,114), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvbf16ger2np",  XX3(59,114), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
+{"dmxvbf16gerx2np",XX3(59,115),        XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
 
 {"dmxvf64gernp",  XX3(59,122), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6ap, XB6a}},
 {"xvf64gernp",   XX3(59,122),  XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6ap, XB6a}},
@@ -9130,6 +9148,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dmxvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvf16ger2pn",          XX3(59,146),  XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
+{"dmxvf16gerx2pn",XX3(59,147), XX3GERX_MASK, FUTURE,   PPCVLE,         {DMR, XA5p, XB6}},
 
 {"dmxvf32gerpn",XX3(59,154),   XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvf32gerpn", XX3(59,154),    XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
@@ -9141,6 +9160,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"dmxvbf16ger2pn",XX3(59,178), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvbf16ger2pn",  XX3(59,178), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
+{"dmxvbf16gerx2pn", XX3(59,179),XX3GERX_MASK, FUTURE,  PPCVLE,         {DMR, XA5p, XB6}},
 
 {"dmxvf64gerpn",XX3(59,186),   XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6ap, XB6a}},
 {"xvf64gerpn", XX3(59,186),    XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6ap, XB6a}},
@@ -9151,6 +9171,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dcffix",     XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE,         {FRT, FRB}},
 {"dcffix.",    XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE,         {FRT, FRB}},
 
+{"dmxvf16gerx2nn", XX3(59,202),        XX3GERX_MASK,  FUTURE,  PPCVLE,         {DMR, XA5p, XB6}},
+
 {"denbcd",     XRC(59,834,0),  X_MASK,      POWER6,    PPCVLE,         {S, FRT, FRB}},
 {"denbcd.",    XRC(59,834,1),  X_MASK,      POWER6,    PPCVLE,         {S, FRT, FRB}},
 
@@ -9166,6 +9188,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dmxvf32gernn",XX3(59,218),   XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvf32gernn", XX3(59,218),    XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 
+{"dmxvbf16gerx2nn", XX3(59,234),XX3GERX_MASK, FUTURE,  PPCVLE,         {DMR, XA5p, XB6}},
+
 {"dmxvbf16ger2nn",XX3(59,242), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 {"xvbf16ger2nn",  XX3(59,242), XX3ACC_MASK, POWER10,   PPCVLE,         {ACC, XA6a, XB6a}},
 
@@ -9761,6 +9785,8 @@ const struct powerpc_opcode prefix_opcodes[] = {
 {"pmxvi8ger4pp",  PMMIRR|XX3(59,2),    P_GER4_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
 {"pmdmxvi8ger4",  PMMIRR|XX3(59,3),    P_GER4_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
 {"pmxvi8ger4",   PMMIRR|XX3(59,3),    P_GER4_MASK,     POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
+{"pmdmxvi8gerx4pp",PMMIRR|XX3(59,10),  P_GERX4_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
+{"pmdmxvi8gerx4", PMMIRR|XX3(59,11),   P_GERX4_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
 {"pmdmxvf16ger2pp",PMMIRR|XX3(59,18),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2pp", PMMIRR|XX3(59,18),   P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmdmxvf16ger2", PMMIRR|XX3(59,19),   P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
@@ -9785,32 +9811,43 @@ const struct powerpc_opcode prefix_opcodes[] = {
 {"pmxvf64gerpp",  PMMIRR|XX3(59,58),   P_GER64_MASK,   POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmdmxvf64ger",  PMMIRR|XX3(59,59),   P_GER64_MASK,   POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64ger",   PMMIRR|XX3(59,59),   P_GER64_MASK,    POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},
+{"pmdmxvf16gerx2pp",PMMIRR|XX3(59,66), P_GERX2_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
+{"pmdmxvf16gerx2",PMMIRR|XX3(59,67),   P_GERX2_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
+{"pmdmxvbf16gerx2pp",PMMIRR|XX3(59,74),P_GERX2_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
 {"pmdmxvi16ger2", PMMIRR|XX3(59,75),   P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvi16ger2",   PMMIRR|XX3(59,75),   P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmdmxvf16ger2np",PMMIRR|XX3(59,82),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2np", PMMIRR|XX3(59,82),   P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf16gerx2np",PMMIRR|XX3(59,83), P_GERX2_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
 {"pmdmxvf32gernp",PMMIRR|XX3(59,90),   P_GER_MASK,     POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32gernp",  PMMIRR|XX3(59,90),   P_GER_MASK,     POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK}},
+{"pmdmxvbf16gerx2",PMMIRR|XX3(59,91),  P_GERX2_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
+{"pmdmxvi8gerx4spp",PMMIRR|XX3(59,98), P_GERX4_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK4}},
 {"pmdmxvi8ger4spp",PMMIRR|XX3(59,99),  P_GER4_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
 {"pmxvi8ger4spp", PMMIRR|XX3(59,99),   P_GER4_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
 {"pmdmxvi16ger2pp",PMMIRR|XX3(59,107), P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvi16ger2pp", PMMIRR|XX3(59,107),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmdmxvbf16ger2np",PMMIRR|XX3(59,114),P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2np",PMMIRR|XX3(59,114),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvbf16gerx2np",PMMIRR|XX3(59,115),P_GERX2_MASK,  FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
 {"pmdmxvf64gernp",PMMIRR|XX3(59,122),  P_GER64_MASK,   POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64gernp",  PMMIRR|XX3(59,122),  P_GER64_MASK,   POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmdmxvf16ger2pn",PMMIRR|XX3(59,146), P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2pn", PMMIRR|XX3(59,146),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf16gerx2pn",PMMIRR|XX3(59,147),P_GERX2_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
 {"pmdmxvf32gerpn",PMMIRR|XX3(59,154),  P_GER_MASK,     POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32gerpn",  PMMIRR|XX3(59,154),  P_GER_MASK,     POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmdmxvbf16ger2pn",PMMIRR|XX3(59,178),P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2pn",PMMIRR|XX3(59,178),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvbf16gerx2pn",PMMIRR|XX3(59,179),P_GERX2_MASK,  FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
 {"pmdmxvf64gerpn",PMMIRR|XX3(59,186),  P_GER64_MASK,   POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64gerpn",  PMMIRR|XX3(59,186),  P_GER64_MASK,   POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},
+{"pmdmxvf16gerx2nn",PMMIRR|XX3(59,202),P_GERX2_MASK,   FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
 {"pmdmxvf16ger2nn",PMMIRR|XX3(59,210), P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2nn", PMMIRR|XX3(59,210),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmdmxvf32gernn",PMMIRR|XX3(59,218),  P_GER_MASK,     POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32gernn",  PMMIRR|XX3(59,218),  P_GER_MASK,     POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK}},
+{"pmdmxvbf16gerx2nn",PMMIRR|XX3(59,234),P_GERX2_MASK,  FUTURE,  0,     {DMR, XA5p, XB6, XMSK8, YMSK, PMSK2}},
 {"pmdmxvbf16ger2nn",PMMIRR|XX3(59,242),P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2nn",PMMIRR|XX3(59,242),  P_GER2_MASK,    POWER10, 0,     {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmdmxvf64gernn",PMMIRR|XX3(59,250),  P_GER64_MASK,   POWER10, 0,     {ACC, XA6ap, XB6a, XMSK, YMSK2}},