struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
assert(size);
- assert(rctx->screen->has_cp_dma);
+ assert(rctx->screen->b.has_cp_dma);
offset += r600_resource_va(&rctx->screen->b.b, dst);
r600_store_value(cb, 0);
r600_store_value(cb, 0);
- if (rctx->screen->has_streamout) {
+ if (rctx->screen->b.has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
- if (rctx->screen->has_streamout) {
+ if (rctx->screen->b.has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
{
struct r600_context *rctx = (struct r600_context*)ctx;
- if (rctx->screen->has_cp_dma) {
+ if (rctx->screen->b.has_cp_dma) {
r600_cp_dma_copy_buffer(rctx, dst, dstx, src, src_box->x, src_box->width);
}
- else if (rctx->screen->has_streamout &&
+ else if (rctx->screen->b.has_streamout &&
/* Require 4-byte alignment. */
dstx % 4 == 0 && src_box->x % 4 == 0 && src_box->width % 4 == 0) {
{
struct r600_context *rctx = (struct r600_context*)ctx;
- if (rctx->screen->has_cp_dma &&
+ if (rctx->screen->b.has_cp_dma &&
rctx->b.chip_class >= EVERGREEN &&
offset % 4 == 0 && size % 4 == 0) {
evergreen_cp_dma_clear_buffer(rctx, dst, offset, size, value);
- } else if (rctx->screen->has_streamout && offset % 4 == 0 && size % 4 == 0) {
+ } else if (rctx->screen->b.has_streamout && offset % 4 == 0 && size % 4 == 0) {
union pipe_color_union clear_value;
clear_value.ui[0] = value;
else if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
!(rctx->screen->b.debug_flags & DBG_NO_DISCARD_RANGE) &&
- (rctx->screen->has_cp_dma ||
- (rctx->screen->has_streamout &&
+ (rctx->screen->b.has_cp_dma ||
+ (rctx->screen->b.has_streamout &&
/* The buffer range must be aligned to 4 with streamout. */
box->x % 4 == 0 && box->width % 4 == 0))) {
assert(usage & PIPE_TRANSFER_WRITE);
struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs;
assert(size);
- assert(rctx->screen->has_cp_dma);
+ assert(rctx->screen->b.has_cp_dma);
dst_offset += r600_resource_va(&rctx->screen->b.b, dst);
src_offset += r600_resource_va(&rctx->screen->b.b, src);
/* Stream output. */
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
- return rscreen->has_streamout ? 4 : 0;
+ return rscreen->b.has_streamout ? 4 : 0;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
- return rscreen->has_streamout ? 1 : 0;
+ return rscreen->b.has_streamout ? 1 : 0;
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return 32*4;
switch (rscreen->b.chip_class) {
case R600:
if (rscreen->b.family < CHIP_RS780) {
- rscreen->has_streamout = rscreen->b.info.drm_minor >= 14;
+ rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
} else {
- rscreen->has_streamout = rscreen->b.info.drm_minor >= 23;
+ rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
}
break;
case R700:
- rscreen->has_streamout = rscreen->b.info.drm_minor >= 17;
+ rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
break;
case EVERGREEN:
case CAYMAN:
- rscreen->has_streamout = rscreen->b.info.drm_minor >= 14;
+ rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
break;
default:
- rscreen->has_streamout = FALSE;
+ rscreen->b.has_streamout = FALSE;
break;
}
rscreen->has_compressed_msaa_texturing = false;
}
- rscreen->has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
+ rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
!(rscreen->b.debug_flags & DBG_NO_CP_DMA);
rscreen->global_pool = compute_memory_pool_new(rscreen);
struct r600_screen {
struct r600_common_screen b;
- bool has_streamout;
bool has_msaa;
- bool has_cp_dma;
bool has_compressed_msaa_texturing;
/*for compute global memory binding, we allocate stuff here, instead of
r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
- if (rctx->b.chip_class == R700 && rctx->screen->has_streamout)
+ if (rctx->b.chip_class == R700 && rctx->screen->b.has_streamout)
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
- if (rctx->screen->has_streamout) {
+ if (rctx->screen->b.has_streamout) {
r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
}
struct radeon_info info;
struct r600_tiling_info tiling_info;
unsigned debug_flags;
+ bool has_cp_dma;
+ bool has_streamout;
/* Auxiliary context. Mainly used to initialize resources.
* It must be locked prior to using and flushed before unlocking. */
static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
{
struct r600_screen *rscreen = (struct r600_screen *)pscreen;
- bool has_streamout = HAVE_LLVM >= 0x0304;
switch (param) {
/* Supported features (boolean caps). */
/* Stream output. */
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
- return has_streamout ? 4 : 0;
+ return rscreen->b.has_streamout ? 4 : 0;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
- return has_streamout ? 1 : 0;
+ return rscreen->b.has_streamout ? 1 : 0;
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
- return has_streamout ? 32*4 : 0;
+ return rscreen->b.has_streamout ? 32*4 : 0;
/* Texturing. */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
return NULL;
}
+ rscreen->b.has_cp_dma = true;
+ rscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
+
if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;