Do not $mul -> $__mul if A and B are less than maxwidth

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index aab568c9fe5e68e61252d0c8aa1e54960579ee40..5444d842a9f5b73c6afe4d8149ac831b7acae0c4 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -28,7 +28,9 @@ module \$mul (A, B, Y);
        output [Y_WIDTH-1:0] Y;\r
 \r
        generate\r
-       if (A_SIGNED != B_SIGNED || A_WIDTH <= 1 || B_WIDTH <= 1)\r
+       if (A_SIGNED != B_SIGNED)\r
+               wire _TECHMAP_FAIL_ = 1;\r
+       else if (A_WIDTH <= `DSP_A_MAXWIDTH && B_WIDTH <= `DSP_B_MAXWIDTH)\r
                wire _TECHMAP_FAIL_ = 1;\r
        // NB: A_SIGNED == B_SIGNED == 0 from here\r
        else if (A_WIDTH >= B_WIDTH)\r