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authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 27 Oct 2023 10:28:06 +0000 (11:28 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 29 Oct 2023 08:54:37 +0000 (08:54 +0000)
openpower/isa/fixedloadshift.mdwn patch | blob | history

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 57a0c66189a52c853c9b1cce7271161cc8065a1f..39aeb6a28e517faf33c3c1aff458d92bd2f0a677 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -95,8 +95,8 @@ Description:
     Let the effective address (EA) be the sum of the contents of
     register RB shifted by (SH+1), and (RA|0).
 
-    The halfword in storage addressed by EA is loaded into
-    RT[48:63]. RT[0:47] are set to 0.
+    The halfword in storage addressed by EA is loaded into RT[48:63].
+    RT[0:47] are set to 0.
 
 Special Registers Altered: