Added format __attribute__ to stringf()
authorClifford Wolf <clifford@clifford.at>
Fri, 10 Oct 2014 15:22:08 +0000 (17:22 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 10 Oct 2014 15:22:08 +0000 (17:22 +0200)
frontends/verilog/preproc.cc
kernel/satgen.h
kernel/yosys.h
passes/cmds/show.cc
passes/techmap/techmap.cc

index f83433219fcb55ab6ce04e65600e392222b3acca..7e14fcb84de71f4cfa5a448beedbe26e34e9d662 100644 (file)
@@ -422,7 +422,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
                                        if (tok == "(" || tok == "{" || tok == "[")
                                                level++;
                                }
-                               for (size_t i = 0; i < args.size(); i++)
+                               for (int i = 0; i < GetSize(args); i++)
                                        defines_map[stringf("macro_%s_arg%d", name.c_str(), i+1)] = args[i];
                        } else {
                                insert_input(tok);
index 779c97506fd6aca719e2caf3a863bb1e08cb7603..d556f4f32ec421e4f6604319b365f65427202844 100644 (file)
@@ -68,7 +68,7 @@ struct SatGen
                                else
                                        vec.push_back(bit == (undef_mode ? RTLIL::State::Sx : RTLIL::State::S1) ? ez->CONST_TRUE : ez->CONST_FALSE);
                        } else {
-                               std::string name = pf + stringf(bit.wire->width == 1 ?  "%s" : "%s [%d]", RTLIL::id2cstr(bit.wire->name), bit.offset);
+                               std::string name = pf + (bit.wire->width == 1 ? stringf("%s", log_id(bit.wire)) : stringf("%s [%d]", log_id(bit.wire->name), bit.offset));
                                vec.push_back(ez->frozen_literal(name));
                                imported_signals[pf][bit] = vec.back();
                        }
index c5da9f046d79f0f4b46fbeead9c497d39e65cf9e..d3f8856449699ea86ba08d6d9f0ce109de84fd16 100644 (file)
@@ -82,7 +82,7 @@ namespace RTLIL {
        struct Cell;
 }
 
-std::string stringf(const char *fmt, ...);
+std::string stringf(const char *fmt, ...) __attribute__ ((format (printf, 1, 2)));
 std::string vstringf(const char *fmt, va_list ap);
 template<typename T> int GetSize(const T &obj) { return obj.size(); }
 int GetSize(RTLIL::Wire *wire);
index abe6cd460f5c6639b266c768099f8373bc2dd68e..1599879a12fc8444c43af21cee0c020ac4144122 100644 (file)
@@ -72,7 +72,7 @@ struct ShowWorker
        {
                if (currentColor == 0)
                        return "color=\"black\"";
-               return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1);
+               return stringf("colorscheme=\"dark28\", color=\"%d\", fontcolor=\"%d\"", currentColor%8+1, currentColor%8+1);
        }
 
        std::string nextColor(std::string presetColor)
index 0ee45ba39da3b4746008d165d82e196964a729a7..73da6ce1de1ec8de916b4d516bd9dfde2c178dcf 100644 (file)
@@ -109,8 +109,10 @@ struct TechmapWorker
                                                                connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
                                        constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
                                                        log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
-                               } else
-                                       connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data);
+                               } else {
+                                       connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
+                                       constmap_info += stringf("|%s %d", log_id(conn.first), i);
+                               }
                        }
 
                return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());