radeon/llvm: Don't set the IMM bit in SMRD instruction definitions.

The IMM bit is already being set in SICodeEmitter.

diff --git a/src/gallium/drivers/radeon/SIInstrInfo.td b/src/gallium/drivers/radeon/SIInstrInfo.td
index 30c9c3377ad86c725d577ed944c688f9eff3f14c..be08e8abbceac634a553704d81a001acf7b2a083 100644 (file)
--- a/src/gallium/drivers/radeon/SIInstrInfo.td
+++ b/src/gallium/drivers/radeon/SIInstrInfo.td
@@ -448,7 +448,6 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
   let mayStore = 1;
 }
 
-/*XXX: We should be able to infer the imm bit based on the arg types */
 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
                        ValueType vt> {
 
@@ -458,9 +457,7 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
               (ins SMRDmemrr:$src0),
               asm,
               [(set (vt dstClass:$dst), (constant_load ADDR_Reg:$src0))]
-  > {
-    let IMM = 0;
-  }
+  >;
 
   def _IMM : SMRD <
               op,
@@ -468,9 +465,7 @@ multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
               (ins SMRDmemri:$src0),
               asm,
               [(set (vt dstClass:$dst), (constant_load ADDR_Offset8:$src0))]
-  > {
-    let IMM = 1;
-  }
+  >;
 }
 
 include "SIInstrFormats.td"