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RISC-V: Fix gcc.target/riscv/attribute-18.c
author
Xing GUO
<higuoxing@gmail.com>
Mon, 1 Feb 2021 09:33:47 +0000
(17:33 +0800)
committer
Kito Cheng
<kito.cheng@sifive.com>
Mon, 1 Feb 2021 09:35:48 +0000
(17:35 +0800)
gcc/testsuite/ChangeLog:
* gcc.target/riscv/attribute-18.c: Add -mriscv-attribute option.
gcc/testsuite/gcc.target/riscv/attribute-18.c
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diff --git
a/gcc/testsuite/gcc.target/riscv/attribute-18.c
b/gcc/testsuite/gcc.target/riscv/attribute-18.c
index 1fd80fed51b2ddeebcd9b85d2302f300a73572bb..492360cf7c1179173e2f5cddc34bf32ed094fc87 100644
(file)
--- a/
gcc/testsuite/gcc.target/riscv/attribute-18.c
+++ b/
gcc/testsuite/gcc.target/riscv/attribute-18.c
@@
-1,4
+1,4
@@
/* { dg-do compile } */
-/* { dg-options "-march=rv64imafdcp -mabi=lp64d -misa-spec=2.2" } */
+/* { dg-options "-m
riscv-attribute -m
arch=rv64imafdcp -mabi=lp64d -misa-spec=2.2" } */
int foo() {}
/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_p\"" } } */