Fix valgrind tests when using verific

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 185b02e48b1ec2b653a76b5824db304e33ce8841..b30a5baa0bddea05896a4d0c1ab4e72a6599c66a 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2239,11 +2239,15 @@ void verific_import(Design *design, const std::map<std::string,std::string> &par
                nl_todo.erase(it);
        }
 
+       hier_tree::DeleteHierarchicalTree();
        veri_file::Reset();
 #ifdef VERIFIC_VHDL_SUPPORT
        vhdl_file::Reset();
 #endif
        Libset::Reset();
+       Message::Reset();
+       RuntimeFlags::DeleteAllFlags();
+       LineFile::DeleteAllLineFiles();
        verific_incdirs.clear();
        verific_libdirs.clear();
        verific_import_pending = false;
@@ -3248,11 +3252,15 @@ struct VerificPass : public Pass {
                                nl_todo.erase(it);
                        }
 
+                       hier_tree::DeleteHierarchicalTree();
                        veri_file::Reset();
 #ifdef VERIFIC_VHDL_SUPPORT
                        vhdl_file::Reset();
 #endif
                        Libset::Reset();
+                       Message::Reset();
+                       RuntimeFlags::DeleteAllFlags();
+                       LineFile::DeleteAllLineFiles();
                        verific_incdirs.clear();
                        verific_libdirs.clear();
                        verific_import_pending = false;

diff --git a/tests/simple/hierdefparam.v b/tests/simple/hierdefparam.v
index c9368ca7ad6bbc71597c8d39478d6e54b1a21267..a6e0ac1b73d2384ec43b1748f79c867c06b6bd3b 100644 (file)
--- a/tests/simple/hierdefparam.v
+++ b/tests/simple/hierdefparam.v
@@ -1,6 +1,6 @@
 `default_nettype none
 
-module hierdefparam_top(input [7:0] A, output [7:0] Y);
+module hierdefparam_top(input wire [7:0] A, output wire [7:0] Y);
   generate begin:foo
     hierdefparam_a mod_a(.A(A), .Y(Y));
   end endgenerate
@@ -8,7 +8,7 @@ module hierdefparam_top(input [7:0] A, output [7:0] Y);
   defparam foo.mod_a.bar[1].mod_b.addvalue = 43;
 endmodule
 
-module hierdefparam_a(input [7:0] A, output [7:0] Y);
+module hierdefparam_a(input wire [7:0] A, output wire [7:0] Y);
   genvar i;
   generate
     for (i = 0; i < 2; i=i+1) begin:bar
@@ -19,7 +19,7 @@ module hierdefparam_a(input [7:0] A, output [7:0] Y);
   assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y;
 endmodule
 
-module hierdefparam_b(input [7:0] A, output [7:0] Y);
+module hierdefparam_b(input wire [7:0] A, output wire [7:0] Y);
   parameter [7:0] addvalue = 44;
   assign Y = A + addvalue;
 endmodule

diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv
new file mode 100644 (file)
index 0000000..8b0a6f3
--- /dev/null
+++ b/tests/simple/implicit_ports.sv
@@ -0,0 +1,16 @@
+// Test implicit port connections
+module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
+       assign cout = cin;
+       assign result = a + b;
+endmodule
+
+module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
+       wire cin = 1;
+       alu alu (
+               .a(a),
+               .b, // Implicit connection is equivalent to .b(b)
+               .cin(), // Explicitely unconnected
+               .cout(cout),
+               .result(alu_result)
+       );
+endmodule

diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.v
deleted file mode 100644 (file)
index 8b0a6f3..0000000
--- a/tests/simple/implicit_ports.v
+++ /dev/null
@@ -1,16 +0,0 @@
-// Test implicit port connections
-module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result);
-       assign cout = cin;
-       assign result = a + b;
-endmodule
-
-module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout);
-       wire cin = 1;
-       alu alu (
-               .a(a),
-               .b, // Implicit connection is equivalent to .b(b)
-               .cin(), // Explicitely unconnected
-               .cout(cout),
-               .result(alu_result)
-       );
-endmodule

diff --git a/tests/simple/module_scope.v b/tests/simple/module_scope.v
index d0778391292f26c578c82b01b84841126f51fe78..ceeab731109bf86230e10dbe5cb073e22cedf1ce 100644 (file)
--- a/tests/simple/module_scope.v
+++ b/tests/simple/module_scope.v
@@ -3,7 +3,7 @@
 module module_scope_Example(o1, o2);
    parameter [31:0] v1 = 10;
    parameter [31:0] v2 = 20;
-   output [31:0] o1, o2;
+   output wire [31:0] o1, o2;
    assign module_scope_Example.o1 = module_scope_Example.v1;
    assign module_scope_Example.o2 = module_scope_Example.v2;
 endmodule
@@ -11,14 +11,14 @@ endmodule
 module module_scope_ExampleLong(o1, o2);
    parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
    parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
-   output [31:0] o1, o2;
+   output wire [31:0] o1, o2;
    assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
    assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
 endmodule
 
 module module_scope_top(
-   output [31:0] a1, a2, b1, b2, c1, c2,
-   output [31:0] d1, d2, e1, e2, f1, f2
+   output wire [31:0] a1, a2, b1, b2, c1, c2,
+   output wire [31:0] d1, d2, e1, e2, f1, f2
 );
    module_scope_Example a(a1, a2);
    module_scope_Example #(1) b(b1, b2);

diff --git a/tests/simple/specify.v b/tests/simple/specify.v
index f19418d90135c99ce5f917ed954f6f17e4082bfb..2c784ef6db93ef96aa741ac36873af3442df8877 100644 (file)
--- a/tests/simple/specify.v
+++ b/tests/simple/specify.v
@@ -1,4 +1,4 @@
-module test_specify;
+module test_specify(input A, output B);
 
 specparam a=1;