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Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 19 Jun 2022 13:55:20 +0000
(14:55 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 19 Jun 2022 13:55:25 +0000
(14:55 +0100)
openpower/sv.mdwn
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a/openpower/sv.mdwn
b/openpower/sv.mdwn
index 35d1502cc1d9ab5cc7574cbefe8fa81c9ca57dee..02f78aecbc102850cde9693509d23f72338c9f2f 100644
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openpower/sv.mdwn
+++ b/
openpower/sv.mdwn
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-19,7
+19,7
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and in GPUs, but keeps strictly to a *Simple* RISC principle of leveraging
a *Scalar* ISA, exclusively using "Prefixing". **Not one single actual
explicit Vector opcode exists in SV, at all**. It is suitable for
low-power Embedded and DSP Workloads as much as it is for power-efficient
-Su
o
ercomputing.
+Su
p
ercomputing.
Fundamental design principles: