intel/i965: make gen_device_info mutable

Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).

This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/common/gen_device_info.c b/src/intel/common/gen_device_info.c
index 7f1af19f98c4bde831e4e1b6ed8f79d6a563345f..615605c18baaf357b7bafcbb4353b99aac07e764 100644 (file)
--- a/src/intel/common/gen_device_info.c
+++ b/src/intel/common/gen_device_info.c
@@ -487,21 +487,20 @@ static const struct gen_device_info gen_device_info_kbl_gt4 = {
    .num_slices = 3,
 };
 
-const struct gen_device_info *
-gen_get_device_info(int devid)
+const bool
+gen_get_device_info(int devid, struct gen_device_info *devinfo)
 {
-   const struct gen_device_info *devinfo;
    switch (devid) {
 #undef CHIPSET
 #define CHIPSET(id, family, name) \
-   case id: devinfo = &gen_device_info_##family; break;
+      case id: *devinfo = gen_device_info_##family; break;
 #include "pci_ids/i965_pci_ids.h"
    default:
       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
-      return NULL;
+      return false;
    }
 
-   return devinfo;
+   return true;
 }
 
 const char *

diff --git a/src/intel/common/gen_device_info.h b/src/intel/common/gen_device_info.h
index 6b639d397a057b7d183e1aecef595e64b27626f7..8b68a011ea4933d38a726c7f1d8d701c45df4f41 100644 (file)
--- a/src/intel/common/gen_device_info.h
+++ b/src/intel/common/gen_device_info.h
@@ -143,5 +143,5 @@ struct gen_device_info
    /** @} */
 };
 
-const struct gen_device_info *gen_get_device_info(int devid);
+const bool gen_get_device_info(int devid, struct gen_device_info *devinfo);
 const char *gen_get_device_name(int devid);

diff --git a/src/intel/isl/tests/isl_surf_get_image_offset_test.c b/src/intel/isl/tests/isl_surf_get_image_offset_test.c
index 5ce326f7cd076d41eb35cc61f1242854f0a238dc..1b3dc58b002981d0fca43aeeb75b750514eb4efb 100644 (file)
--- a/src/intel/isl/tests/isl_surf_get_image_offset_test.c
+++ b/src/intel/isl/tests/isl_surf_get_image_offset_test.c
@@ -124,9 +124,11 @@ test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0(void)
 {
    bool ok;
 
+   struct gen_device_info devinfo;
+   t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo));
+
    struct isl_device dev;
-   isl_device_init(&dev, gen_get_device_info(BDW_GT2_DEVID),
-                   /*bit6_swizzle*/ false);
+   isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
 
    struct isl_surf surf;
    ok = isl_surf_init(&dev, &surf,
@@ -170,9 +172,11 @@ test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0(void)
 {
    bool ok;
 
+   struct gen_device_info devinfo;
+   t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo));
+
    struct isl_device dev;
-   isl_device_init(&dev, gen_get_device_info(BDW_GT2_DEVID),
-                   /*bit6_swizzle*/ false);
+   isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
 
    struct isl_surf surf;
    ok = isl_surf_init(&dev, &surf,
@@ -229,9 +233,11 @@ test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0(void)
 {
    bool ok;
 
+   struct gen_device_info devinfo;
+   t_assert(gen_get_device_info(BDW_GT2_DEVID, &devinfo));
+
    struct isl_device dev;
-   isl_device_init(&dev, gen_get_device_info(BDW_GT2_DEVID),
-                   /*bit6_swizzle*/ false);
+   isl_device_init(&dev, &devinfo, /*bit6_swizzle*/ false);
 
    struct isl_surf surf;
    ok = isl_surf_init(&dev, &surf,

diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index 2b51424742d10f178bdb70c95dc9107bf2aa4929..e52761586d05e696a6942adbc87f4566f40b366e 100644 (file)
--- a/src/intel/tools/disasm.c
+++ b/src/intel/tools/disasm.c
@@ -101,7 +101,9 @@ gen_disasm_create(int pciid)
    if (gd == NULL)
       return NULL;
 
-   gd->devinfo = *gen_get_device_info(pciid);
+   if (!gen_get_device_info(pciid, &gd->devinfo))
+      return NULL;
+
    brw_init_compaction_tables(&gd->devinfo);
 
    return gd;

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index fecb8505b89c574bed362c72dd4471e8afa34bf1..6edbb1c8c1b739eda874f06ca782ccf98a6a1f23 100644 (file)
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -77,19 +77,18 @@ anv_physical_device_init(struct anv_physical_device *device,
    }
 
    device->name = gen_get_device_name(device->chipset_id);
-   device->info = gen_get_device_info(device->chipset_id);
-   if (!device->info) {
+   if (!gen_get_device_info(device->chipset_id, &device->info)) {
       result = vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
       goto fail;
    }
 
-   if (device->info->is_haswell) {
+   if (device->info.is_haswell) {
       fprintf(stderr, "WARNING: Haswell Vulkan support is incomplete\n");
-   } else if (device->info->gen == 7 && !device->info->is_baytrail) {
+   } else if (device->info.gen == 7 && !device->info.is_baytrail) {
       fprintf(stderr, "WARNING: Ivy Bridge Vulkan support is incomplete\n");
-   } else if (device->info->gen == 7 && device->info->is_baytrail) {
+   } else if (device->info.gen == 7 && device->info.is_baytrail) {
       fprintf(stderr, "WARNING: Bay Trail Vulkan support is incomplete\n");
-   } else if (device->info->gen >= 8) {
+   } else if (device->info.gen >= 8) {
       /* Broadwell, Cherryview, Skylake, Broxton, Kabylake is as fully
        * supported as anything */
    } else {
@@ -99,7 +98,7 @@ anv_physical_device_init(struct anv_physical_device *device,
    }
 
    device->cmd_parser_version = -1;
-   if (device->info->gen == 7) {
+   if (device->info.gen == 7) {
       device->cmd_parser_version =
          anv_gem_get_param(fd, I915_PARAM_CMD_PARSER_VERSION);
       if (device->cmd_parser_version == -1) {
@@ -127,7 +126,7 @@ anv_physical_device_init(struct anv_physical_device *device,
       goto fail;
    }
 
-   if (!device->info->has_llc &&
+   if (!device->info.has_llc &&
        anv_gem_get_param(fd, I915_PARAM_MMAP_VERSION) < 1) {
       result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
                          "kernel missing wc mmap");
@@ -136,14 +135,14 @@ anv_physical_device_init(struct anv_physical_device *device,
 
    bool swizzled = anv_gem_get_bit6_swizzle(fd, I915_TILING_X);
 
-   device->max_vs_threads = device->info->max_vs_threads;
-   device->max_hs_threads = device->info->max_hs_threads;
-   device->max_ds_threads = device->info->max_ds_threads;
-   device->max_gs_threads = device->info->max_gs_threads;
-   device->max_wm_threads = device->info->max_wm_threads;
+   device->max_vs_threads = device->info.max_vs_threads;
+   device->max_hs_threads = device->info.max_hs_threads;
+   device->max_ds_threads = device->info.max_ds_threads;
+   device->max_gs_threads = device->info.max_gs_threads;
+   device->max_wm_threads = device->info.max_wm_threads;
 
    /* GENs prior to 8 do not support EU/Subslice info */
-   if (device->info->gen >= 8) {
+   if (device->info.gen >= 8) {
       device->subslice_total = anv_gem_get_param(fd, I915_PARAM_SUBSLICE_TOTAL);
       device->eu_total = anv_gem_get_param(fd, I915_PARAM_EU_TOTAL);
 
@@ -155,27 +154,27 @@ anv_physical_device_init(struct anv_physical_device *device,
          fprintf(stderr, "WARNING: Kernel 4.1 required to properly"
                          " query GPU properties.\n");
       }
-   } else if (device->info->gen == 7) {
-      device->subslice_total = 1 << (device->info->gt - 1);
+   } else if (device->info.gen == 7) {
+      device->subslice_total = 1 << (device->info.gt - 1);
    }
 
-   if (device->info->is_cherryview &&
+   if (device->info.is_cherryview &&
        device->subslice_total > 0 && device->eu_total > 0) {
       /* Logical CS threads = EUs per subslice * 7 threads per EU */
       device->max_cs_threads = device->eu_total / device->subslice_total * 7;
 
       /* Fuse configurations may give more threads than expected, never less. */
-      if (device->max_cs_threads < device->info->max_cs_threads)
-         device->max_cs_threads = device->info->max_cs_threads;
+      if (device->max_cs_threads < device->info.max_cs_threads)
+         device->max_cs_threads = device->info.max_cs_threads;
    } else {
-      device->max_cs_threads = device->info->max_cs_threads;
+      device->max_cs_threads = device->info.max_cs_threads;
    }
 
    close(fd);
 
    brw_process_intel_debug_variable();
 
-   device->compiler = brw_compiler_create(NULL, device->info);
+   device->compiler = brw_compiler_create(NULL, &device->info);
    if (device->compiler == NULL) {
       result = vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
       goto fail;
@@ -188,7 +187,7 @@ anv_physical_device_init(struct anv_physical_device *device,
        goto fail;
 
    /* XXX: Actually detect bit6 swizzling */
-   isl_device_init(&device->isl_dev, device->info, swizzled);
+   isl_device_init(&device->isl_dev, &device->info, swizzled);
 
    return VK_SUCCESS;
 
@@ -237,7 +236,7 @@ static const VkExtensionProperties device_extensions[] = {
 };
 
 static void *
-default_alloc_func(void *pUserData, size_t size, size_t align, 
+default_alloc_func(void *pUserData, size_t size, size_t align,
                    VkSystemAllocationScope allocationScope)
 {
    return malloc(size);
@@ -428,9 +427,9 @@ void anv_GetPhysicalDeviceFeatures(
       .alphaToOne                               = true,
       .multiViewport                            = true,
       .samplerAnisotropy                        = false, /* FINISHME */
-      .textureCompressionETC2                   = pdevice->info->gen >= 8 ||
-                                                  pdevice->info->is_baytrail,
-      .textureCompressionASTC_LDR               = pdevice->info->gen >= 9, /* FINISHME CHV */
+      .textureCompressionETC2                   = pdevice->info.gen >= 8 ||
+                                                  pdevice->info.is_baytrail,
+      .textureCompressionASTC_LDR               = pdevice->info.gen >= 9, /* FINISHME CHV */
       .textureCompressionBC                     = true,
       .occlusionQueryPrecise                    = true,
       .pipelineStatisticsQuery                  = false,
@@ -473,7 +472,7 @@ void anv_GetPhysicalDeviceProperties(
     VkPhysicalDeviceProperties*                 pProperties)
 {
    ANV_FROM_HANDLE(anv_physical_device, pdevice, physicalDevice);
-   const struct gen_device_info *devinfo = pdevice->info;
+   const struct gen_device_info *devinfo = &pdevice->info;
 
    const float time_stamp_base = devinfo->gen >= 9 ? 83.333 : 80.0;
 
@@ -645,7 +644,7 @@ void anv_GetPhysicalDeviceMemoryProperties(
     */
    heap_size = 3 * physical_device->aperture_size / 4;
 
-   if (physical_device->info->has_llc) {
+   if (physical_device->info.has_llc) {
       /* Big core GPUs share LLC with the CPU and thus one memory type can be
        * both cached and coherent at the same time.
        */
@@ -861,7 +860,7 @@ VkResult anv_CreateDevice(
          return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
    }
 
-   anv_set_dispatch_devinfo(physical_device->info);
+   anv_set_dispatch_devinfo(&physical_device->info);
 
    device = anv_alloc2(&physical_device->instance->alloc, pAllocator,
                        sizeof(*device), 8,
@@ -891,7 +890,7 @@ VkResult anv_CreateDevice(
       goto fail_fd;
    }
 
-   device->info = *physical_device->info;
+   device->info = physical_device->info;
    device->isl_dev = physical_device->isl_dev;
 
    /* On Broadwell and later, we can use batch chaining to more efficiently

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index ff59f479fd0377f0cdce6ea02aa7faf6c6d33fe2..7341d725cd0a58332994e9ea1838f0fbd3c4ad4d 100644 (file)
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -365,8 +365,8 @@ anv_physical_device_get_format_properties(struct anv_physical_device *physical_d
                                           VkFormat format,
                                           VkFormatProperties *out_properties)
 {
-   int gen = physical_device->info->gen * 10;
-   if (physical_device->info->is_haswell)
+   int gen = physical_device->info.gen * 10;
+   if (physical_device->info.is_haswell)
       gen += 5;
 
    VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0;
@@ -374,25 +374,25 @@ anv_physical_device_get_format_properties(struct anv_physical_device *physical_d
       /* Nothing to do here */
    } else if (vk_format_is_depth_or_stencil(format)) {
       tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
-      if (physical_device->info->gen >= 8)
+      if (physical_device->info.gen >= 8)
          tiled |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
 
       tiled |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
                VK_FORMAT_FEATURE_BLIT_DST_BIT;
    } else {
       struct anv_format linear_fmt, tiled_fmt;
-      linear_fmt = anv_get_format(physical_device->info, format,
+      linear_fmt = anv_get_format(&physical_device->info, format,
                                   VK_IMAGE_ASPECT_COLOR_BIT,
                                   VK_IMAGE_TILING_LINEAR);
-      tiled_fmt = anv_get_format(physical_device->info, format,
+      tiled_fmt = anv_get_format(&physical_device->info, format,
                                  VK_IMAGE_ASPECT_COLOR_BIT,
                                  VK_IMAGE_TILING_OPTIMAL);
 
-      linear = get_image_format_properties(physical_device->info,
+      linear = get_image_format_properties(&physical_device->info,
                                            linear_fmt.isl_format, linear_fmt);
-      tiled = get_image_format_properties(physical_device->info,
+      tiled = get_image_format_properties(&physical_device->info,
                                           linear_fmt.isl_format, tiled_fmt);
-      buffer = get_buffer_format_properties(physical_device->info,
+      buffer = get_buffer_format_properties(&physical_device->info,
                                             linear_fmt.isl_format);
 
       /* XXX: We handle 3-channel formats by switching them out for RGBX or

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index f578a9d9a85976f9b415723fa0022d3fa2381438..839f813d0d7adfde4f1ffcaae871a1d6874bc586 100644 (file)
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -564,7 +564,7 @@ struct anv_physical_device {
     uint32_t                                    chipset_id;
     char                                        path[20];
     const char *                                name;
-    const struct gen_device_info *              info;
+    struct gen_device_info                      info;
     uint64_t                                    aperture_size;
     struct brw_compiler *                       compiler;
     struct isl_device                           isl_dev;

diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 1d2070b6f8cfd088f15e9bc0a6d0235250b82af2..1134fa43878ee0919892726ceb3c6a79e2c0889f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -61,7 +61,7 @@ static void compile_clip_prog( struct brw_context *brw,
 
    /* Begin the compilation:
     */
-   brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&brw->screen->devinfo, &c.func, mem_ctx);
 
    c.func.single_program_flow = 1;
 
@@ -116,7 +116,7 @@ static void compile_clip_prog( struct brw_context *brw,
 
    if (unlikely(INTEL_DEBUG & DEBUG_CLIP)) {
       fprintf(stderr, "clip:\n");
-      brw_disassemble(brw->screen->devinfo, c.func.store,
+      brw_disassemble(&brw->screen->devinfo, c.func.store,
                       0, program_size, stderr);
       fprintf(stderr, "\n");
    }

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 908eb6d1edc43376c72494fb02d9eccd8de48aa8..9b72e8481319e0c37c96922a69fab8ca8ffb16c4 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -207,7 +207,7 @@ intel_texture_view_requires_resolve(struct brw_context *brw,
 
    const uint32_t brw_format = brw_format_for_mesa_format(intel_tex->_Format);
 
-   if (isl_format_supports_lossless_compression(brw->screen->devinfo,
+   if (isl_format_supports_lossless_compression(&brw->screen->devinfo,
                                                 brw_format))
       return false;
 
@@ -806,7 +806,7 @@ brw_initialize_cs_context_constants(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
    const struct intel_screen *screen = brw->screen;
-   const struct gen_device_info *devinfo = screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
 
    /* FINISHME: Do this for all platforms that the kernel supports */
    if (brw->is_cherryview &&
@@ -919,7 +919,7 @@ brwCreateContext(gl_api api,
 {
    struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate;
    struct intel_screen *screen = driContextPriv->driScreenPriv->driverPrivate;
-   const struct gen_device_info *devinfo = screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
    struct dd_function_table functions;
 
    /* Only allow the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag if the kernel

diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index a73673fabbf5f81cb4166e5383594bbac0512ff1..e79668f8f026c0773e417974ce8c86b96de109ea 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -84,7 +84,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
       prog_data.base.total_shared = prog->Comp.SharedSize;
    }
 
-   assign_cs_binding_table_offsets(brw->screen->devinfo, prog,
+   assign_cs_binding_table_offsets(&brw->screen->devinfo, prog,
                                    &cp->program.Base, &prog_data);
 
    /* Allocate the references to the uniforms that will end up in the

diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs.c b/src/mesa/drivers/dri/i965/brw_ff_gs.c
index 7c878e9f66e2cdb03b1d9d54b2cacd019fedbae9..d8eb1464f560eca3326d6b53458aa06e11d6ba7e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_ff_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_ff_gs.c
@@ -63,7 +63,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
 
    /* Begin the compilation:
     */
-   brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&brw->screen->devinfo, &c.func, mem_ctx);
 
    c.func.single_program_flow = 1;
 
@@ -135,7 +135,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
 
    if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
       fprintf(stderr, "gs:\n");
-      brw_disassemble(brw->screen->devinfo, c.func.store,
+      brw_disassemble(&brw->screen->devinfo, c.func.store,
                       0, program_size, stderr);
       fprintf(stderr, "\n");
     }

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 2b472c695115b580e0de5185addb195b390b6947..93a909c1c65972ff976967409c6abaa887bf8201 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -105,7 +105,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
 
    memset(&prog_data, 0, sizeof(prog_data));
 
-   assign_gs_binding_table_offsets(brw->screen->devinfo, prog,
+   assign_gs_binding_table_offsets(&brw->screen->devinfo, prog,
                                    &gp->program.Base, &prog_data);
 
    /* Allocate the references to the uniforms that will end up in the
@@ -139,7 +139,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
       ((1 << gp->program.Base.CullDistanceArraySize) - 1) <<
       gp->program.Base.ClipDistanceArraySize;
 
-   brw_compute_vue_map(brw->screen->devinfo,
+   brw_compute_vue_map(&brw->screen->devinfo,
                        &prog_data.base.vue_map, outputs_written,
                        prog->SeparateShader);
 

diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index dd5b4cce5528606f184295bc8675d3af0cb79644..6d8cd74bdf02c93b45f417f50687a5d55675c5c5 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -59,7 +59,7 @@ static void compile_sf_prog( struct brw_context *brw,
    mem_ctx = ralloc_context(NULL);
    /* Begin the compilation:
     */
-   brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&brw->screen->devinfo, &c.func, mem_ctx);
 
    c.key = *key;
    c.vue_map = brw->vue_map_geom_out;
@@ -118,7 +118,7 @@ static void compile_sf_prog( struct brw_context *brw,
 
    if (unlikely(INTEL_DEBUG & DEBUG_SF)) {
       fprintf(stderr, "sf:\n");
-      brw_disassemble(brw->screen->devinfo,
+      brw_disassemble(&brw->screen->devinfo,
                       c.func.store, 0, program_size, stderr);
       fprintf(stderr, "\n");
    }

diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c
index b1eba6d3428af478661e88246c47966d111a9fc2..1ed8aaa481c40933a06ea96add886363a41a6624 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -765,7 +765,7 @@ dump_prog_cache(struct brw_context *brw)
         }
 
          fprintf(stderr, "%s:\n", name);
-         brw_disassemble(brw->screen->devinfo, brw->cache.bo->virtual,
+         brw_disassemble(&brw->screen->devinfo, brw->cache.bo->virtual,
                          item->offset, item->size, stderr);
       }
    }

diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index d99d38670d0b2e8d8b2e3aadf1a5f045db94863f..103d3a0529c5157fa6f8696a1db865f074814456 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -288,7 +288,7 @@ brw_format_for_mesa_format(mesa_format mesa_format)
 void
 brw_init_surface_formats(struct brw_context *brw)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
    int gen;
    mesa_format format;

diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index aeaff96e54d0dd13b970619ffc707a1c696faaac..5c3c9a6ef26027c423a9264bc208d14ea282c8ce 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -83,7 +83,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
                      struct brw_tes_prog_key *key)
 {
    const struct brw_compiler *compiler = brw->screen->compiler;
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct brw_stage_state *stage_state = &brw->tes.base;
    nir_shader *nir = tep->program.Base.nir;
    struct brw_tes_prog_data prog_data;

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index c637304ce781159bf38dc4c7cc6792f353bc590b..a51e4a250464cc64c17c1488f3fe01eef1f91e81 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -112,7 +112,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
    mem_ctx = ralloc_context(NULL);
 
    brw_assign_common_binding_table_offsets(MESA_SHADER_VERTEX,
-                                           brw->screen->devinfo,
+                                           &brw->screen->devinfo,
                                            prog, &vp->program.Base,
                                            &prog_data.base.base, 0);
 
@@ -160,7 +160,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
       ((1 << vp->program.Base.CullDistanceArraySize) - 1) <<
       vp->program.Base.ClipDistanceArraySize;
 
-   brw_compute_vue_map(brw->screen->devinfo,
+   brw_compute_vue_map(&brw->screen->devinfo,
                        &prog_data.base.vue_map, outputs_written,
                        prog ? prog->SeparateShader ||
                               prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 23674f6b01f0968b4c952fc03483cff3c09428fa..ba8e4aded060240040e5d21afdb1c5e3a2e786da 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -97,7 +97,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
    if (!prog)
       prog_data.base.use_alt_mode = true;
 
-   assign_fs_binding_table_offsets(brw->screen->devinfo, prog,
+   assign_fs_binding_table_offsets(&brw->screen->devinfo, prog,
                                    &fp->program.Base, key, &prog_data);
 
    /* Allocate the references to the uniforms that will end up in the

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ba6fa5266c390cd0bdfe474247fdab1aac1adc2a..61a4b948ea773133d5e62d00b7524927129cceef 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -94,7 +94,7 @@ brw_emit_surface_state(struct brw_context *brw,
    surf.dim = get_isl_surf_dim(target);
 
    const enum isl_dim_layout dim_layout =
-      get_isl_dim_layout(brw->screen->devinfo, mt->tiling, target);
+      get_isl_dim_layout(&brw->screen->devinfo, mt->tiling, target);
 
    if (surf.dim_layout != dim_layout) {
       /* The layout of the specified texture target is not compatible with the
@@ -441,7 +441,7 @@ brw_texture_view_sane(const struct brw_context *brw,
    if (!intel_miptree_is_lossless_compressed(brw, mt))
       return true;
 
-   if (isl_format_supports_lossless_compression(brw->screen->devinfo,
+   if (isl_format_supports_lossless_compression(&brw->screen->devinfo,
                                                 format))
       return true;
 
@@ -1075,7 +1075,7 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw,
          const uint32_t surf_index = render_target_start + i;
          const int flags = (_mesa_geometric_layers(fb) > 0 ?
                               INTEL_RENDERBUFFER_LAYERED : 0) |
-                           (brw->draw_aux_buffer_disabled[i] ? 
+                           (brw->draw_aux_buffer_disabled[i] ?
                               INTEL_AUX_BUFFER_DISABLED : 0);
 
         if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) {
@@ -1150,7 +1150,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
          if (irb) {
             const unsigned format = brw->render_target_format[
                _mesa_get_render_format(ctx, intel_rb_format(irb))];
-            assert(isl_format_supports_sampling(brw->screen->devinfo,
+            assert(isl_format_supports_sampling(&brw->screen->devinfo,
                                                 format));
 
             /* Override the target of the texture if the render buffer is a
@@ -1577,7 +1577,7 @@ const struct brw_tracked_state brw_cs_image_surfaces = {
 static uint32_t
 get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    uint32_t hw_format = brw_format_for_mesa_format(format);
    if (access == GL_WRITE_ONLY) {
       return hw_format;

diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c b/src/mesa/drivers/dri/i965/gen7_cs_state.c
index 1aa4b2f669f029c38f3fe0fe7a19f8f835aa51b5..862b91553ec55155ee0a478cc67e4d48a42b6067 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_cs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c
@@ -46,7 +46,7 @@ brw_upload_cs_state(struct brw_context *brw)
    struct brw_stage_state *stage_state = &brw->cs.base;
    struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
    struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
       brw_emit_buffer_surface_state(

diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index ec494dfcd7255102bef6fa11ea357584be0407c2..ad704916c29fec962fa64f44eb371dc387fc42f0 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -58,7 +58,7 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
       needs_slm |= prog_data && prog_data->total_shared;
    }
 
-   return gen_get_default_l3_weights(brw->screen->devinfo,
+   return gen_get_default_l3_weights(&brw->screen->devinfo,
                                      needs_dc, needs_slm);
 }
 
@@ -197,7 +197,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
 static void
 update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg);
 
    if (brw->urb.size != sz) {
@@ -230,7 +230,7 @@ emit_l3_state(struct brw_context *brw)
 
    if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
       const struct gen_l3_config *const cfg =
-         gen_get_l3_config(brw->screen->devinfo, w);
+         gen_get_l3_config(&brw->screen->devinfo, w);
 
       setup_l3_config(brw, cfg);
       update_urb_size(brw, cfg);
@@ -292,7 +292,7 @@ const struct brw_tracked_state gen7_l3_state = {
 void
 gen7_restore_default_l3_config(struct brw_context *brw)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
 
    if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index 707e0739ea36ecba7f727a3b4b6628599655f2d0..4216af853cca10eba0754077c7ed6d7c22bb5a99 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -202,7 +202,7 @@ void
 gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
                 bool gs_present, bool tess_present)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const int push_size_kB =
       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
 

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 5e19d542f5deaa6283f25f405cc4c4bf9ef14db1..aba203abac6d146c2dcc8f6c8de4ad8a48da83cd 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -262,7 +262,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
    if (brw->gen >= 9) {
       mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
       const uint32_t brw_format = brw_format_for_mesa_format(linear_format);
-      return isl_format_supports_lossless_compression(brw->screen->devinfo,
+      return isl_format_supports_lossless_compression(&brw->screen->devinfo,
                                                       brw_format);
    } else
       return true;
@@ -3063,7 +3063,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
                            struct isl_surf *surf)
 {
    surf->dim = get_isl_surf_dim(mt->target);
-   surf->dim_layout = get_isl_dim_layout(brw->screen->devinfo,
+   surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo,
                                          mt->tiling, mt->target);
 
    if (mt->num_samples > 1) {

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index d4e34ec4a2dec33c6dfdcd804da293bbcfadc07a..2026e3eed121e29bce2977ca372255cb40897336 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1088,7 +1088,7 @@ intelCreateBuffer(__DRIscreen *dri_screen,
    if (mesaVis->depthBits == 24) {
       assert(mesaVis->stencilBits == 8);
 
-      if (screen->devinfo->has_hiz_and_separate_stencil) {
+      if (screen->devinfo.has_hiz_and_separate_stencil) {
          rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT,
                                                 num_samples);
          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
@@ -1141,7 +1141,7 @@ intelDestroyBuffer(__DRIdrawable * driDrawPriv)
 static void
 intel_detect_sseu(struct intel_screen *screen)
 {
-   assert(screen->devinfo->gen >= 8);
+   assert(screen->devinfo.gen >= 8);
    int ret;
 
    screen->subslice_total = -1;
@@ -1278,13 +1278,13 @@ intel_supported_msaa_modes(const struct intel_screen  *screen)
    static const int gen6_modes[] = {4, 0, -1};
    static const int gen4_modes[] = {0, -1};
 
-   if (screen->devinfo->gen >= 9) {
+   if (screen->devinfo.gen >= 9) {
       return gen9_modes;
-   } else if (screen->devinfo->gen >= 8) {
+   } else if (screen->devinfo.gen >= 8) {
       return gen8_modes;
-   } else if (screen->devinfo->gen >= 7) {
+   } else if (screen->devinfo.gen >= 7) {
       return gen7_modes;
-   } else if (screen->devinfo->gen == 6) {
+   } else if (screen->devinfo.gen == 6) {
       return gen6_modes;
    } else {
       return gen4_modes;
@@ -1309,7 +1309,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
    static const uint8_t multisample_samples[2]  = {4, 8};
 
    struct intel_screen *screen = dri_screen->driverPrivate;
-   const struct gen_device_info *devinfo = screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
    uint8_t depth_bits[4], stencil_bits[4];
    __DRIconfig **configs = NULL;
 
@@ -1431,9 +1431,9 @@ static void
 set_max_gl_versions(struct intel_screen *screen)
 {
    __DRIscreen *dri_screen = screen->driScrnPriv;
-   const bool has_astc = screen->devinfo->gen >= 9;
+   const bool has_astc = screen->devinfo.gen >= 9;
 
-   switch (screen->devinfo->gen) {
+   switch (screen->devinfo.gen) {
    case 9:
    case 8:
       dri_screen->max_gl_core_version = 44;
@@ -1445,7 +1445,7 @@ set_max_gl_versions(struct intel_screen *screen)
       dri_screen->max_gl_core_version = 33;
       dri_screen->max_gl_compat_version = 30;
       dri_screen->max_gl_es1_version = 11;
-      dri_screen->max_gl_es2_version = screen->devinfo->is_haswell ? 31 : 30;
+      dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30;
       break;
    case 6:
       dri_screen->max_gl_core_version = 33;
@@ -1573,8 +1573,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
        return false;
 
    screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr);
-   screen->devinfo = gen_get_device_info(screen->deviceID);
-   if (!screen->devinfo)
+   if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
       return false;
 
    brw_process_intel_debug_variable();
@@ -1582,7 +1581,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
    if (INTEL_DEBUG & DEBUG_BUFMGR)
       dri_bufmgr_set_debug(screen->bufmgr, true);
 
-   if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo->gen < 7) {
+   if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo.gen < 7) {
       fprintf(stderr,
               "shader_time debugging requires gen7 (Ivybridge) or better.\n");
       INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
@@ -1632,10 +1631,10 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
    screen->hw_has_timestamp = intel_detect_timestamp(screen);
 
    /* GENs prior to 8 do not support EU/Subslice info */
-   if (screen->devinfo->gen >= 8) {
+   if (screen->devinfo.gen >= 8) {
       intel_detect_sseu(screen);
-   } else if (screen->devinfo->gen == 7) {
-      screen->subslice_total = 1 << (screen->devinfo->gt - 1);
+   } else if (screen->devinfo.gen == 7) {
+      screen->subslice_total = 1 << (screen->devinfo.gt - 1);
    }
 
    const char *force_msaa = getenv("INTEL_FORCE_MSAA");
@@ -1659,7 +1658,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
     *
     * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
     */
-   if (screen->devinfo->gen >= 6) {
+   if (screen->devinfo.gen >= 6) {
       struct drm_i915_reset_stats stats;
       memset(&stats, 0, sizeof(stats));
 
@@ -1678,20 +1677,20 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
     * MI_MATH GPR registers, and version 7 in order to use
     * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
     */
-   screen->has_mi_math_and_lrr = screen->devinfo->gen >= 8 ||
-                                      (screen->devinfo->is_haswell &&
+   screen->has_mi_math_and_lrr = screen->devinfo.gen >= 8 ||
+                                      (screen->devinfo.is_haswell &&
                                        screen->cmd_parser_version >= 7);
 
    dri_screen->extensions = !screen->has_context_reset_notification
       ? screenExtensions : intelRobustScreenExtensions;
 
    screen->compiler = brw_compiler_create(screen,
-                                               screen->devinfo);
+                                          &screen->devinfo);
    screen->compiler->shader_debug_log = shader_debug_log_mesa;
    screen->compiler->shader_perf_log = shader_perf_log_mesa;
    screen->program_id = 1;
 
-   if (screen->devinfo->has_resource_streamer) {
+   if (screen->devinfo.has_resource_streamer) {
       screen->has_resource_streamer =
         intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER);
    }

diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index acf319c4b70cd7894a4327251c4ecf42deb6834a..51c1d4e3dbdd8a4a61510df9f15ad8d733b0710a 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -40,7 +40,7 @@
 struct intel_screen
 {
    int deviceID;
-   const struct gen_device_info *devinfo;
+   struct gen_device_info devinfo;
 
    __DRIscreen *driScrnPriv;