# RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem
**URLs**:
+* <https://www.sigarch.org/simd-instructions-considered-harmful/>
* <https://libre-soc.org/openpower/sv/>
* <https://libre-soc.org/openpower/sv/rfc/ls010/>
* <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
**Motivation**
-SIMD is getting out of control and damaging the reputation of mainstream
-general-purpose ISAs that offer it. A solution from 50 years ago exists
-in the form of Cray-Style True-Scalable Vectors. However the usual way that
-True-Scalable Vector ISAs are done *also* adds more instructions and
-complexifies the ISA. Simple-V takes a step back to a simpler era in
-computing from half a century ago: the Zilog Z80 CPIR and LDIR instructions,
-and the 8086 REP instruction, and brings them forward to Modern-day Computing.
-The result is a huge reduction in programming complexity, and a strong
-base to project the Power ISA back to the most powerful Supercomputing ISA
-for at least the next two decades.
+Just at the time when customers are asking for higher performance,
+the seductive lure of SIMD, as outlined in the sigarch "SIMD Considered
+Harmful" article is getting out of control and damaging the reputation
+of mainstream general-purpose ISAs that offer it. A solution from
+50 years ago exists in the form of Cray-Style True-Scalable Vectors.
+However the usual way that True-Scalable Vector ISAs are done *also*
+adds more instructions and complexifies the ISA. Simple-V takes a step
+back to a simpler era in computing from half a century ago: the Zilog
+Z80 CPIR and LDIR instructions, and the 8086 REP instruction, and brings
+them forward to Modern-day Computing. The result is a huge reduction in
+programming complexity, and a strong base to project the Power ISA back
+to the most powerful Supercomputing ISA for at least the next two decades.
**Notes and Observations**: