sources = []
sources += Split('''
+ t1000.cc
''')
# Convert file names to SCons File objects. This takes care of the
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/** @file
+ * Implementation of T1000 platform.
+ */
+
+#include <deque>
+#include <string>
+#include <vector>
+
+#include "cpu/intr_control.hh"
+#include "dev/simconsole.hh"
+#include "dev/sparc/t1000.hh"
+#include "sim/builder.hh"
+#include "sim/system.hh"
+
+using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
+
+T1000::T1000(const string &name, System *s, IntrControl *ic)
+ : Platform(name, ic), system(s)
+{
+ // set the back pointer from the system to myself
+ system->platform = this;
+}
+
+Tick
+T1000::intrFrequency()
+{
+ return (Tick)0;
+}
+
+void
+T1000::postConsoleInt()
+{
+}
+
+void
+T1000::clearConsoleInt()
+{
+}
+
+void
+T1000::postPciInt(int line)
+{
+}
+
+void
+T1000::clearPciInt(int line)
+{
+}
+
+Addr
+T1000::pciToDma(Addr pciAddr) const
+{
+ return (Addr)0;
+}
+
+
+Addr
+T1000::calcConfigAddr(int bus, int dev, int func)
+{
+ return (Addr)0;
+}
+
+void
+T1000::serialize(std::ostream &os)
+{
+}
+
+void
+T1000::unserialize(Checkpoint *cp, const std::string §ion)
+{
+}
+
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
+
+ SimObjectParam<System *> system;
+ SimObjectParam<IntrControl *> intrctrl;
+
+END_DECLARE_SIM_OBJECT_PARAMS(T1000)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
+
+ INIT_PARAM(system, "system"),
+ INIT_PARAM(intrctrl, "interrupt controller")
+
+END_INIT_SIM_OBJECT_PARAMS(T1000)
+
+CREATE_SIM_OBJECT(T1000)
+{
+ return new T1000(getInstanceName(), system, intrctrl);
+}
+
+REGISTER_SIM_OBJECT("T1000", T1000)
--- /dev/null
+/*
+ * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/**
+ * @file
+ * Declaration of top level class for the Tsunami chipset. This class just
+ * retains pointers to all its children so the children can communicate.
+ */
+
+#ifndef __DEV_T1000_HH__
+#define __DEV_T1000_HH__
+
+#include "dev/platform.hh"
+
+class IdeController;
+class System;
+
+class T1000 : public Platform
+{
+ public:
+ /** Pointer to the system */
+ System *system;
+
+ public:
+ /**
+ * Constructor for the Tsunami Class.
+ * @param name name of the object
+ * @param s system the object belongs to
+ * @param intctrl pointer to the interrupt controller
+ */
+ T1000(const std::string &name, System *s, IntrControl *intctrl);
+
+ /**
+ * Return the interrupting frequency to AlphaAccess
+ * @return frequency of RTC interrupts
+ */
+ virtual Tick intrFrequency();
+
+ /**
+ * Cause the cpu to post a serial interrupt to the CPU.
+ */
+ virtual void postConsoleInt();
+
+ /**
+ * Clear a posted CPU interrupt (id=55)
+ */
+ virtual void clearConsoleInt();
+
+ /**
+ * Cause the chipset to post a cpi interrupt to the CPU.
+ */
+ virtual void postPciInt(int line);
+
+ /**
+ * Clear a posted PCI->CPU interrupt
+ */
+ virtual void clearPciInt(int line);
+
+
+ virtual Addr pciToDma(Addr pciAddr) const;
+
+ /**
+ * Calculate the configuration address given a bus/dev/func.
+ */
+ virtual Addr calcConfigAddr(int bus, int dev, int func);
+
+ /**
+ * Serialize this object to the given output stream.
+ * @param os The stream to serialize to.
+ */
+ virtual void serialize(std::ostream &os);
+
+ /**
+ * Reconstruct the state of this object from a checkpoint.
+ * @param cp The checkpoint use.
+ * @param section The section name of this object
+ */
+ virtual void unserialize(Checkpoint *cp, const std::string §ion);
+};
+
+#endif // __DEV_T1000_HH__
--- /dev/null
+from m5.params import *
+from m5.proxy import *
+from Device import BasicPioDevice
+from Platform import Platform
+from AlphaConsole import AlphaConsole
+from Uart import Uart8250
+from Pci import PciConfigAll
+from BadDevice import BadDevice
+
+class IsaFake(BasicPioDevice):
+ type = 'IsaFake'
+ pio_size = Param.Addr(0x8, "Size of address range")
+ ret_data = Param.UInt8(0xFF, "Default data to return")
+ ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
+
+class BadAddr(IsaFake):
+ ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
+
+class T1000(Platform):
+ type = 'T1000'
+ system = Param.System(Parent.any, "system")
+
+ fake_iob = IsaFake(pio_addr=0x8000000000, pio_size=0x7F00000000)
+
+ fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
+ fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
+ fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
+ fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
+
+ fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
+
+ fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
+
+ fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
+ fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
+ fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
+ fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
+ fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
+ fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
+ fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
+ fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
+ fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
+ fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
+
+ fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
+ fake_ata1 = IsaFake(pio_addr=0x801fc000170)
+
+ fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
+ uart = Uart8250(pio_addr=0x801fc0003f8)
+
+ # Attach I/O devices to specified bus object. Can't do this
+ # earlier, since the bus object itself is typically defined at the
+ # System level.
+ def attachIO(self, bus):
+ self.fake_iob.pio = bus.port
+ self.fake_uart1.pio = bus.port
+ self.fake_uart2.pio = bus.port
+ self.fake_uart3.pio = bus.port
+ self.fake_uart4.pio = bus.port
+ self.fake_ppc.pio = bus.port
+ self.fake_OROM.pio = bus.port
+ self.fake_pnp_addr.pio = bus.port
+ self.fake_pnp_write.pio = bus.port
+ self.fake_pnp_read0.pio = bus.port
+ self.fake_pnp_read1.pio = bus.port
+ self.fake_pnp_read2.pio = bus.port
+ self.fake_pnp_read3.pio = bus.port
+ self.fake_pnp_read4.pio = bus.port
+ self.fake_pnp_read5.pio = bus.port
+ self.fake_pnp_read6.pio = bus.port
+ self.fake_pnp_read7.pio = bus.port
+ self.fake_ata0.pio = bus.port
+ self.fake_ata1.pio = bus.port
+ self.fb.pio = bus.port
+ self.io.pio = bus.port
+ self.uart.pio = bus.port
projects / gem5.git / commitdiff