log(" yosys [modname]*>\n");
log(" only part of current module 'modname' is selected\n");
log("\n");
- log("When in interavtive shell, some errors (e.g. invalid command arguments)\n");
+ log("When in interactive shell, some errors (e.g. invalid command arguments)\n");
log("do not terminate yosys but return to the command prompt.\n");
log("\n");
log("This command is the default action if nothing else has been specified\n");
log(" whole design.\n");
log("\n");
log(" -module <modname>\n");
- log(" limit the current scope to the specified module\n");
+ log(" limit the current scope to the specified module.\n");
log(" the difference between this and simply selecting the module\n");
log(" is that all object names are interpreted relative to this\n");
log(" module after this command until the selection is cleared again.\n");
log("\n");
log("When this command is called without an argument, the current selection\n");
- log("is displayed in a compact form (i.e.. only the module name when a whole module\n");
+ log("is displayed in a compact form (i.e. only the module name when a whole module\n");
log("is selected).\n");
log("\n");
log("The <selection> argument itself is a series of commands for a simple stack\n");
log(" all objects with a matching attribute name-value-pair\n");
log("\n");
log(" n:<pattern>\n");
- log(" all object with a name matching the given pattern\n");
- log(" (i.e. the n: is optional as it is the default matching rule)\n");
+ log(" all objects with a name matching the given pattern\n");
+ log(" (i.e. 'n:' is optional as it is the default matching rule)\n");
log("\n");
log(" @<name>\n");
log(" push the selection saved prior with 'select -set <name> ...'\n");
log(" pop the top set from the stack and subtract it from the new top\n");
log("\n");
log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
- log(" expand top set <num1> num times accorind to the specified rules.\n");
+ log(" expand top set <num1> num times according to the specified rules.\n");
log(" (i.e. select all cells connected to selected wires and select all\n");
log(" wires connected to selected cells) The rules specify which cell\n");
log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n");
log(" and a '+' for inclusion, followed by an optional comma seperated\n");
- log(" list of cell types followed by an optional comma seperated list of\n");
+ log(" list of cell types followed by an optional comma separated list of\n");
log(" cell ports in square brackets. a rule can also be just a cell or wire\n");
log(" name that limits the expansion (is included but does not go beyond).\n");
log(" select at most <num2> objects. a warning message is printed when this\n");
log(" Also run the specified command with the postscript file as parameter.\n");
log("\n");
log(" -lib <verilog_or_ilang_file>\n");
- log(" Use the specified library file for determining whether cell ports are.\n");
+ log(" Use the specified library file for determining whether cell ports are\n");
log(" inputs or outputs. This option can be used multiple times to specify\n");
log(" more than one library.\n");
log("\n");
if (asprintf(&p, "%s/input.v", tempdir_name) < 0) abort();
FILE *f = fopen(p, "wt");
- if (f == NULL);
+ if (f == NULL)
log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
free(p);
if (asprintf(&p, "%s/stdcells.genlib", tempdir_name) < 0) abort();
f = fopen(p, "wt");
- if (f == NULL);
+ if (f == NULL)
log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
log("\n");
log(" -liberty <file>\n");
log(" generate netlists for the specified cell library (using the liberty\n");
- log(" file format). This option is ignored if also -script option is also\n");
- log(" used. Without this option, ABC is used to optimize the netlist but\n");
- log(" keeps using yosys's internal gate library.\n");
+ log(" file format). Without this option, ABC is used to optimize the netlist\n");
+ log(" but keeps using yosys's internal gate library. This option is ignored if\n");
+ log(" the -script option is also used.\n");
log("\n");
log(" -nocleanup\n");
log(" when this option is used, the temporary files created by this pass\n");
log("\n");
log(" fsm_detect [selection]\n");
log("\n");
- log("This pass detects finite state machine by identifying the state signal.\n");
+ log("This pass detects finite state machines by identifying the state signal.\n");
log("The state signal is then marked by setting the attribute 'fsm_encoding'\n");
log("on the state signal to \"auto\".\n");
log("\n");
log("Existing 'fsm_encoding' attributes are not changed by this pass.\n");
log("\n");
- log("Signals can be protected from beeing detected by this pass by setting the\n");
- log("'fsm_encoding' atrribute to \"none\".\n");
+ log("Signals can be protected from being detected by this pass by setting the\n");
+ log("'fsm_encoding' attribute to \"none\".\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
log("\n");
log(" fsm_expand [selection]\n");
log("\n");
- log("The fsm_extract pass is conservative about the cells that belong the a finate\n");
+ log("The fsm_extract pass is conservative about the cells that belong to a finite\n");
log("state machine. This pass can be used to merge additional auxiliary gates into\n");
log("the finate state machine.\n");
log("\n");
log(" opt_muxtree [selection]\n");
log("\n");
log("This pass analyzes the control signals for the multiplexer trees in the design\n");
- log("and identifies inputs that can never be active. In then removes this dead\n");
+ log("and identifies inputs that can never be active. It then removes this dead\n");
log("branches from the multiplexer trees.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");
log(" opt_rmunused [selection]\n");
log("\n");
log("This pass identifies wires and cells that are unused and removes them. Other\n");
- log("often remove cells but leave the wires in the design or reconnect the wires\n");
- log("but leave the old cells in the design. This pass can be used to clean up after\n");
- log("the passes that do the actual work.\n");
+ log("passes often remove cells but leave the wires in the design or reconnect the\n");
+ log("wires but leave the old cells in the design. This pass can be used to clean up\n");
+ log("after the passes that do the actual work.\n");
log("\n");
log("This pass only operates on completely selected modules without processes.\n");
log("\n");
log("\n");
log(" proc_dff [selection]\n");
log("\n");
- log("This pass identifies flip-flops in the processes and converts then to\n");
- log("flip-flop cells.\n");
+ log("This pass identifies flip-flops in the processes and converts them to\n");
+ log("d-type flip-flop cells.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
log("\n");
log(" -max_depth <num>\n");
log(" limit to loops not longer than the specified number of cells. This can\n");
- log(" e.g. be usefull in identifying local loops in a module that turns out\n");
+ log(" e.g. be useful in identifying local loops in a module that turns out\n");
log(" to be one gigantic SCC.\n");
log("\n");
log(" -all_cell_types\n");
};
struct SubmodPass : public Pass {
- SubmodPass() : Pass("submod", "moving part of a module to a new submodle") { }
+ SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
- log_header("Executing SUBMOD pass (moving cells to submodes as requested).\n");
+ log_header("Executing SUBMOD pass (moving cells to submodules as requested).\n");
log_push();
Pass::call(design, "opt_rmunused");
OBJS += passes/techmap/techmap.o
passes/techmap/stdcells.inc: techlibs/stdcells.v
+ echo "// autogenerated from $<" > $@.new
od -v -td1 -w1 $< | awk 'BEGIN { print "static char stdcells_code[] = {"; } $$2 != "" { print $$2 ","; } \
- END { print 0 "};"; }' | fmt > $@.new
+ END { print 0 "};"; }' | fmt >> $@.new
mv $@.new $@
passes/techmap/techmap.o: passes/techmap/stdcells.inc
log("\n");
log(" techmap [-map filename] [selection]\n");
log("\n");
- log("This pass implements a very simple technology mapper than replaces cells in\n");
+ log("This pass implements a very simple technology mapper that replaces cells in\n");
log("the design with implementations given in form of a verilog or ilang source\n");
log("file.\n");
log("\n");
log(" -map filename\n");
log(" the library of cell implementations to be used.\n");
log(" without this parameter a builtin library is used that\n");
- log(" transform the internal RTL cells to the internal gate\n");
+ log(" transforms the internal RTL cells to the internal gate\n");
log(" library.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");
projects / yosys.git / commitdiff