case kind::BITVECTOR_NEG: return "bvneg";
case kind::BITVECTOR_UDIV_TOTAL:
case kind::BITVECTOR_UDIV: return "bvudiv";
+ case kind::BITVECTOR_UREM_TOTAL:
case kind::BITVECTOR_UREM: return "bvurem";
case kind::BITVECTOR_SDIV: return "bvsdiv";
case kind::BITVECTOR_SREM: return "bvsrem";
regress2/sygus/multi-udiv.sy
regress2/sygus/nia-max-square.sy
regress2/sygus/no-syntax-test-no-si.sy
+ regress2/sygus/pbe_bvurem.sy
regress2/sygus/process-10-vars-2fun.sy
regress2/sygus/process-arg-invariance.sy
regress2/sygus/real-grammar-neg.sy
--- /dev/null
+; EXPECT: unsat
+; COMMAND-LINE: --sygus-out=status
+(set-logic BV)
+(define-sort BV () (_ BitVec 8))
+(synth-fun IC ((s BV) (t BV)) Bool
+ ((Start Bool (
+ true
+ false
+ (ite Start Start Start)
+ (= (bvmul StartBv s) t)
+ ))
+ (StartBv BV (
+ s
+ t
+ #x00
+ #x01
+ #x7E
+ (bvnot StartBv)
+ (bvmul StartBv StartBv)
+ (bvudiv StartBv StartBv)
+ (bvurem StartBv StartBv)
+ (bvand StartBv StartBv)
+ ))
+))
+(constraint (not (IC (_ bv32 8) (_ bv187 8) )))
+(constraint (not (IC (_ bv102 8) (_ bv15 8) )))
+(constraint (not (IC (_ bv92 8) (_ bv85 8) )))
+(constraint (IC (_ bv39 8) (_ bv214 8) ))
+(constraint (IC (_ bv155 8) (_ bv82 8) ))
+(constraint (IC (_ bv53 8) (_ bv98 8) ))
+(constraint (IC (_ bv41 8) (_ bv47 8) ))
+(check-synth)