r300: don't flush VAP too often.

Flush the VAP the first time for each state atom we upload new
VAP data

diff --git a/src/mesa/drivers/dri/r300/r300_cmdbuf.c b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
index c3a808ca79f6d37aeaf7a1c9d7f7b8dfb9512ad4..3b12d364193a361d008f055e0d77e39374b4ce56 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_cmdbuf.c
+++ b/src/mesa/drivers/dri/r300/r300_cmdbuf.c
@@ -97,14 +97,20 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
        addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
        ndw = cmd.vpu.count * 4;
        if (ndw) {
-               BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
-
-               /* flush processing vertices */
-               OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
-               OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
-               OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
-               OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
-               OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 1);
+
+               if (r300->vap_flush_needed) {
+                       BEGIN_BATCH_NO_AUTOSTATE(15 + ndw);
+
+                       /* flush processing vertices */
+                       OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0);
+                       OUT_BATCH_REGVAL(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
+                       OUT_BATCH_REGVAL(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN);
+                       OUT_BATCH_REGVAL(R300_SC_SCREENDOOR, 0xffffff);
+                       OUT_BATCH_REGVAL(R300_VAP_PVS_STATE_FLUSH_REG, 0);
+                       r300->vap_flush_needed = GL_FALSE;
+               } else {
+                       BEGIN_BATCH_NO_AUTOSTATE(5 + ndw);
+               }
                OUT_BATCH_REGVAL(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
                OUT_BATCH(CP_PACKET0(R300_VAP_PVS_UPLOAD_DATA, ndw-1) | RADEON_ONE_REG_WR);
                for (i = 0; i < ndw; i++) {

diff --git a/src/mesa/drivers/dri/r300/r300_context.c b/src/mesa/drivers/dri/r300/r300_context.c
index dd63add8340add5fcdbdaf394b1bf3dadc3ab58b..5d497efc9c48430cd78cad526f8744ef15ced7bd 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_context.c
+++ b/src/mesa/drivers/dri/r300/r300_context.c
@@ -235,7 +235,11 @@ static void r300_vtbl_emit_cs_header(struct radeon_cs *cs, radeonContextPtr rmes
 
 static void r300_vtbl_pre_emit_atoms(radeonContextPtr radeon)
 {
+   r300ContextPtr r300 = (r300ContextPtr)radeon;
    BATCH_LOCALS(radeon);
+
+   r300->vap_flush_needed = GL_TRUE;
+
    cp_wait(radeon, R300_WAIT_3D | R300_WAIT_3D_CLEAN);
    BEGIN_BATCH_NO_AUTOSTATE(2);
    OUT_BATCH_REGVAL(R300_TX_INVALTAGS, R300_TX_FLUSH);

diff --git a/src/mesa/drivers/dri/r300/r300_context.h b/src/mesa/drivers/dri/r300/r300_context.h
index 6d3472722da6f128b9824815ec93f974e2538f06..37718f5415df60357b99c40e3efe5ca29b3bcc9a 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_context.h
+++ b/src/mesa/drivers/dri/r300/r300_context.h
@@ -683,7 +683,9 @@ struct r300_context {
        GLboolean disable_lowimpact_fallback;
 
        DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */
+       
        struct r300_swtcl_info swtcl;
+       GLboolean vap_flush_needed;
 };
 
 struct r300_buffer_object {

diff --git a/src/mesa/drivers/dri/r300/r300_ioctl.c b/src/mesa/drivers/dri/r300/r300_ioctl.c
index 5e3e529bff6136a3f7ae38d2aaf95209eca1070c..619d268f387c3d7f20f0b5433e5ac5e35ff6a7ef 100644 (file)
--- a/src/mesa/drivers/dri/r300/r300_ioctl.c
+++ b/src/mesa/drivers/dri/r300/r300_ioctl.c
@@ -528,6 +528,8 @@ static void r300EmitClearState(GLcontext * ctx)
                                       PVS_SRC_SELECT_FORCE_0,
                                       PVS_SRC_REG_INPUT, VSF_FLAG_NONE);
                vpu.cmd[8] = 0x0;
+
+               r300->vap_flush_needed = GL_TRUE;
                emit_vpu(ctx, &vpu);
        }
 }