## Register files, elements, and Element-width Overrides
-In the Upper Compliancy Levels the size of the GPR and FPR Register
+In the Upper Compliancy Levels of SVP64 the size of the GPR and FPR Register
files are expanded from 32 to 128 entries, and the number of CR Fields
-expanded from CR0-CR7 to CR0-CR127.
+expanded from CR0-CR7 to CR0-CR127. (Note: A future version of SVP64 is anticipated
+to extend the VSR register file).
Memory access remains exactly the same: the effects of `MSR.LE` remain
exactly the same, affecting as they already do and remain **only**
nothing to do with the ordering of the contents of register files or
register-register operations.
+To be absolutely clear:
+
+**No conceptual arithmetic ordering or other changes over the Scalar Power ISA
+definitions to registers or register files
+or to arithmetic or Logical Operations beyond element-width subdivision and
+sequential element numbering are expressed or implied**
+
Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered
and for numbering to be sequentially incremental the element offset
numbering is naturally **LSB0-sequentially-incrementing from zero not
MSB0-incrementing.** Expressed exclusively in MSB0-numbering, SVP64 is
-unnecessarily complex to understand: the required subtractions from 63,
+becomes unnecessarily complex to both express and subsequently understand:
+the required subtractions from 63,
31, 15 and 7 unfortunately become a hostile minefield. Therefore for the
purposes of this section the more natural **LSB0 numbering is assumed**
and it is up to the reader to translate to MSB0 numbering.