phy: use vivado parameters and fix RX datapath (LSB first)

diff --git a/lib/sata/phy/k7sataphy/datapath.py b/lib/sata/phy/k7sataphy/datapath.py
index 28ae7cf61cc1e864c8c4dba2ee1e04d82d0d341a..42a91e95c3df8c021b0fadf9411cb9784a17ebd1 100644 (file)
--- a/lib/sata/phy/k7sataphy/datapath.py
+++ b/lib/sata/phy/k7sataphy/datapath.py
@@ -20,8 +20,8 @@ class K7SATAPHYDatapathRX(Module):
                data_sr_d = Signal(32+8)
                charisk_sr_d = Signal(4+1)
                self.comb += [
-                       data_sr.eq(Cat(self.sink.data, data_sr_d)),
-                       charisk_sr.eq(Cat(self.sink.charisk, charisk_sr_d))
+                       data_sr.eq(Cat(data_sr_d[16:], self.sink.data)),
+                       charisk_sr.eq(Cat(charisk_sr_d[2:], self.sink.charisk))
                ]
                self.sync.sata_rx += [
                        data_sr_d.eq(data_sr),
@@ -44,7 +44,7 @@ class K7SATAPHYDatapathRX(Module):
                data = Signal(32)
                charisk = Signal(4)
                self.comb += [
-                       If(~alignment,
+                       If(alignment,
                                data.eq(data_sr[0:32]),
                                charisk.eq(charisk_sr[0:4])
                        ).Else(

diff --git a/lib/sata/phy/k7sataphy/gtx.py b/lib/sata/phy/k7sataphy/gtx.py
index 1d1077398b106e29a37d118e0fc83f0b046d3278..084266fd8a94ff3bc27b4e5d3a42284a83219363 100644 (file)
--- a/lib/sata/phy/k7sataphy/gtx.py
+++ b/lib/sata/phy/k7sataphy/gtx.py
@@ -87,7 +87,7 @@ class K7SATAPHYGTX(Module):
 
                cdr_config = {
                        "SATA1" :       0x0380008BFF40100008,
-                       "SATA2" :       0x0380008BFF40200008,
+                       "SATA2" :       0x0388008BFF40200008,
                        "SATA3" :       0X0380008BFF10200010
                }
                rxcdr_cfg = cdr_config[default_speed]
@@ -185,32 +185,32 @@ class K7SATAPHYGTX(Module):
                                        "p_ALIGN_PCOMMA_VALUE":0b0101111100,
                                        "p_SHOW_REALIGN_COMMA":"FALSE",
                                        "p_RXSLIDE_AUTO_WAIT":7,
-                                       "p_RXSLIDE_MODE":"OFF",
+                                       "p_RXSLIDE_MODE":"PCS",
                                        "p_RX_SIG_VALID_DLY":10,
 
                                # RX 8B/10B Decoder Attributes
                                        "p_RX_DISPERR_SEQ_MATCH":"TRUE",
                                        "p_DEC_MCOMMA_DETECT":"TRUE",
                                        "p_DEC_PCOMMA_DETECT":"TRUE",
-                                       "p_DEC_VALID_COMMA_ONLY":"TRUE",
+                                       "p_DEC_VALID_COMMA_ONLY":"FALSE",
 
                                # RX Clock Correction Attributes
                                        "p_CBCC_DATA_SOURCE_SEL":"DECODED",
                                        "p_CLK_COR_SEQ_2_USE":"FALSE",
                                        "p_CLK_COR_KEEP_IDLE":"FALSE",
-                                       "p_CLK_COR_MAX_LAT":35,
-                                       "p_CLK_COR_MIN_LAT":28,
+                                       "p_CLK_COR_MAX_LAT":9,
+                                       "p_CLK_COR_MIN_LAT":7,
                                        "p_CLK_COR_PRECEDENCE":"TRUE",
                                        "p_CLK_COR_REPEAT_WAIT":0,
-                                       "p_CLK_COR_SEQ_LEN":4,
+                                       "p_CLK_COR_SEQ_LEN":1,
                                        "p_CLK_COR_SEQ_1_ENABLE":ones(4),
-                                       "p_CLK_COR_SEQ_1_1":0b0110111100,
-                                       "p_CLK_COR_SEQ_1_2":0b0001001010,
-                                       "p_CLK_COR_SEQ_1_3":0b0001001010,
-                                       "p_CLK_COR_SEQ_1_4":0b0001111011,
+                                       "p_CLK_COR_SEQ_1_1":0b0100000000,
+                                       "p_CLK_COR_SEQ_1_2":0b0000000000,
+                                       "p_CLK_COR_SEQ_1_3":0b0000000000,
+                                       "p_CLK_COR_SEQ_1_4":0b0000000000,
                                        "p_CLK_CORRECT_USE":"FALSE",
                                        "p_CLK_COR_SEQ_2_ENABLE":ones(4),
-                                       "p_CLK_COR_SEQ_2_1":0,
+                                       "p_CLK_COR_SEQ_2_1":0b0100000000,
                                        "p_CLK_COR_SEQ_2_2":0,
                                        "p_CLK_COR_SEQ_2_3":0,
                                        "p_CLK_COR_SEQ_2_4":0,
@@ -295,7 +295,7 @@ class K7SATAPHYGTX(Module):
                                        "p_RXPH_CFG":0,
                                        "p_RXPHDLY_CFG":0x084820,
                                        "p_RXPH_MONITOR_SEL":0,
-                                       "p_RX_XCLK_SEL":"RXREC",
+                                       "p_RX_XCLK_SEL":"RXUSR",
                                        "p_RX_DDI_SEL":0,
                                        "p_RX_DEFER_RESET_BUF_EN":"TRUE",
 

diff --git a/test/test_stim.py b/test/test_stim.py
index b69665171bf23784c4ecc7918096b008e1b9e865..f3ba8726c19fc9730540d3ed87404f6bc73d8d55 100644 (file)
--- a/test/test_stim.py
+++ b/test/test_stim.py
@@ -33,7 +33,7 @@ for i in range(16):
        rx = regs.stim_rx_primitive.read()
        print("rx: %08x %s" %(rx, decode_primitive(rx)))
        time.sleep(0.1)
-#regs.stim_tx_primitive.write(primitives["R_RDY"])
+#regs.stim_tx_primitive.write(primitives["X_RDY"])
 for i in range(16):
        rx = regs.stim_rx_primitive.read()
        print("rx: %08x %s" %(rx, decode_primitive(rx)))