add notes about fmv[ft]g similarity to m[tf]vsrd

diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
index 5943161ef4fe55ad6aaa913051b3e5ce393e1afb..550f9e8902192aac6c8a2c3b739ca2dfc9f0e1c7 100644 (file)
--- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
+++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
@@ -53,7 +53,9 @@ File to another.
 
 Move a 64-bit float from a FPR to a GPR, just copying bits of the IEEE 754
 representation directly. This is equivalent to `stfd` followed by `ld`.
-As `fmvtg` is just copying bits, `FPSCR` is not affected in any way.
+As `fmvtg` is just copying bits, `FPSCR` is not affected in any way. `fmvtg` is
+similar to `mfvsrd`, except doesn't require VSX, which is useful for SFFS
+implementations.
 
 Rc=1 tests RT and sets CR0, exactly like all other Scalar Fixed-Point
 operations.
@@ -115,7 +117,9 @@ Special Registers altered:
 
 move a 64-bit float from a GPR to a FPR, just copying bits of the IEEE 754
 representation directly. This is equivalent to `std` followed by `lfd`.
-As `fmvfg` is just copying bits, `FPSCR` is not affected in any way.
+As `fmvfg` is just copying bits, `FPSCR` is not affected in any way. `fmvfg` is
+similar to `mtvsrd`, except doesn't require VSX, which is useful for SFFS
+implementations.
 
 Special Registers altered: