Rename remaining `wrap` methods to `cast`.

Following commit d72d4a55.

diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py
index f19160bdc60e26571d14a512a19f0802d8325d31..efd232d9ff2c0e5654ecbfde7c0aedacd794f103 100644 (file)
--- a/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@ -1255,10 +1255,16 @@ class Statement:
     def __init__(self, *, src_loc_at=0):
         self.src_loc = tracer.get_src_loc(1 + src_loc_at)
 
+    # TODO(nmigen-0.2): remove this
+    @classmethod
+    @deprecated("instead of `Statement.wrap`, use `Statement.cast`")
+    def wrap(cls, obj):
+        return cls.cast(obj)
+
     @staticmethod
-    def wrap(obj):
+    def cast(obj):
         if isinstance(obj, Iterable):
-            return _StatementList(sum((Statement.wrap(e) for e in obj), []))
+            return _StatementList(sum((Statement.cast(e) for e in obj), []))
         else:
             if isinstance(obj, Statement):
                 return _StatementList([obj])
@@ -1359,7 +1365,7 @@ class Switch(Statement):
                 new_keys = (*new_keys, key)
             if not isinstance(stmts, Iterable):
                 stmts = [stmts]
-            self.cases[new_keys] = Statement.wrap(stmts)
+            self.cases[new_keys] = Statement.cast(stmts)
             if orig_keys in case_src_locs:
                 self.case_src_locs[new_keys] = case_src_locs[orig_keys]
 

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 6a14edf6bbc3a319521bd81986df77a1ae2b9c74..87bbf13cf2bd4948f0d1c8585e45b25fbb918c14 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -131,7 +131,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
         self.submodules    = _ModuleBuilderSubmodules(self)
         self.domains       = _ModuleBuilderDomainSet(self)
 
-        self._statements   = Statement.wrap([])
+        self._statements   = Statement.cast([])
         self._ctrl_context = None
         self._ctrl_stack   = []
 
@@ -433,7 +433,7 @@ class Module(_ModuleBuilderRoot, Elaboratable):
         while len(self._ctrl_stack) > self.domain._depth:
             self._pop_ctrl()
 
-        for assign in Statement.wrap(assigns):
+        for assign in Statement.cast(assigns):
             if not compat_mode and not isinstance(assign, (Assign, Assert, Assume, Cover)):
                 raise SyntaxError(
                     "Only assignments and property checks may be appended to d.{}"

diff --git a/nmigen/hdl/ir.py b/nmigen/hdl/ir.py
index de65d312f4c76b22a007f5a0982d4f95d9384cfc..b77a340246f9014e1646a4dc02d23760f4afa12f 100644 (file)
--- a/nmigen/hdl/ir.py
+++ b/nmigen/hdl/ir.py
@@ -144,7 +144,7 @@ class Fragment:
         yield from self.domains
 
     def add_statements(self, *stmts):
-        self.statements += Statement.wrap(stmts)
+        self.statements += Statement.cast(stmts)
 
     def add_subfragment(self, subfragment, name=None):
         assert isinstance(subfragment, Fragment)

diff --git a/nmigen/hdl/rec.py b/nmigen/hdl/rec.py
index 3ec1151979b3e70fa9fd59e9c7108f0caa82ef37..8a84e178f4aa35f4cecb0dcd70b066259cd7be88 100644 (file)
--- a/nmigen/hdl/rec.py
+++ b/nmigen/hdl/rec.py
@@ -3,7 +3,7 @@ from collections import OrderedDict
 from functools import reduce
 
 from .. import tracer
-from ..tools import union
+from ..tools import union, deprecated
 from .ast import *
 
 
@@ -19,11 +19,17 @@ DIR_FANIN  = Direction.FANIN
 
 class Layout:
     @staticmethod
-    def wrap(obj, src_loc_at=0):
+    def cast(obj, *, src_loc_at=0):
         if isinstance(obj, Layout):
             return obj
         return Layout(obj, src_loc_at=1 + src_loc_at)
 
+    # TODO(nmigen-0.2): remove this
+    @classmethod
+    @deprecated("instead of `Layout.wrap`, use `Layout.cast`")
+    def wrap(cls, obj, *, src_loc_at=0):
+        return cls.cast(obj, src_loc_at=1 + src_loc_at)
+
     def __init__(self, fields, *, src_loc_at=0):
         self.fields = OrderedDict()
         for field in fields:
@@ -35,7 +41,7 @@ class Layout:
                 name, shape = field
                 direction = DIR_NONE
                 if isinstance(shape, list):
-                    shape = Layout.wrap(shape)
+                    shape = Layout.cast(shape)
             else:
                 name, shape, direction = field
                 if not isinstance(direction, Direction):
@@ -115,7 +121,7 @@ class Record(Value):
                 return b
             return "{}__{}".format(a, b)
 
-        self.layout = Layout.wrap(layout, src_loc_at=1 + src_loc_at)
+        self.layout = Layout.cast(layout, src_loc_at=1 + src_loc_at)
         self.fields = OrderedDict()
         for field_name, field_shape, field_dir in self.layout:
             if fields is not None and field_name in fields:

diff --git a/nmigen/test/test_hdl_rec.py b/nmigen/test/test_hdl_rec.py
index 219c8f0daf9dd3fa94bbfaffea6f61dfe2466d0d..2e84107aa9869a7c9056ec80184a399c2f6c00d8 100644 (file)
--- a/nmigen/test/test_hdl_rec.py
+++ b/nmigen/test/test_hdl_rec.py
@@ -13,7 +13,7 @@ class UnsignedEnum(Enum):
 
 class LayoutTestCase(FHDLTestCase):
     def test_fields(self):
-        layout = Layout.wrap([
+        layout = Layout.cast([
             ("cyc",  1),
             ("data", signed(32)),
             ("stb",  1, DIR_FANOUT),
@@ -34,7 +34,7 @@ class LayoutTestCase(FHDLTestCase):
         self.assertEqual(sublayout["b"], ((1, False), DIR_NONE))
 
     def test_enum_field(self):
-        layout = Layout.wrap([
+        layout = Layout.cast([
             ("enum", UnsignedEnum),
             ("enum_dir", UnsignedEnum, DIR_FANOUT),
         ])
@@ -42,18 +42,18 @@ class LayoutTestCase(FHDLTestCase):
         self.assertEqual(layout["enum_dir"], ((2, False), DIR_FANOUT))
 
     def test_range_field(self):
-        layout = Layout.wrap([
+        layout = Layout.cast([
             ("range", range(0, 7)),
         ])
         self.assertEqual(layout["range"], ((3, False), DIR_NONE))
 
     def test_slice_tuple(self):
-        layout = Layout.wrap([
+        layout = Layout.cast([
             ("a", 1),
             ("b", 2),
             ("c", 3)
         ])
-        expect = Layout.wrap([
+        expect = Layout.cast([
             ("a", 1),
             ("c", 3)
         ])
@@ -63,29 +63,29 @@ class LayoutTestCase(FHDLTestCase):
         with self.assertRaises(TypeError,
                 msg="Field (1,) has invalid layout: should be either (name, shape) or "
                     "(name, shape, direction)"):
-            Layout.wrap([(1,)])
+            Layout.cast([(1,)])
 
     def test_wrong_name(self):
         with self.assertRaises(TypeError,
                 msg="Field (1, 1) has invalid name: should be a string"):
-            Layout.wrap([(1, 1)])
+            Layout.cast([(1, 1)])
 
     def test_wrong_name_duplicate(self):
         with self.assertRaises(NameError,
                 msg="Field ('a', 2) has a name that is already present in the layout"):
-            Layout.wrap([("a", 1), ("a", 2)])
+            Layout.cast([("a", 1), ("a", 2)])
 
     def test_wrong_direction(self):
         with self.assertRaises(TypeError,
                 msg="Field ('a', 1, 0) has invalid direction: should be a Direction "
                     "instance like DIR_FANIN"):
-            Layout.wrap([("a", 1, 0)])
+            Layout.cast([("a", 1, 0)])
 
     def test_wrong_shape(self):
         with self.assertRaises(TypeError,
                 msg="Field ('a', 'x') has invalid shape: should be castable to Shape or "
                     "a list of fields of a nested record"):
-            Layout.wrap([("a", "x")])
+            Layout.cast([("a", "x")])
 
 
 class RecordTestCase(FHDLTestCase):

diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index ed837a321ff3034c08f362b147ff582a45dab230..d5eac8a9f40e28c27b15e7c24b59cb1a1fcd0f5c 100644 (file)
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -22,7 +22,7 @@ class SimulatorUnitTestCase(FHDLTestCase):
         stmt = stmt(osig, *isigs)
         frag = Fragment()
         frag.add_statements(stmt)
-        for signal in flatten(s._lhs_signals() for s in Statement.wrap(stmt)):
+        for signal in flatten(s._lhs_signals() for s in Statement.cast(stmt)):
             frag.add_driver(signal)
 
         with Simulator(frag,

diff --git a/nmigen/test/tools.py b/nmigen/test/tools.py
index 0329e43b047bcf9f195d37aaa5a4a977cf8db47b..c3907ce8b920a1231228961d471fb7d9f858f205 100644 (file)
--- a/nmigen/test/tools.py
+++ b/nmigen/test/tools.py
@@ -20,7 +20,7 @@ __all__ = ["FHDLTestCase"]
 class FHDLTestCase(unittest.TestCase):
     def assertRepr(self, obj, repr_str):
         if isinstance(obj, list):
-            obj = Statement.wrap(obj)
+            obj = Statement.cast(obj)
         def prepare_repr(repr_str):
             repr_str = re.sub(r"\s+",   " ",  repr_str)
             repr_str = re.sub(r"\( (?=\()", "(", repr_str)