freedreno/ir3: optimize sam.s2en to sam

Detect when sampler/texture idx are immediate and switch to non s2en
encoding.

Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index f00daebabf5dbf19ee7960cd99421b96bca32ca9..ac126d5b98f94692adf8aaea9a34609fa3cdf9b1 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -29,12 +29,13 @@
 #include "ir3_compiler.h"
 
 static const struct debug_named_value shader_debug_options[] = {
-               {"vs", IR3_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
-               {"fs", IR3_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
-               {"cs", IR3_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
-               {"disasm",  IR3_DBG_DISASM, "Dump NIR and adreno shader disassembly"},
-               {"optmsgs", IR3_DBG_OPTMSGS,"Enable optimizer debug messages"},
-               DEBUG_NAMED_VALUE_END
+       {"vs",         IR3_DBG_SHADER_VS,  "Print shader disasm for vertex shaders"},
+       {"fs",         IR3_DBG_SHADER_FS,  "Print shader disasm for fragment shaders"},
+       {"cs",         IR3_DBG_SHADER_CS,  "Print shader disasm for compute shaders"},
+       {"disasm",     IR3_DBG_DISASM,     "Dump NIR and adreno shader disassembly"},
+       {"optmsgs",    IR3_DBG_OPTMSGS,    "Enable optimizer debug messages"},
+       {"forces2en",  IR3_DBG_FORCES2EN,  "Force s2en mode for tex sampler instructions"},
+       DEBUG_NAMED_VALUE_END
 };
 
 DEBUG_GET_ONCE_FLAGS_OPTION(ir3_shader_debug, "IR3_SHADER_DEBUG", shader_debug_options, 0)

diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h
index e2336062b2931d9d0e9181175fc35a8a3c338b65..1bc59970c4ece86611fd31afd19b49114a01f8ea 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler.h
+++ b/src/freedreno/ir3/ir3_compiler.h
@@ -76,6 +76,7 @@ enum ir3_shader_debug {
        IR3_DBG_SHADER_CS = 0x04,
        IR3_DBG_DISASM    = 0x08,
        IR3_DBG_OPTMSGS   = 0x10,
+       IR3_DBG_FORCES2EN = 0x20,
 };
 
 extern enum ir3_shader_debug ir3_shader_debug;

diff --git a/src/freedreno/ir3/ir3_cp.c b/src/freedreno/ir3/ir3_cp.c
index bbc85b1219848a6d5f2d64cd48a7cf2ad11a6b29..28ba43f09eede29fea92acd40bb1cbc73eafc3ce 100644 (file)
--- a/src/freedreno/ir3/ir3_cp.c
+++ b/src/freedreno/ir3/ir3_cp.c
@@ -613,6 +613,34 @@ instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
                        break;
                }
        }
+
+       /* Handle converting a sam.s2en (taking samp/tex idx params via
+        * register) into a normal sam (encoding immediate samp/tex idx)
+        * if they are immediate.  This saves some instructions and regs
+        * in the common case where we know samp/tex at compile time:
+        */
+       if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
+                       !(ir3_shader_debug & IR3_DBG_FORCES2EN)) {
+               /* The first src will be a fan-in (collect), if both of it's
+                * two sources are mov from imm, then we can
+                */
+               struct ir3_instruction *samp_tex = ssa(instr->regs[1]);
+
+               debug_assert(samp_tex->opc == OPC_META_FI);
+
+               struct ir3_instruction *samp = ssa(samp_tex->regs[1]);
+               struct ir3_instruction *tex  = ssa(samp_tex->regs[2]);
+
+               if ((samp->opc == OPC_MOV) &&
+                               (samp->regs[1]->flags & IR3_REG_IMMED) &&
+                               (tex->opc == OPC_MOV) &&
+                               (tex->regs[1]->flags & IR3_REG_IMMED)) {
+                       instr->flags &= ~IR3_INSTR_S2EN;
+                       instr->cat5.samp = samp->regs[1]->iim_val;
+                       instr->cat5.tex  = tex->regs[1]->iim_val;
+                       instr->regs[1]->instr = NULL;
+               }
+       }
 }
 
 void