arm: Add testsuite checks for asm-flag

Inspired by the tests in gcc.target/i386.  Testing code generation,
diagnostics, and execution.

	* gcc.target/arm/asm-flag-1.c: New test.
	* gcc.target/arm/asm-flag-3.c: New test.
	* gcc.target/arm/asm-flag-5.c: New test.
	* gcc.target/arm/asm-flag-6.c: New test.

From-SVN: r278227

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e0535b32247126341ce321d51c7544a611e9c9d8..494c9eed8bd688bd6b8c98989811ae70ac440448 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2019-11-14  Richard Henderson  <richard.henderson@linaro.org>
+
+       * gcc.target/arm/asm-flag-1.c: New test.
+       * gcc.target/arm/asm-flag-3.c: New test.
+       * gcc.target/arm/asm-flag-5.c: New test.
+       * gcc.target/arm/asm-flag-6.c: New test.
+
 2019-11-14  Jan Hubicka  <jh@suse.cz>
 
        * gcc.dg/ipa/inline-9.c: New testcase.

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
new file mode 100644 (file)
index 0000000..9707ebf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c
@@ -0,0 +1,36 @@
+/* Test the valid @cc<cc> asm flag outputs.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#ifndef __GCC_ASM_FLAG_OUTPUTS__
+#error "missing preprocessor define"
+#endif
+
+void f(char *out)
+{
+  asm(""
+      : "=@ccne"(out[0]), "=@cceq"(out[1]),
+       "=@cccs"(out[2]), "=@cccc"(out[3]),
+       "=@ccmi"(out[4]), "=@ccpl"(out[5]),
+       "=@ccvs"(out[6]), "=@ccvc"(out[7]),
+       "=@cchi"(out[8]), "=@ccls"(out[9]),
+       "=@ccge"(out[10]), "=@cclt"(out[11]),
+       "=@ccgt"(out[12]), "=@ccle"(out[13]),
+       "=@cchs"(out[14]), "=@cclo"(out[15]));
+}
+
+/* There will be at least one of each.  */
+/* { dg-final { scan-assembler "movne" } } */
+/* { dg-final { scan-assembler "moveq" } } */
+/* { dg-final { scan-assembler "movcs" } } */
+/* { dg-final { scan-assembler "movcc" } } */
+/* { dg-final { scan-assembler "movmi" } } */
+/* { dg-final { scan-assembler "movpl" } } */
+/* { dg-final { scan-assembler "movvs" } } */
+/* { dg-final { scan-assembler "movvc" } } */
+/* { dg-final { scan-assembler "movhi" } } */
+/* { dg-final { scan-assembler "movls" } } */
+/* { dg-final { scan-assembler "movge" } } */
+/* { dg-final { scan-assembler "movls" } } */
+/* { dg-final { scan-assembler "movgt" } } */
+/* { dg-final { scan-assembler "movle" } } */

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
new file mode 100644 (file)
index 0000000..e84e343
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c
@@ -0,0 +1,38 @@
+/* Test some of the valid @cc<cc> asm flag outputs.  */
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+#define DO(C) \
+void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); }
+
+DO(ne)
+DO(eq)
+DO(cs)
+DO(cc)
+DO(hs)
+DO(lo)
+DO(mi)
+DO(pl)
+DO(vs)
+DO(vc)
+DO(hi)
+DO(ls)
+DO(ge)
+DO(lt)
+DO(gt)
+DO(le)
+
+/* { dg-final { scan-assembler "bne" } } */
+/* { dg-final { scan-assembler "beq" } } */
+/* { dg-final { scan-assembler "bcs" } } */
+/* { dg-final { scan-assembler "bcc" } } */
+/* { dg-final { scan-assembler "bmi" } } */
+/* { dg-final { scan-assembler "bpl" } } */
+/* { dg-final { scan-assembler "bvs" } } */
+/* { dg-final { scan-assembler "bvc" } } */
+/* { dg-final { scan-assembler "bhi" } } */
+/* { dg-final { scan-assembler "bls" } } */
+/* { dg-final { scan-assembler "bge" } } */
+/* { dg-final { scan-assembler "blt" } } */
+/* { dg-final { scan-assembler "bgt" } } */
+/* { dg-final { scan-assembler "ble" } } */

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
new file mode 100644 (file)
index 0000000..4d4394e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c
@@ -0,0 +1,30 @@
+/* Test error conditions of asm flag outputs.  */
+/* { dg-do compile } */
+/* { dg-options "" } */
+
+void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); }
+void f_c(void) { char x; asm("" : "=@cccc"(x)); }
+void f_s(void) { short x; asm("" : "=@cccc"(x)); }
+void f_i(void) { int x; asm("" : "=@cccc"(x)); }
+void f_l(void) { long x; asm("" : "=@cccc"(x)); }
+void f_ll(void) { long long x; asm("" : "=@cccc"(x)); }
+
+void f_f(void)
+{
+  float x;
+  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+void f_d(void)
+{
+  double x;
+  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}
+
+struct S { int x[3]; };
+
+void f_S(void)
+{
+  struct S x;
+  asm("" : "=@cccc"(x)); /* { dg-error invalid type } */
+}

diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
new file mode 100644 (file)
index 0000000..09174e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c
@@ -0,0 +1,62 @@
+/* Executable testcase for 'output flags.'  */
+/* { dg-do run } */
+
+int test_bits (long nzcv)
+{
+  long n, z, c, v;
+
+  __asm__ ("msr APSR_nzcvq, %[in]"
+          : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v)
+          : [in] "r"(nzcv << 28));
+
+  return n * 8 + z * 4 + c * 2 + v == nzcv;
+}
+       
+int test_cmps (long x, long y)
+{
+  long gt, lt, ge, le;
+
+  __asm__ ("cmp %[x], %[y]"
+          : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le)
+          : [x] "r"(x), [y] "r"(y));
+
+  return (gt == (x > y)
+         && lt == (x < y)
+         && ge == (x >= y)
+         && le == (x <= y));
+}
+
+int test_cmpu (unsigned long x, unsigned long y)
+{
+  long gt, lt, ge, le;
+
+  __asm__ ("cmp %[x], %[y]"
+          : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le)
+          : [x] "r"(x), [y] "r"(y));
+
+  return (gt == (x > y)
+         && lt == (x < y)
+         && ge == (x >= y)
+         && le == (x <= y));
+}
+
+int main ()
+{
+  long i, j;
+
+  for (i = 0; i < 16; ++i)
+    if (!test_bits (i))
+      __builtin_abort ();
+
+  for (i = -1; i <= 1; ++i)
+    for (j = -1; j <= 1; ++j)
+      if (!test_cmps (i, j))
+        __builtin_abort ();
+
+  for (i = 0; i <= 2; ++i)
+    for (j = 0; j <= 2; ++j)
+      if (!test_cmpu (i, j))
+        __builtin_abort ();
+
+  return 0;
+}