re PR rtl-optimization/84071 (wrong elimination of zero-extension after sign-extended...

	PR rtl-optimization/84071
	* doc/tm.texi.in (WORD_REGISTER_OPERATIONS): Add explicit case.
	* doc/tm.texi: Regenerate.

From-SVN: r257237

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b1e0891ba8c7c5bd4e01911e696cd6bf6eea775d..40d570bbfc88b76057558ea8c627869f369b49c3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-01-31  Eric Botcazou  <ebotcazou@adacore.com>
+
+       PR rtl-optimization/84071
+       * doc/tm.texi.in (WORD_REGISTER_OPERATIONS): Add explicit case.
+       * doc/tm.texi: Regenerate.
+
 2018-01-31  Richard Biener  <rguenther@suse.de>
 
        PR tree-optimization/84132

diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 2f317b5a3681c7439f48d1b97409774b7c63c413..ddf48cb4b4d2f491d1c13ef8d4582cc5d78fbbf9 100644 (file)
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10766,8 +10766,12 @@ five otherwise.  This is best for most machines.
 
 @defmac WORD_REGISTER_OPERATIONS
 Define this macro to 1 if operations between registers with integral mode
-smaller than a word are always performed on the entire register.
-Most RISC machines have this property and most CISC machines do not.
+smaller than a word are always performed on the entire register.  To be
+more explicit, if you start with a pair of @code{word_mode} registers with
+known values and you do a subword, for example @code{QImode}, addition on
+the low part of the registers, then the compiler may consider that the
+result has a known value in @code{word_mode} too if the macro is defined
+to 1.  Most RISC machines have this property and most CISC machines do not.
 @end defmac
 
 @deftypefn {Target Hook} {unsigned int} TARGET_MIN_ARITHMETIC_PRECISION (void)

diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in
index 2a42038829d9980865c81bcc3fc4fa161e4a9780..0aab45f4992c45b5393a4b8bfd3bfcdedcbdc0ec 100644 (file)
--- a/gcc/doc/tm.texi.in
+++ b/gcc/doc/tm.texi.in
@@ -7376,8 +7376,12 @@ is in effect.
 
 @defmac WORD_REGISTER_OPERATIONS
 Define this macro to 1 if operations between registers with integral mode
-smaller than a word are always performed on the entire register.
-Most RISC machines have this property and most CISC machines do not.
+smaller than a word are always performed on the entire register.  To be
+more explicit, if you start with a pair of @code{word_mode} registers with
+known values and you do a subword, for example @code{QImode}, addition on
+the low part of the registers, then the compiler may consider that the
+result has a known value in @code{word_mode} too if the macro is defined
+to 1.  Most RISC machines have this property and most CISC machines do not.
 @end defmac
 
 @hook TARGET_MIN_ARITHMETIC_PRECISION