r600g: export one component per pixel + r7xx uncompression shader
authorJerome Glisse <jglisse@redhat.com>
Mon, 23 Aug 2010 19:39:39 +0000 (15:39 -0400)
committerJerome Glisse <jglisse@redhat.com>
Mon, 23 Aug 2010 19:42:32 +0000 (15:42 -0400)
We need to always at least export one component (wether it's depth
or color. Add valid r7xx shader program for depth decompression.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
src/gallium/drivers/r600/r600_blit.c
src/gallium/drivers/r600/r600_screen.c
src/gallium/drivers/r600/r600_screen.h
src/gallium/drivers/r600/r600_shader.c
src/gallium/drivers/r600/r600_state.c

index 1a975da4bdb51398db5e2465beb0d8c2a010f7f8..72175fbbd5e4c4bdc352cfb68b237cdbccee64e8 100644 (file)
@@ -242,7 +242,7 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
 {
        struct radeon_state *rstate;
        struct radeon_bo *bo;
-       u32 shader_bc[] = {
+       u32 shader_bc_r600[] = {
                0x00000004, 0x81000400,
                0x00000008, 0xA01C0000,
                0xC001A03C, 0x94000688,
@@ -260,6 +260,24 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
                0x00000802, 0x40801910,
                0x80000C02, 0x60801910
        };
+       u32 shader_bc_r700[] = {
+               0x00000004, 0x81000400,
+               0x00000008, 0xA01C0000,
+               0xC001A03C, 0x94000688,
+               0xC0024000, 0x94200688,
+               0x7C000000, 0x002D1001,
+               0x00080000, 0x00000000,
+               0x7C000100, 0x002D1002,
+               0x00080000, 0x00000000,
+               0x00000001, 0x00600C90,
+               0x00000401, 0x20600C90,
+               0x00000801, 0x40600C90,
+               0x80000C01, 0x60600C90,
+               0x00000002, 0x00800C90,
+               0x00000402, 0x20800C90,
+               0x00000802, 0x40800C90,
+               0x80000C02, 0x60800C90
+       };
 
        /* simple shader */
        bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
@@ -270,7 +288,19 @@ static struct radeon_state *r600_blit_state_vs_shader(struct r600_screen *rscree
                radeon_bo_decref(rscreen->rw, bo);
                return NULL;
        }
-       memcpy(bo->data, shader_bc, 128);
+       switch (rscreen->chip_class) {
+       case R600:
+               memcpy(bo->data, shader_bc_r600, 128);
+               break;
+       case R700:
+               memcpy(bo->data, shader_bc_r700, 128);
+               break;
+       default:
+               R600_ERR("unsupported chip family\n");
+               radeon_bo_unmap(rscreen->rw, bo);
+               radeon_bo_decref(rscreen->rw, bo);
+               return NULL;
+       }
        radeon_bo_unmap(rscreen->rw, bo);
 
        rstate = radeon_state(rscreen->rw, R600_VS_SHADER_TYPE, R600_VS_SHADER);
@@ -303,7 +333,7 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
 {
        struct radeon_state *rstate;
        struct radeon_bo *bo;
-       u32 shader_bc[] = {
+       u32 shader_bc_r600[] = {
                0x00000002, 0xA00C0000,
                0xC0008000, 0x94200688,
                0x00000000, 0x00201910,
@@ -311,6 +341,14 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
                0x00000800, 0x40201910,
                0x80000C00, 0x60201910
        };
+       u32 shader_bc_r700[] = {
+               0x00000002, 0xA00C0000,
+               0xC0008000, 0x94200688,
+               0x00000000, 0x00200C90,
+               0x00000400, 0x20200C90,
+               0x00000800, 0x40200C90,
+               0x80000C00, 0x60200C90
+       };
 
        /* simple shader */
        bo = radeon_bo(rscreen->rw, 0, 128, 4096, NULL);
@@ -321,7 +359,19 @@ static struct radeon_state *r600_blit_state_ps_shader(struct r600_screen *rscree
        if (radeon_bo_map(rscreen->rw, bo)) {
                return NULL;
        }
-       memcpy(bo->data, shader_bc, 48);
+       switch (rscreen->chip_class) {
+       case R600:
+               memcpy(bo->data, shader_bc_r600, 48);
+               break;
+       case R700:
+               memcpy(bo->data, shader_bc_r700, 48);
+               break;
+       default:
+               R600_ERR("unsupported chip family\n");
+               radeon_bo_unmap(rscreen->rw, bo);
+               radeon_bo_decref(rscreen->rw, bo);
+               return NULL;
+       }
        radeon_bo_unmap(rscreen->rw, bo);
 
        rstate = radeon_state(rscreen->rw, R600_PS_SHADER_TYPE, R600_PS_SHADER);
index cdaca9ed7dbf487f5027a4118089ebef8c0fb7ac..135843295706826d73c1b68536886410b6c31705 100644 (file)
@@ -234,11 +234,34 @@ static void r600_destroy_screen(struct pipe_screen* pscreen)
 struct pipe_screen *r600_screen_create(struct radeon *rw)
 {
        struct r600_screen* rscreen;
+       enum radeon_family family = radeon_get_family(rw);
 
        rscreen = CALLOC_STRUCT(r600_screen);
        if (rscreen == NULL) {
                return NULL;
        }
+
+       switch (family) {
+       case CHIP_R600:
+       case CHIP_RV610:
+       case CHIP_RV630:
+       case CHIP_RV670:
+       case CHIP_RV620:
+       case CHIP_RV635:
+       case CHIP_RS780:
+       case CHIP_RS880:
+               rscreen->chip_class = R600;
+               break;
+       case CHIP_RV770:
+       case CHIP_RV730:
+       case CHIP_RV710:
+       case CHIP_RV740:
+               rscreen->chip_class = R700;
+               break;
+       default:
+               FREE(rscreen);
+               return NULL;
+       }
        rscreen->rw = rw;
        rscreen->screen.winsys = (struct pipe_winsys*)rw;
        rscreen->screen.destroy = r600_destroy_screen;
index 5e82ac8e234a7480b134e0d2f5cb3ff672c9fdc8..438976f654a25f347aa0710ea4b93d904744a883 100644 (file)
@@ -42,9 +42,16 @@ struct r600_transfer {
        struct pipe_resource            *linear_texture;
 };
 
+enum chip_class {
+       R600,
+       R700,
+       EVERGREEN,
+};
+
 struct r600_screen {
        struct pipe_screen              screen;
        struct radeon                   *rw;
+       enum chip_class                 chip_class;
 };
 
 static INLINE struct r600_screen *r600_screen(struct pipe_screen *screen)
index 5cdbe2bfe8084b4afea225d0ba46e51907f53cdb..b20a5a11bec211cc201cc88415cb8d6173ba31f4 100644 (file)
@@ -191,6 +191,10 @@ static int r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_context_sta
                        num_cout++;
                }
        }
+       if (!exports_ps) {
+               /* always at least export 1 component per pixel */
+               exports_ps = 2;
+       }
        state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_0] = S_0286CC_NUM_INTERP(rshader->ninput) |
                                                        S_0286CC_PERSP_GRADIENT_ENA(1);
        state->states[R600_PS_SHADER__SPI_PS_IN_CONTROL_1] = 0x00000000;
index c3ef6267b2586a042a4774dc97b7bdc488986c81..12a61cacdad382095e61912cc3864de0420d8636 100644 (file)
@@ -775,7 +775,7 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
        rtex = (struct r600_resource_texture*)state->zsbuf->texture;
        rtex->tilled = 1;
        rtex->array_mode = 2;
-       rtex->tile_type = 0;
+       rtex->tile_type = 1;
        rtex->depth = 1;
        rbuffer = &rtex->resource;