using namespace llvm;
namespace {
- class AMDGPUConvertToISAPass : public MachineFunctionPass {
- private:
- static char ID;
- TargetMachine &TM;
+class AMDGPUConvertToISAPass : public MachineFunctionPass {
- void lowerFLT(MachineInstr &MI);
+private:
+ static char ID;
+ TargetMachine &TM;
- public:
- AMDGPUConvertToISAPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm) { }
+public:
+ AMDGPUConvertToISAPass(TargetMachine &tm) :
+ MachineFunctionPass(ID), TM(tm) { }
- virtual bool runOnMachineFunction(MachineFunction &MF);
+ virtual bool runOnMachineFunction(MachineFunction &MF);
+};
- };
} // End anonymous namespace
char AMDGPUConvertToISAPass::ID = 0;
void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
MachineFunction * MF, MachineRegisterInfo & MRI,
- const struct TargetInstrInfo * TII, unsigned reg) const
+ const TargetInstrInfo * TII, unsigned reg) const
{
- AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg());
+ AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg());
}
class AMDGPUTargetLowering : public AMDILTargetLowering
{
protected:
+
+ /// addLiveIn - This functions adds reg to the live in list of the entry block
+ /// and emits a copy from reg to MI.getOperand(0).
+ ///
+ // Some registers are loaded with values before the program
+ /// begins to execute. The loading of these values is modeled with pseudo
+ /// instructions which are lowered using this function.
void addLiveIn(MachineInstr * MI, MachineFunction * MF,
- MachineRegisterInfo & MRI, const struct TargetInstrInfo * TII,
+ MachineRegisterInfo & MRI, const TargetInstrInfo * TII,
unsigned reg) const;
public:
};
-} /* End namespace llvm */
+} // End namespace llvm
-#endif /* AMDGPUISELLOWERING_H */
+#endif // AMDGPUISELLOWERING_H
const AMDGPURegisterInfo & RI = getRegisterInfo();
unsigned ISAOpcode = getISAOpcode(MI.getOpcode());
- /* Create the new instruction */
+ // Create the new instruction
newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(ISAOpcode));
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
MachineOperand &MO = MI.getOperand(i);
- /* Convert dst regclass to one that is supported by the ISA */
+ // Convert dst regclass to one that is supported by the ISA
if (MO.isReg() && MO.isDef()) {
if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg());
MRI.setRegClass(MO.getReg(), newRegClass);
}
}
- /* Add the operand to the new instruction */
+ // Add the operand to the new instruction
newInstr.addOperand(MO);
}
//
//===----------------------------------------------------------------------===//
//
-// This file contains the definitoin of a TargetInstrInfo class that is common
+// This file contains the definition of a TargetInstrInfo class that is common
// to all AMD GPUs.
//
//===----------------------------------------------------------------------===//
virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
+ /// getISAOpcode - This function takes an AMDIL opcode as an argument and
+ /// returns an equivalent ISA opcode.
virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
+ /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
+ /// MachineInstr
virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const;
using namespace llvm;
namespace {
- class AMDGPULowerInstructionsPass : public MachineFunctionPass {
- private:
- static char ID;
- TargetMachine &TM;
- void lowerVCREATE_v4(MachineInstr &MI, MachineBasicBlock::iterator I,
- MachineBasicBlock &MBB, MachineFunction &MF);
+class AMDGPULowerInstructionsPass : public MachineFunctionPass {
- public:
- AMDGPULowerInstructionsPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm) { }
+private:
+ static char ID;
+ TargetMachine &TM;
+ void lowerVCREATE_v4(MachineInstr &MI, MachineBasicBlock::iterator I,
+ MachineBasicBlock &MBB, MachineFunction &MF);
- virtual bool runOnMachineFunction(MachineFunction &MF);
+public:
+ AMDGPULowerInstructionsPass(TargetMachine &tm) :
+ MachineFunctionPass(ID), TM(tm) { }
- };
-} /* End anonymous namespace */
+ virtual bool runOnMachineFunction(MachineFunction &MF);
+
+};
+
+} // End anonymous namespace
char AMDGPULowerInstructionsPass::ID = 0;
namespace llvm {
- class AMDGPUTargetMachine;
- class TargetInstrInfo;
+class AMDGPUTargetMachine;
+class TargetInstrInfo;
- struct AMDGPURegisterInfo : public AMDILRegisterInfo
- {
- AMDGPUTargetMachine &TM;
- const TargetInstrInfo &TII;
+struct AMDGPURegisterInfo : public AMDILRegisterInfo
+{
+ AMDGPUTargetMachine &TM;
+ const TargetInstrInfo &TII;
- AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+ AMDGPURegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
- virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
- virtual const TargetRegisterClass *
+ /// getISARegClass - rc is an AMDIL reg class. This function returns the
+ /// ISA reg class that is equivalent to the given AMDIL reg class.
+ virtual const TargetRegisterClass *
getISARegClass(const TargetRegisterClass * rc) const = 0;
- };
+};
+
} // End namespace llvm
#endif // AMDIDSAREGISTERINFO_H_
mDump(false)
{
- /* TLInfo uses InstrInfo so it must be initialized after. */
+ // TLInfo uses InstrInfo so it must be initialized after.
if (Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) {
InstrInfo = new R600InstrInfo(*this);
TLInfo = new R600TargetLowering(*this);
formatted_raw_ostream &Out,
CodeGenFileType FileType,
bool DisableVerify) {
- /* XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
- * only using it to access addPassesToGenerateCode() */
+ // XXX: Hack here addPassesToEmitFile will fail, but this is Ok since we are
+ // only using it to access addPassesToGenerateCode()
bool fail = LLVMTargetMachine::addPassesToEmitFile(PM, Out, FileType,
DisableVerify);
assert(fail);
bool DisableVerify);
};
-} /* End namespace llvm */
+} // End namespace llvm
-#endif /* AMDGPU_TARGET_MACHINE_H */
+#endif // AMDGPU_TARGET_MACHINE_H
case AMDIL::CONTINUE_LOGICALNZ_f32:
case AMDIL::IF_LOGICALNZ_i32:
case AMDIL::IF_LOGICALZ_f32:
- case AMDIL::ELSE:
+ case AMDIL::ELSE:
case AMDIL::ENDIF:
case AMDIL::ENDLOOP:
case AMDIL::IF_LOGICALNZ_f32:
}
void AMDGPU::utilAddLiveIn(llvm::MachineFunction * MF,
- llvm::MachineRegisterInfo & MRI,
- const struct llvm::TargetInstrInfo * TII,
- unsigned physReg, unsigned virtReg)
+ llvm::MachineRegisterInfo & MRI,
+ const llvm::TargetInstrInfo * TII,
+ unsigned physReg, unsigned virtReg)
{
if (!MRI.isLiveIn(physReg)) {
MRI.addLiveIn(physReg, virtReg);
MF->front().addLiveIn(physReg);
BuildMI(MF->front(), MF->front().begin(), DebugLoc(),
- TII->get(TargetOpcode::COPY), virtReg)
- .addReg(physReg);
+ TII->get(TargetOpcode::COPY), virtReg)
+ .addReg(physReg);
} else {
MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg));
}
#define MO_FLAG_MASK (1 << 3)
void utilAddLiveIn(llvm::MachineFunction * MF, llvm::MachineRegisterInfo & MRI,
- const struct llvm::TargetInstrInfo * TII, unsigned physReg, unsigned virtReg);
+ const llvm::TargetInstrInfo * TII, unsigned physReg, unsigned virtReg);
} // End namespace AMDGPU
unsigned getHWReg(unsigned regNo) const;
- unsigned getElement(unsigned regNo);
-
};
} /* End anonymous namespace */
}
}
-
-RegElement maskBitToElement(unsigned int maskBit)
-{
- switch (maskBit) {
- case WRITE_MASK_X: return ELEMENT_X;
- case WRITE_MASK_Y: return ELEMENT_Y;
- case WRITE_MASK_Z: return ELEMENT_Z;
- case WRITE_MASK_W: return ELEMENT_W;
- default:
- assert("Invalid maskBit");
- return ELEMENT_X;
- }
-}
-
#include "AMDILGenCodeEmitter.inc"
private:
const R600InstrInfo * TII;
+ /// lowerImplicitParameter - Each OpenCL kernel has nine implicit parameters
+ /// that are stored in the first nine dwords of a Vertex Buffer. These
+ /// implicit parameters are represented by pseudo instructions, which are
+ /// lowered to VTX_READ instructions by this function.
void lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB,
MachineRegisterInfo & MRI, unsigned dword_offset) const;
namespace llvm {
- class R600TargetMachine;
- class TargetInstrInfo;
+class R600TargetMachine;
+class TargetInstrInfo;
- struct R600RegisterInfo : public AMDGPURegisterInfo
- {
- AMDGPUTargetMachine &TM;
- const TargetInstrInfo &TII;
+struct R600RegisterInfo : public AMDGPURegisterInfo
+{
+ AMDGPUTargetMachine &TM;
+ const TargetInstrInfo &TII;
- R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+ R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
- virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const;
+
+ /// getISARegClass - rc is an AMDIL reg class. This function returns the
+ /// R600 reg class that is equivalent to the given AMDIL reg class.
+ virtual const TargetRegisterClass * getISARegClass(
+ const TargetRegisterClass * rc) const;
+
+ /// getHWRegIndex - get the HW encoding for a register.
+ unsigned getHWRegIndex(unsigned reg) const;
+
+ /// getHWRegChan - get the HW encoding for a register's channel.
+ unsigned getHWRegChan(unsigned reg) const;
- virtual const TargetRegisterClass *
- getISARegClass(const TargetRegisterClass * rc) const;
- unsigned getHWRegIndex(unsigned reg) const;
- unsigned getHWRegChan(unsigned reg) const;
private:
- unsigned getHWRegChanGen(unsigned reg) const;
- unsigned getHWRegIndexGen(unsigned reg) const;
- };
+ /// getHWRegIndexGen - Generated function returns a register's encoding
+ unsigned getHWRegIndexGen(unsigned reg) const;
+ /// getHWRegChanGen - Generated function returns a register's channel
+ /// encoding.
+ unsigned getHWRegChanGen(unsigned reg) const;
+};
+
} // End namespace llvm
#endif // AMDIDSAREGISTERINFO_H_
using namespace llvm;
namespace {
- class SIAssignInterpRegsPass : public MachineFunctionPass {
- private:
- static char ID;
- TargetMachine &TM;
+class SIAssignInterpRegsPass : public MachineFunctionPass {
- public:
- SIAssignInterpRegsPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm) { }
+private:
+ static char ID;
+ TargetMachine &TM;
- virtual bool runOnMachineFunction(MachineFunction &MF);
+public:
+ SIAssignInterpRegsPass(TargetMachine &tm) :
+ MachineFunctionPass(ID), TM(tm) { }
+
+ virtual bool runOnMachineFunction(MachineFunction &MF);
+
+ const char *getPassName() const { return "SI Assign intrpolation registers"; }
+};
- const char *getPassName() const { return "SI Assign intrpolation registers"; }
- };
} // End anonymous namespace
char SIAssignInterpRegsPass::ID = 0;
_OS(OS), TM(NULL) { }
const char *getPassName() const { return "SI Code Emitter"; }
bool runOnMachineFunction(MachineFunction &MF);
+
+ /// getMachineOpValue - Return the encoding for MO
virtual uint64_t getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const;
+
+ /// GPR4AlignEncode - Encoding for when 4 consectuive registers are used
virtual unsigned GPR4AlignEncode(const MachineInstr &MI, unsigned OpNo)
const;
+
+ /// GPR2AlignEncode - Encoding for when 2 consecutive registers are used
virtual unsigned GPR2AlignEncode(const MachineInstr &MI, unsigned OpNo)
const;
+ /// i32LiteralEncode - Encode an i32 literal this is used as an operand
+ /// for an instruction in place of a register.
virtual uint64_t i32LiteralEncode(const MachineInstr &MI, unsigned OpNo)
const;
+
+ /// VOPPostEncode - Post-Encoder method for VOP instructions
virtual uint64_t VOPPostEncode(const MachineInstr &MI,
uint64_t Value) const;
};
abort();
}
-// hwInst |= SII->getBinaryCode(MI);
-
unsigned bytes = SII->getEncodingBytes(MI);
outputBytes(hwInst, bytes);
}
return MO.getImm();
case MachineOperand::MO_FPImmediate:
- /* XXX: Not all instructions can use inline literals */
- /* XXX: We should make sure this is a 32-bit constant */
+ // XXX: Not all instructions can use inline literals
+ // XXX: We should make sure this is a 32-bit constant
return LITERAL_REG | (MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue() << 32);
default:
llvm_unreachable("Encoding of this operand type is not supported yet.");
return LITERAL_REG | (MI.getOperand(OpNo).getImm() << 32);
}
-/* Set the "VGPR" bit for VOP args that can take either a VGPR or a SGPR.
- * XXX: It would be nice if we could handle this without a PostEncode function.
- */
+/// Set the "VGPR" bit for VOP args that can take either a VGPR or a SGPR.
+/// XXX: It would be nice if we could handle this without a PostEncode function.
uint64_t SICodeEmitter::VOPPostEncode(const MachineInstr &MI,
uint64_t Value) const
{
vgprBitOffset = 0;
}
- /* Add one to skip over the destination reg operand. */
+ // Add one to skip over the destination reg operand.
for (unsigned opIdx = 1; opIdx < numSrcOps + 1; opIdx++) {
if (!MI.getOperand(opIdx).isReg()) {
continue;
MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineInstr * MI, MachineBasicBlock * BB) const
{
- const struct TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
+ const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
MachineBasicBlock::iterator I = MI;
void SITargetLowering::lowerUSE_SGPR(MachineInstr *MI,
MachineFunction * MF, MachineRegisterInfo & MRI) const
{
- const struct TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
+ const TargetInstrInfo * TII = getTargetMachine().getInstrInfo();
unsigned dstReg = MI->getOperand(0).getReg();
int64_t newIndex = MI->getOperand(1).getImm();
const TargetRegisterClass * dstClass = MRI.getRegClass(dstReg);
{
const SIInstrInfo * TII;
+ /// AppendS_WAITCNT - Memory reads and writes are syncronized using the
+ /// S_WAITCNT instruction. This function takes the most conservative
+ /// approach and inserts an S_WAITCNT instruction after every read and
+ /// write.
void AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I) const;
void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
namespace llvm {
- class SIInstrInfo : public AMDGPUInstrInfo {
- private:
- const SIRegisterInfo RI;
- AMDGPUTargetMachine &TM;
+class SIInstrInfo : public AMDGPUInstrInfo {
+private:
+ const SIRegisterInfo RI;
+ AMDGPUTargetMachine &TM;
- MachineInstr * convertABS_f32(MachineInstr & absInstr, MachineFunction &MF,
- DebugLoc DL) const;
+ MachineInstr * convertABS_f32(MachineInstr & absInstr, MachineFunction &MF,
+ DebugLoc DL) const;
- MachineInstr * convertCLAMP_f32(MachineInstr & clampInstr,
- MachineFunction &MF, DebugLoc DL) const;
+ MachineInstr * convertCLAMP_f32(MachineInstr & clampInstr,
+ MachineFunction &MF, DebugLoc DL) const;
- public:
- explicit SIInstrInfo(AMDGPUTargetMachine &tm);
+public:
+ explicit SIInstrInfo(AMDGPUTargetMachine &tm);
- const SIRegisterInfo &getRegisterInfo() const;
+ const SIRegisterInfo &getRegisterInfo() const;
- virtual void copyPhysReg(MachineBasicBlock &MBB,
+ virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
- unsigned getEncodingType(const MachineInstr &MI) const;
+ /// getEncodingType - Returns the encoding type of this instruction.
+ unsigned getEncodingType(const MachineInstr &MI) const;
- unsigned getEncodingBytes(const MachineInstr &MI) const;
+ /// getEncodingBytes - Returns the size of this instructions encoding in
+ /// number of bytes.
+ unsigned getEncodingBytes(const MachineInstr &MI) const;
- uint64_t getBinaryCode(const MachineInstr &MI, bool encodOpcode = false) const;
-
- virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
+ /// convertToISA - Convert the AMDIL MachineInstr to a supported SI
+ ///MachineInstr
+ virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const;
- virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
+ /// getISAOpcode - This function takes an AMDIL opcode as an argument and
+ /// returns an equivalent SI opcode.
+ virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
};
} // End namespace llvm
-/* These must be kept in sync with SIInstructions.td and also the
- * InstrEncodingInfo array in SIInstrInfo.cpp.
- *
- * NOTE: This enum is only used to identify the encoding type within LLVM,
- * the actual encoding type that is part of the instruction format is different
- */
+// These must be kept in sync with SIInstructions.td and also the
+// InstrEncodingInfo array in SIInstrInfo.cpp.
+//
+// NOTE: This enum is only used to identify the encoding type within LLVM,
+// the actual encoding type that is part of the instruction format is different
namespace SIInstrEncodingType {
enum Encoding {
EXP = 0,
namespace SIInstrFlags {
enum Flags {
- /* First 4 bits are the instruction encoding */
+ // First 4 bits are the instruction encoding
NEED_WAIT = 1 << 4
};
}
using namespace llvm;
namespace {
- class SIPropagateImmReadsPass : public MachineFunctionPass {
- private:
- static char ID;
- TargetMachine &TM;
+class SIPropagateImmReadsPass : public MachineFunctionPass {
- public:
- SIPropagateImmReadsPass(TargetMachine &tm) :
- MachineFunctionPass(ID), TM(tm) { }
+private:
+ static char ID;
+ TargetMachine &TM;
- virtual bool runOnMachineFunction(MachineFunction &MF);
- };
-} /* End anonymous namespace */
+public:
+ SIPropagateImmReadsPass(TargetMachine &tm) :
+ MachineFunctionPass(ID), TM(tm) { }
+
+ virtual bool runOnMachineFunction(MachineFunction &MF);
+};
+
+} // End anonymous namespace
char SIPropagateImmReadsPass::ID = 0;
continue;
}
- /* XXX: Create and use S_MOV_IMM for SREGs */
+ // XXX: Create and use S_MOV_IMM for SREGs
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::V_MOV_IMM))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(1));
}
}
-bool SIRegisterInfo::isBaseRegClass(unsigned regClassID) const
-{
- switch (regClassID) {
- default: return true;
- case AMDIL::AllReg_32RegClassID:
- case AMDIL::AllReg_64RegClassID:
- return false;
- }
-}
-
const TargetRegisterClass *
SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
{
namespace llvm {
- class AMDGPUTargetMachine;
- class TargetInstrInfo;
+class AMDGPUTargetMachine;
+class TargetInstrInfo;
- struct SIRegisterInfo : public AMDGPURegisterInfo
- {
- AMDGPUTargetMachine &TM;
- const TargetInstrInfo &TII;
+struct SIRegisterInfo : public AMDGPURegisterInfo
+{
+ AMDGPUTargetMachine &TM;
+ const TargetInstrInfo &TII;
- SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+ SIRegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
- virtual BitVector getReservedRegs(const MachineFunction &MF) const;
- virtual unsigned getBinaryCode(unsigned reg) const;
+ virtual BitVector getReservedRegs(const MachineFunction &MF) const;
- virtual bool isBaseRegClass(unsigned regClassID) const;
+ /// getBinaryCode - Returns the hardware encoding for a register
+ virtual unsigned getBinaryCode(unsigned reg) const;
- virtual const TargetRegisterClass *
+ /// getISARegClass - rc is an AMDIL reg class. This function returns the
+ /// SI register class that is equivalent to the given AMDIL register class.
+ virtual const TargetRegisterClass *
getISARegClass(const TargetRegisterClass * rc) const;
- unsigned getHWRegNum(unsigned reg) const;
+ /// getHWRegNum - Generated function that returns the hardware encoding for
+ /// a register
+ unsigned getHWRegNum(unsigned reg) const;
- };
+};
} // End namespace llvm
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