radeonsi/gfx9: add radeon_surf.gfx9.surf_offset
authorMarek Olšák <marek.olsak@amd.com>
Wed, 15 Feb 2017 23:11:58 +0000 (00:11 +0100)
committerMarek Olšák <marek.olsak@amd.com>
Thu, 30 Mar 2017 12:44:33 +0000 (14:44 +0200)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
src/gallium/drivers/radeon/r600_texture.c
src/gallium/drivers/radeon/radeon_winsys.h
src/gallium/drivers/radeonsi/si_descriptors.c
src/gallium/drivers/radeonsi/si_state.c
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c

index f1b2cd96bcf0cb3743bc7391f9a50f3637c2264b..2e66dd0fd4e67dbc53a5064416504bc864246d2c 100644 (file)
@@ -555,7 +555,7 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
        }
 
        if (rscreen->chip_class >= GFX9) {
-               offset = 0;
+               offset = rtex->surface.u.gfx9.surf_offset;
                stride = rtex->surface.u.gfx9.surf_pitch *
                         rtex->surface.bpe;
                slice_size = rtex->surface.u.gfx9.surf_slice_size;
index 5b032bfea7b822f138d86028991ce2991b25dbf1..b3c7608c81e91c0d0a7702e4dea5ca59d583495f 100644 (file)
@@ -354,6 +354,7 @@ struct gfx9_surf_layout {
     struct gfx9_surf_meta_flags cmask; /* metadata of fmask */
 
     enum gfx9_resource_type     resource_type; /* 1D, 2D or 3D */
+    uint64_t                    surf_offset; /* 0 unless imported with an offset */
     /* The size of the 2D plane containing all mipmap levels. */
     uint64_t                    surf_slice_size;
     uint16_t                    surf_pitch; /* in blocks */
index 58d35dabde2f355492cec3a89178bc909207f5f0..fb82f8f3ee968703a3f60c14b6464a55aa7e05c2 100644 (file)
@@ -398,6 +398,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
                /* Only stencil_offset needs to be added here. */
                if (is_stencil)
                        va += tex->surface.u.gfx9.stencil_offset;
+               else
+                       va += tex->surface.u.gfx9.surf_offset;
        } else {
                va += base_level_info->offset;
        }
index de64e64a33882a454e325f55c52a84da30720c2b..c4063a8a8d6d5dca0d41dc11a5424db429a40270 100644 (file)
@@ -2271,6 +2271,7 @@ static void si_init_depth_surface(struct si_context *sctx,
        surf->db_htile_surface = 0;
 
        if (sctx->b.chip_class >= GFX9) {
+               assert(rtex->surface.u.gfx9.surf_offset == 0);
                surf->db_depth_base = rtex->resource.gpu_address >> 8;
                surf->db_stencil_base = (rtex->resource.gpu_address +
                                         rtex->surface.u.gfx9.stencil_offset) >> 8;
@@ -2658,6 +2659,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
                                meta = tex->surface.u.gfx9.cmask;
 
                        /* Set mutable surface parameters. */
+                       cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
                        cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
                                           S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
                                           S_028C74_RB_ALIGNED(meta.rb_aligned) |
index dd3a154c14b280c05ff7d0d80c3a1c9963c2af02..fd9e4dd482f3c4e9b9ce4d8c005a49d4c50bb11a 100644 (file)
@@ -902,6 +902,7 @@ static int gfx9_surface_init(struct radeon_winsys *rws,
    surf->surf_size = 0;
    surf->dcc_size = 0;
    surf->htile_size = 0;
+   surf->u.gfx9.surf_offset = 0;
    surf->u.gfx9.stencil_offset = 0;
    surf->u.gfx9.fmask_size = 0;
    surf->u.gfx9.cmask_size = 0;