tiling.microtile = tex->tex.microtile;
tiling.macrotile = tex->tex.macrotile[0];
tiling.stride = tex->tex.stride_in_bytes[0];
- rws->buffer_set_tiling(tex->buf, &tiling);
+ rws->buffer_set_metadata(tex->buf, &tiling);
return tex;
if (!buffer)
return NULL;
- rws->buffer_get_tiling(buffer, &tiling);
+ rws->buffer_get_metadata(buffer, &tiling);
/* Enforce a microtiled zbuffer. */
if (util_format_is_depth_or_stencil(base->format) &&
metadata.stride = surface->level[0].pitch_bytes;
metadata.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
- rscreen->ws->buffer_set_tiling(resource->buf, &metadata);
+ rscreen->ws->buffer_set_metadata(resource->buf, &metadata);
return rscreen->ws->buffer_get_handle(resource->buf,
surface->level[0].pitch_bytes, whandle);
if (!buf)
return NULL;
- rscreen->ws->buffer_get_tiling(buf, &metadata);
+ rscreen->ws->buffer_get_metadata(buf, &metadata);
surface.bankw = metadata.bankw;
surface.bankh = metadata.bankh;
* \param buf A winsys buffer object to get the flags from.
* \param md Metadata
*/
- void (*buffer_get_tiling)(struct pb_buffer *buf,
- struct radeon_bo_metadata *md);
+ void (*buffer_get_metadata)(struct pb_buffer *buf,
+ struct radeon_bo_metadata *md);
/**
* Set buffer metadata.
* \param buf A winsys buffer object to set the flags for.
* \param md Metadata
*/
- void (*buffer_set_tiling)(struct pb_buffer *buf,
- struct radeon_bo_metadata *md);
+ void (*buffer_set_metadata)(struct pb_buffer *buf,
+ struct radeon_bo_metadata *md);
/**
* Get a winsys buffer from a winsys handle. The internal structure
}
}
-static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
- struct radeon_bo_metadata *md)
+static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *md)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_info info = {0};
md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
}
-static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
- struct radeon_bo_metadata *md)
+static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *md)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_metadata metadata = {0};
void amdgpu_bo_init_functions(struct amdgpu_winsys *ws)
{
- ws->base.buffer_set_tiling = amdgpu_bo_set_tiling;
- ws->base.buffer_get_tiling = amdgpu_bo_get_tiling;
+ ws->base.buffer_set_metadata = amdgpu_buffer_set_metadata;
+ ws->base.buffer_get_metadata = amdgpu_buffer_get_metadata;
ws->base.buffer_map = amdgpu_bo_map;
ws->base.buffer_unmap = amdgpu_bo_unmap;
ws->base.buffer_wait = amdgpu_bo_wait;
}
}
-static void radeon_bo_get_tiling(struct pb_buffer *_buf,
- struct radeon_bo_metadata *md)
+static void radeon_bo_get_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *md)
{
struct radeon_bo *bo = radeon_bo(_buf);
struct drm_radeon_gem_set_tiling args;
md->scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT);
}
-static void radeon_bo_set_tiling(struct pb_buffer *_buf,
- struct radeon_bo_metadata *md)
+static void radeon_bo_set_metadata(struct pb_buffer *_buf,
+ struct radeon_bo_metadata *md)
{
struct radeon_bo *bo = radeon_bo(_buf);
struct drm_radeon_gem_set_tiling args;
void radeon_drm_bo_init_functions(struct radeon_drm_winsys *ws)
{
- ws->base.buffer_set_tiling = radeon_bo_set_tiling;
- ws->base.buffer_get_tiling = radeon_bo_get_tiling;
+ ws->base.buffer_set_metadata = radeon_bo_set_metadata;
+ ws->base.buffer_get_metadata = radeon_bo_get_metadata;
ws->base.buffer_map = radeon_bo_map;
ws->base.buffer_unmap = radeon_bo_unmap;
ws->base.buffer_wait = radeon_bo_wait;