boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/projects/pd/randd/dist/binaries/console
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/projects/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/projects/pd/randd/dist/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
[system.disk0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:39:31
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 13 2013 10:45:16
+gem5 started Feb 13 2013 13:46:08
+gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1854344296500 because m5_exit instruction encountered
+Exiting @ tick 1854310111000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
sim_seconds 1.854310 # Number of seconds simulated
-sim_ticks 1854309852000 # Number of ticks simulated
-final_tick 1854309852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 1854310111000 # Number of ticks simulated
+final_tick 1854310111000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 117975 # Simulator instruction rate (inst/s)
-host_op_rate 117975 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4129044881 # Simulator tick rate (ticks/s)
-host_mem_usage 335500 # Number of bytes of host memory used
-host_seconds 449.09 # Real time elapsed on the host
-sim_insts 52981417 # Number of instructions simulated
-sim_ops 52981417 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 964672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24877888 # Number of bytes read from this memory
+host_inst_rate 145253 # Simulator instruction rate (inst/s)
+host_op_rate 145253 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5083862253 # Simulator tick rate (ticks/s)
+host_mem_usage 332668 # Number of bytes of host memory used
+host_seconds 364.74 # Real time elapsed on the host
+sim_insts 52980262 # Number of instructions simulated
+sim_ops 52980262 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 964224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 24877184 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28494848 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 964672 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 964672 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7516416 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7516416 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 15073 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 388717 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 28493696 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 964224 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 964224 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7514944 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7514944 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 15066 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 388706 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 445232 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 117444 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 117444 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 520232 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 13416252 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::total 445214 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 117421 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 117421 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 519991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 13415870 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1430337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15366821 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 520232 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 520232 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4053484 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4053484 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4053484 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 520232 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 13416252 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::total 15366198 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 519991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 519991 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4052690 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4052690 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4052690 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 519991 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 13415870 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1430337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19420306 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 445232 # Total number of read requests seen
-system.physmem.writeReqs 117444 # Total number of write requests seen
-system.physmem.cpureqs 565193 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28494848 # Total number of bytes read from memory
-system.physmem.bytesWritten 7516416 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28494848 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7516416 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 171 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28112 # Track reads on a per bank basis
+system.physmem.bw_total::total 19418888 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 445214 # Total number of read requests seen
+system.physmem.writeReqs 117421 # Total number of write requests seen
+system.physmem.cpureqs 564314 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28493696 # Total number of bytes read from memory
+system.physmem.bytesWritten 7514944 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28493696 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7514944 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 56 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 174 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28116 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 27866 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 27716 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27523 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 27754 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 27794 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 27723 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 27566 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28230 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 27914 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 28000 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27799 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27706 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 27921 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27830 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27718 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7631 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7398 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7277 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 7173 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7281 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7238 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 7208 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 7147 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 7771 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7465 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7554 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7296 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7212 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::2 27714 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 27520 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 27750 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 27793 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 27726 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 27564 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 28224 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 27918 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 27999 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 27794 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 27705 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 27923 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 27829 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 27717 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 7633 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7399 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7274 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 7170 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7277 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7235 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 7211 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 7144 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7765 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7469 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7552 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 7291 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7210 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 7327 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7265 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 7201 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7264 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7200 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1787 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1854304427000 # Total gap between requests
+system.physmem.numWrRetry 946 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1854304705000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 445232 # Categorize read packet sizes
+system.physmem.readPktSize::6 445214 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 119231 # categorize write packet sizes
+system.physmem.writePktSize::6 118367 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 171 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 174 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 323360 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 64418 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 19847 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 7546 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3166 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2952 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2693 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2668 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2640 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2594 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1545 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1469 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1418 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1345 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1374 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1596 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1493 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 910 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 761 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 323357 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 64296 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 7564 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3180 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2966 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2710 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2705 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2662 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2613 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1551 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1463 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1409 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1357 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1378 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1393 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1481 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2999 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3738 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4232 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4753 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5084 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5089 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5092 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2975 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3712 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4165 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4221 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4750 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5085 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5091 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5093 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 5096 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 2108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1369 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 935 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 875 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 2131 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1394 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 941 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 885 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 356 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 12 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 9 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 7898633503 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15636428503 # Sum of mem lat for all requests
-system.physmem.totBusLat 2225860000 # Total cycles spent in databus access
-system.physmem.totBankLat 5511935000 # Total cycles spent in bank access
-system.physmem.avgQLat 17742.88 # Average queueing delay per request
-system.physmem.avgBankLat 12381.59 # Average bank access latency per request
+system.physmem.totQLat 7913395266 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 15649662766 # Sum of mem lat for all requests
+system.physmem.totBusLat 2225790000 # Total cycles spent in databus access
+system.physmem.totBankLat 5510477500 # Total cycles spent in bank access
+system.physmem.avgQLat 17776.60 # Average queueing delay per request
+system.physmem.avgBankLat 12378.70 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 35124.47 # Average memory access latency
+system.physmem.avgMemAccLat 35155.30 # Average memory access latency
system.physmem.avgRdBW 15.37 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 4.05 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 15.37 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.15 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.01 # Average read queue length over time
-system.physmem.avgWrQLen 10.74 # Average write queue length over time
-system.physmem.readRowHits 417598 # Number of row buffer hits during reads
-system.physmem.writeRowHits 91555 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 93.81 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes
-system.physmem.avgGap 3295510.08 # Average gap between requests
+system.physmem.avgWrQLen 11.52 # Average write queue length over time
+system.physmem.readRowHits 417628 # Number of row buffer hits during reads
+system.physmem.writeRowHits 91533 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 93.82 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.95 # Row buffer hit rate for writes
+system.physmem.avgGap 3295750.72 # Average gap between requests
system.iocache.replacements 41685 # number of replacements
-system.iocache.tagsinuse 1.265033 # Cycle average of tags in use
+system.iocache.tagsinuse 1.265053 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1704476002000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 1.265033 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.079065 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.079065 # Average percentage of cache occupancy
+system.iocache.warmup_cycle 1704474436000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::tsunami.ide 1.265053 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.079066 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.079066 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10574791806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10574791806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10595719804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10595719804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10595719804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10595719804 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10610366806 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10610366806 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10631294804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10631294804 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10631294804 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10631294804 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 254495.374615 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 254495.374615 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 253941.756836 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 253941.756836 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 253941.756836 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 280489 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255351.530757 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 255351.530757 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 254794.363188 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 254794.363188 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 254794.363188 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 282772 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27002 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27194 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.387712 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.398323 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931250 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931250 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8412803020 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8412803020 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8424734270 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8424734270 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8424734270 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8424734270 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8448369274 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8448369274 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8460300524 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8460300524 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8460300524 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8460300524 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.763006 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.763006 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 202464.454659 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 202464.454659 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 201910.947154 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 201910.947154 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203320.400318 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 203320.400318 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 202763.343895 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 202763.343895 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 13854519 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11622006 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 399782 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9584331 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 5815567 # Number of BTB hits
+system.cpu.branchPred.lookups 13838840 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11607895 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 399412 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9524270 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5814876 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 60.677861 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 905443 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 39042 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 61.053246 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 905729 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 39052 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9921013 # DTB read hits
-system.cpu.dtb.read_misses 41705 # DTB read misses
-system.cpu.dtb.read_acv 547 # DTB read access violations
-system.cpu.dtb.read_accesses 941529 # DTB read accesses
-system.cpu.dtb.write_hits 6598119 # DTB write hits
-system.cpu.dtb.write_misses 10489 # DTB write misses
-system.cpu.dtb.write_acv 411 # DTB write access violations
-system.cpu.dtb.write_accesses 338424 # DTB write accesses
-system.cpu.dtb.data_hits 16519132 # DTB hits
-system.cpu.dtb.data_misses 52194 # DTB misses
-system.cpu.dtb.data_acv 958 # DTB access violations
-system.cpu.dtb.data_accesses 1279953 # DTB accesses
-system.cpu.itb.fetch_hits 1307587 # ITB hits
-system.cpu.itb.fetch_misses 36909 # ITB misses
-system.cpu.itb.fetch_acv 1032 # ITB acv
-system.cpu.itb.fetch_accesses 1344496 # ITB accesses
+system.cpu.dtb.read_hits 9926019 # DTB read hits
+system.cpu.dtb.read_misses 41533 # DTB read misses
+system.cpu.dtb.read_acv 530 # DTB read access violations
+system.cpu.dtb.read_accesses 942239 # DTB read accesses
+system.cpu.dtb.write_hits 6593693 # DTB write hits
+system.cpu.dtb.write_misses 10528 # DTB write misses
+system.cpu.dtb.write_acv 400 # DTB write access violations
+system.cpu.dtb.write_accesses 337995 # DTB write accesses
+system.cpu.dtb.data_hits 16519712 # DTB hits
+system.cpu.dtb.data_misses 52061 # DTB misses
+system.cpu.dtb.data_acv 930 # DTB access violations
+system.cpu.dtb.data_accesses 1280234 # DTB accesses
+system.cpu.itb.fetch_hits 1304342 # ITB hits
+system.cpu.itb.fetch_misses 39856 # ITB misses
+system.cpu.itb.fetch_acv 1022 # ITB acv
+system.cpu.itb.fetch_accesses 1344198 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 109625107 # number of cpu cycles simulated
+system.cpu.numCycles 109629781 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 28053642 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 70690468 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 13854519 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 6721010 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 13247907 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1985368 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 37409434 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 32200 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 254032 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 293409 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 622 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 8552479 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 266219 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 80576938 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.877304 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.221000 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 28054548 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 70673295 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 13838840 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 6720605 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 13244077 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1985157 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 37404215 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 32636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 256282 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 293547 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 8545648 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 265175 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 80570729 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.877158 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.220803 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 67329031 83.56% 83.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 853166 1.06% 84.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1699610 2.11% 86.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 825917 1.03% 87.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2751267 3.41% 91.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 561372 0.70% 91.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 646563 0.80% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1011071 1.25% 93.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4898941 6.08% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 67326652 83.56% 83.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 851821 1.06% 84.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1698513 2.11% 86.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 825554 1.02% 87.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2751975 3.42% 91.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 562639 0.70% 91.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 645154 0.80% 92.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1011601 1.26% 93.92% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4896820 6.08% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80576938 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.126381 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.644838 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 29188607 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 37070199 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 12111886 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 962831 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1243414 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 585279 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 42689 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 69390201 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 129780 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 1243414 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 30310150 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 13624817 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 19789639 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 11346848 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 4262068 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 65638780 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 6929 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 510249 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 1482252 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 43832025 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 79671797 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 79192798 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 478999 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 38181176 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 5650841 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1682596 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 239958 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12134086 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 10437264 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 6898844 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1303944 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 867300 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 58187512 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2050080 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 56823763 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 104138 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6892850 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3517048 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1389102 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 80576938 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.705211 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.366405 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 80570729 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.126232 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.644654 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 29191187 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 37065229 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 12109046 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 962419 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 1242847 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 584292 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 42668 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 69380603 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 129620 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 1242847 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 30314558 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 13623750 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 19784463 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 11341758 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 4263351 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 65627824 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 6945 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 510530 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 1483365 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 43820100 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 79668795 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 79189543 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 479252 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 38180356 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 5639736 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 1682796 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 239926 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12145356 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 10440685 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 6902590 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1325482 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 872752 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 58180873 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 2047058 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 56813064 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 111741 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6883646 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3532849 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 1386082 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 80570729 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.705133 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.366225 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 55928630 69.41% 69.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10806018 13.41% 82.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 5163609 6.41% 89.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3379495 4.19% 93.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2652407 3.29% 96.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1461056 1.81% 98.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 758797 0.94% 99.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 331056 0.41% 99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 95870 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 55925631 69.41% 69.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10804122 13.41% 82.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 5164072 6.41% 89.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3379310 4.19% 93.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 2651147 3.29% 96.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1461283 1.81% 98.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 759145 0.94% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 331157 0.41% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 94862 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 80576938 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 80570729 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 90990 11.53% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.53% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 373752 47.37% 58.90% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 324325 41.10% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 89963 11.41% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 373446 47.37% 58.78% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 325006 41.22% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 38746520 68.19% 68.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 61714 0.11% 68.31% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 38735893 68.18% 68.19% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 61716 0.11% 68.30% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.35% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.35% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 10353275 18.22% 86.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 6676641 11.75% 98.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 949084 1.67% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 10357569 18.23% 86.59% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 6672257 11.74% 98.33% # Type of FU issued
+system.cpu.iq.FU_type_0::IprAccess 949100 1.67% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 56823763 # Type of FU issued
-system.cpu.iq.rate 0.518346 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 789067 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.013886 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 194424766 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 66808135 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 55585961 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 692902 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 336093 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 56813064 # Type of FU issued
+system.cpu.iq.rate 0.518227 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 788415 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013877 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 194404430 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 66788743 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 55573367 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 692582 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 336629 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 327887 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 57243591 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 361953 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 600271 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 57232794 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 361399 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 600057 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1344993 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 3536 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14132 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 520971 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1348422 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 4157 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 14125 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 524715 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 17952 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 173575 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 17951 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 174954 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1243414 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 9953615 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 683685 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 63765437 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 675848 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 10437264 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 6898844 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1805870 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 511832 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 18204 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14132 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 202521 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 411600 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 614121 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 56355375 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 9990908 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 468387 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 1242847 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 9951157 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 684131 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 63754506 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 676985 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 10440685 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 6902590 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1803123 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 512112 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 18418 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 14125 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 202045 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 411832 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 613877 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 56345945 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 9995759 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 467118 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 3527845 # number of nop insts executed
-system.cpu.iew.exec_refs 16614745 # number of memory reference insts executed
-system.cpu.iew.exec_branches 8928138 # Number of branches executed
-system.cpu.iew.exec_stores 6623837 # Number of stores executed
-system.cpu.iew.exec_rate 0.514074 # Inst execution rate
-system.cpu.iew.wb_sent 56029038 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 55913848 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 27775021 # num instructions producing a value
-system.cpu.iew.wb_consumers 37616621 # num instructions consuming a value
+system.cpu.iew.exec_nop 3526575 # number of nop insts executed
+system.cpu.iew.exec_refs 16615200 # number of memory reference insts executed
+system.cpu.iew.exec_branches 8926807 # Number of branches executed
+system.cpu.iew.exec_stores 6619441 # Number of stores executed
+system.cpu.iew.exec_rate 0.513966 # Inst execution rate
+system.cpu.iew.wb_sent 56016691 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 55901254 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 27769565 # num instructions producing a value
+system.cpu.iew.wb_consumers 37614191 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.510046 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.738371 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.509909 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.738274 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7476360 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 660978 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 568527 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 79333524 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.708051 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.637595 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 7465102 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 660976 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 568169 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 79327882 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.708087 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.637784 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 58563645 73.82% 73.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 8604221 10.85% 84.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4603933 5.80% 90.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2533514 3.19% 93.66% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1516762 1.91% 95.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 607132 0.77% 96.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 522001 0.66% 97.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 533698 0.67% 97.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1848618 2.33% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 58561818 73.82% 73.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 8602415 10.84% 84.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 4601651 5.80% 90.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2532853 3.19% 93.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1516154 1.91% 95.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 607730 0.77% 96.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 522045 0.66% 97.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 534524 0.67% 97.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1848692 2.33% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 79333524 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 56172173 # Number of instructions committed
-system.cpu.commit.committedOps 56172173 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 79327882 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 56171016 # Number of instructions committed
+system.cpu.commit.committedOps 56171016 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 15470144 # Number of memory references committed
-system.cpu.commit.loads 9092271 # Number of loads committed
+system.cpu.commit.refs 15470138 # Number of memory references committed
+system.cpu.commit.loads 9092263 # Number of loads committed
system.cpu.commit.membars 226349 # Number of memory barriers committed
-system.cpu.commit.branches 8440686 # Number of branches committed
+system.cpu.commit.branches 8440338 # Number of branches committed
system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 52021801 # Number of committed integer instructions.
-system.cpu.commit.function_calls 740555 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 1848618 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 52020652 # Number of committed integer instructions.
+system.cpu.commit.function_calls 740552 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 1848692 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 140883934 # The number of ROB reads
-system.cpu.rob.rob_writes 128542305 # The number of ROB writes
-system.cpu.timesIdled 1179238 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29048169 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 3598988155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 52981417 # Number of Instructions Simulated
-system.cpu.committedOps 52981417 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 52981417 # Number of Instructions Simulated
-system.cpu.cpi 2.069124 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.069124 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.483296 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.483296 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 73895852 # number of integer regfile reads
-system.cpu.int_regfile_writes 40324169 # number of integer regfile writes
-system.cpu.fp_regfile_reads 166027 # number of floating regfile reads
-system.cpu.fp_regfile_writes 167433 # number of floating regfile writes
-system.cpu.misc_regfile_reads 1987804 # number of misc regfile reads
-system.cpu.misc_regfile_writes 938984 # number of misc regfile writes
+system.cpu.rob.rob_reads 140865752 # The number of ROB reads
+system.cpu.rob.rob_writes 128516921 # The number of ROB writes
+system.cpu.timesIdled 1179002 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 29059052 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 3598984001 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 52980262 # Number of Instructions Simulated
+system.cpu.committedOps 52980262 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 52980262 # Number of Instructions Simulated
+system.cpu.cpi 2.069257 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.069257 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.483265 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.483265 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 73880365 # number of integer regfile reads
+system.cpu.int_regfile_writes 40316413 # number of integer regfile writes
+system.cpu.fp_regfile_reads 166011 # number of floating regfile reads
+system.cpu.fp_regfile_writes 167446 # number of floating regfile writes
+system.cpu.misc_regfile_reads 1987331 # number of misc regfile reads
+system.cpu.misc_regfile_writes 938994 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu.icache.replacements 1009308 # number of replacements
-system.cpu.icache.tagsinuse 510.238404 # Cycle average of tags in use
-system.cpu.icache.total_refs 7486940 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1009816 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.414163 # Average number of references to valid blocks.
+system.cpu.icache.replacements 1008798 # number of replacements
+system.cpu.icache.tagsinuse 510.238342 # Cycle average of tags in use
+system.cpu.icache.total_refs 7480626 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1009306 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 7.411653 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 20723156000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.238404 # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst 510.238342 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.996559 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.996559 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7486941 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7486941 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7486941 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7486941 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7486941 # number of overall hits
-system.cpu.icache.overall_hits::total 7486941 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1065537 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1065537 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1065537 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1065537 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1065537 # number of overall misses
-system.cpu.icache.overall_misses::total 1065537 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14679368493 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14679368493 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14679368493 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14679368493 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14679368493 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14679368493 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 8552478 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8552478 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 8552478 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8552478 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 8552478 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8552478 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124588 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.124588 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.124588 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.124588 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.124588 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.124588 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13776.498135 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13776.498135 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13776.498135 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13776.498135 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13776.498135 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 6928 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 616 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 184 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 37.652174 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 308 # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_hits::cpu.inst 7480627 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7480627 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 7480627 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 7480627 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 7480627 # number of overall hits
+system.cpu.icache.overall_hits::total 7480627 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1065018 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1065018 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1065018 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1065018 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1065018 # number of overall misses
+system.cpu.icache.overall_misses::total 1065018 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14700112992 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14700112992 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14700112992 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14700112992 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14700112992 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14700112992 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 8545645 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 8545645 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 8545645 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 8545645 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 8545645 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 8545645 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124627 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.124627 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.124627 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.124627 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.124627 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.124627 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13802.689712 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13802.689712 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13802.689712 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13802.689712 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13802.689712 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 5838 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 237 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 28.758621 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 237 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55502 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 55502 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 55502 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 55502 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 55502 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 55502 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1010035 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1010035 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1010035 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1010035 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1010035 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1010035 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042197495 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12042197495 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042197495 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12042197495 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042197495 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12042197495 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118099 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.118099 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118099 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.118099 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11922.554659 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11922.554659 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11922.554659 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11922.554659 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55491 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 55491 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 55491 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 55491 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 55491 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 55491 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009527 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1009527 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1009527 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1009527 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1009527 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1009527 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12048771993 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 12048771993 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12048771993 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12048771993 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12048771993 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 12048771993 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118134 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.118134 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118134 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.118134 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11935.066613 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11935.066613 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11935.066613 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11935.066613 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 338291 # number of replacements
-system.cpu.l2cache.tagsinuse 65364.646667 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2546198 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 403460 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 6.310906 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 338275 # number of replacements
+system.cpu.l2cache.tagsinuse 65364.674694 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2545615 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 403441 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 6.309758 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 4180772752 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 54014.481347 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 5327.723075 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6022.442245 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.824196 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.081295 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.091895 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.997385 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 994848 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 827113 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1821961 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 840942 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 840942 # number of Writeback hits
+system.cpu.l2cache.occ_blocks::writebacks 54011.059986 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 5325.208257 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6028.406451 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.824143 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.081256 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.091986 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.997386 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 994342 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 827132 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1821474 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 840875 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 840875 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 1 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 185617 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 185617 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 994848 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1012730 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2007578 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 994848 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1012730 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2007578 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 15075 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 273765 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 288840 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_hits::cpu.data 185593 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 185593 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 994342 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1012725 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2007067 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 994342 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1012725 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2007067 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 15068 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 273766 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 288834 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 35 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 35 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 115444 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 115444 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 15075 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 389209 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 404284 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 15075 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 389209 # number of overall misses
-system.cpu.l2cache.overall_misses::total 404284 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1040084000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12407885000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 13447969000 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 291000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 291000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7693925000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 7693925000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 1040084000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 20101810000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 21141894000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 1040084000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 20101810000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 21141894000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009923 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1100878 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2110801 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 840942 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 840942 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_misses::cpu.data 115432 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 115432 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 15068 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 389198 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 404266 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 15068 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 389198 # number of overall misses
+system.cpu.l2cache.overall_misses::total 404266 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1052241000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12408474500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 13460715500 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 274500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 274500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7669350500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 7669350500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 1052241000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 20077825000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 21130066000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 1052241000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 20077825000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 21130066000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009410 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1100898 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2110308 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 840875 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 840875 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 61 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 61 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 301061 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 301061 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 1009923 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1401939 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2411862 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1009923 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1401939 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2411862 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014927 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248679 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.136839 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 301025 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 301025 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 1009410 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1401923 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2411333 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1009410 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1401923 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2411333 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014928 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248675 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.136868 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.573770 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.573770 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383457 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.383457 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014927 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.277622 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.167623 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014927 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.277622 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.167623 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68993.963516 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45323.123847 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 46558.541061 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8314.285714 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8314.285714 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66646.382662 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66646.382662 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 52294.659200 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68993.963516 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51647.855008 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 52294.659200 # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383463 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.383463 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014928 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.277617 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014928 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.277617 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69832.824529 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45325.111592 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 46603.639115 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7842.857143 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7842.857143 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66440.419468 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66440.419468 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 52267.729663 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69832.824529 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51587.688015 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 52267.729663 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 75932 # number of writebacks
-system.cpu.l2cache.writebacks::total 75932 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 75909 # number of writebacks
+system.cpu.l2cache.writebacks::total 75909 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15074 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273765 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 288839 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15067 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273766 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 288833 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115444 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 115444 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 15074 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 389209 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 404283 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 15074 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 389209 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 404283 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 852119347 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058627177 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9910746524 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 507531 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 507531 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6283747927 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6283747927 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 852119347 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15342375104 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16194494451 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 852119347 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15342375104 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16194494451 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333816000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333816000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882705000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882705000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216521000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216521000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248679 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136839 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115432 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 115432 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 15067 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 389198 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 404265 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 15067 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 389198 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 404265 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 864374583 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9058859411 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9923233994 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 514531 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 514531 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6259293268 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6259293268 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 864374583 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15318152679 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16182527262 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 864374583 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15318152679 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16182527262 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333805500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333805500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882511000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882511000 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216316500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216316500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248675 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136868 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.573770 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.573770 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383457 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383457 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.167623 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014926 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277622 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.167623 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56529.079674 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.062433 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34312.355755 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14500.885714 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14500.885714 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54431.134810 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54431.134810 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56529.079674 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39419.373920 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40057.322348 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383463 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383463 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.167652 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014927 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277617 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.167652 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57368.725227 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33089.789861 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34356.302756 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14700.885714 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14700.885714 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54224.939947 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54224.939947 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57368.725227 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39358.251273 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40029.503573 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1401345 # number of replacements
+system.cpu.dcache.replacements 1401332 # number of replacements
system.cpu.dcache.tagsinuse 511.995159 # Cycle average of tags in use
-system.cpu.dcache.total_refs 11814052 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1401857 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 8.427430 # Average number of references to valid blocks.
+system.cpu.dcache.total_refs 11818848 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1401844 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 8.430930 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21807000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.995159 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999991 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7207582 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7207582 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4204734 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4204734 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 185999 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 185999 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 7212145 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7212145 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4204906 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4204906 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 186063 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 186063 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 11412316 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 11412316 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 11412316 # number of overall hits
-system.cpu.dcache.overall_hits::total 11412316 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1803400 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1803400 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1942918 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1942918 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 11417051 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 11417051 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 11417051 # number of overall hits
+system.cpu.dcache.overall_hits::total 11417051 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1802577 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1802577 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1942748 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1942748 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 22749 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22749 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3746318 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3746318 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3746318 # number of overall misses
-system.cpu.dcache.overall_misses::total 3746318 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 34352879000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 34352879000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 65301849857 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 65301849857 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 305868500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 305868500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 3745325 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3745325 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3745325 # number of overall misses
+system.cpu.dcache.overall_misses::total 3745325 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 34332308500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 34332308500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 65131487898 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 65131487898 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 306015000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 306015000 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 13000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 13000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 99654728857 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 99654728857 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 99654728857 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 99654728857 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 9010982 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9010982 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6147652 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6147652 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208748 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 208748 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 99463796398 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 99463796398 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 99463796398 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 99463796398 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 9014722 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9014722 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6147654 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6147654 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208812 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 208812 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 215521 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 215521 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15158634 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15158634 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15158634 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15158634 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200134 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.200134 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316042 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.316042 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108978 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108978 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 15162376 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15162376 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15162376 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15162376 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.199959 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.199959 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316015 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.316015 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108945 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108945 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000005 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.247141 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.247141 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.247141 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.247141 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19048.951425 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19048.951425 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33610.193460 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33610.193460 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13445.360236 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13445.360236 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.247014 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.247014 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.247014 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.247014 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19046.236860 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19046.236860 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33525.443289 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 33525.443289 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13451.800079 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13451.800079 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26600.712715 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26600.712715 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26600.712715 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2209173 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1658 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 95967 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 26556.786500 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26556.786500 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 26556.786500 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 2193487 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 506 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 95928 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 23.020132 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 236.857143 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.865972 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 72.285714 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 840942 # number of writebacks
-system.cpu.dcache.writebacks::total 840942 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 719404 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 719404 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642459 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1642459 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5206 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 5206 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2361863 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2361863 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2361863 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2361863 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083996 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1083996 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300459 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 300459 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17543 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17543 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 840875 # number of writebacks
+system.cpu.dcache.writebacks::total 840875 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 718560 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 718560 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1642321 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1642321 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5210 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5210 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2360881 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2360881 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2360881 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2360881 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1084017 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1084017 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300427 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 300427 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17539 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17539 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1384455 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1384455 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1384455 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1384455 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21792492000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21792492000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9914016773 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 9914016773 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199792500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199792500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 1384444 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1384444 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1384444 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1384444 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21793042000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21793042000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9888893772 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 9888893772 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 199306000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 199306000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 11000 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 11000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31706508773 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 31706508773 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31706508773 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 31706508773 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423893000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423893000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997872998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997872998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421765998 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421765998 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120297 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120297 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048874 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048874 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.084039 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.084039 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31681935772 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 31681935772 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31681935772 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 31681935772 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423882500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423882500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997678998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997678998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421561498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421561498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120250 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120250 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048869 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048869 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083994 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083994 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000005 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091331 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091331 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091331 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.849092 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.849092 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32996.238332 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32996.238332 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11388.730548 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11388.730548 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091308 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091308 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091308 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20103.967004 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20103.967004 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32916.128617 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32916.128617 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11363.589714 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11363.589714 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22901.798017 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22901.798017 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22884.230617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 22884.230617 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed
-system.cpu.kern.inst.hwrei 211023 # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce 6441 # number of quiesce instructions executed
+system.cpu.kern.inst.hwrei 211025 # number of hwrei instructions executed
system.cpu.kern.ipl_count::0 74671 40.97% 40.97% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl
system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 182254 # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105575 57.93% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 182256 # number of times we switched to this ipl
system.cpu.kern.ipl_good::0 73304 49.32% 49.32% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73304 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148618 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1817865196000 98.03% 98.03% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 63825500 0.00% 98.04% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 556558000 0.03% 98.07% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 35823437500 1.93% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1854309017000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1817868211500 98.03% 98.03% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 63824000 0.00% 98.04% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 559692500 0.03% 98.07% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 35817544000 1.93% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1854309272000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981693 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694344 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::total 0.815444 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::31 0.694331 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_used::total 0.815435 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175139 91.23% 93.44% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175141 91.23% 93.44% # number of callpals executed
system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed
system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 191983 # number of callpals executed
+system.cpu.kern.callpal::total 191985 # number of callpals executed
system.cpu.kern.mode_switch::kernel 5849 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
+system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
-system.cpu.kern.mode_good::kernel 1908
-system.cpu.kern.mode_good::user 1738
+system.cpu.kern.mode_good::kernel 1910
+system.cpu.kern.mode_good::user 1740
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch_good::kernel 0.326210 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.326552 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 0.394052 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 29463172000 1.59% 1.59% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 2708574500 0.15% 1.73% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1822137262500 98.27% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_switch_good::total 0.394384 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 29467227000 1.59% 1.59% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 2708568500 0.15% 1.74% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1822133468500 98.26% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4177 # number of times the context was actually changed
---------- End Simulation Statistics ----------
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/projects/pd/randd/dist/binaries/console
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/projects/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/projects/pd/randd/dist/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.disk0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/projects/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
sim_ticks 1841685645500 # Number of ticks simulated
final_tick 1841685645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 340884 # Simulator instruction rate (inst/s)
-host_op_rate 340884 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9045969324 # Simulator tick rate (ticks/s)
-host_mem_usage 315876 # Number of bytes of host memory used
-host_seconds 203.59 # Real time elapsed on the host
+host_inst_rate 300759 # Simulator instruction rate (inst/s)
+host_op_rate 300759 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7981184825 # Simulator tick rate (ticks/s)
+host_mem_usage 313952 # Number of bytes of host memory used
+host_seconds 230.75 # Real time elapsed on the host
sim_insts 69401254 # Number of instructions simulated
sim_ops 69401254 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 474368 # Number of bytes read from this memory
system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2420382927 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4417685427 # Sum of mem lat for all requests
+system.physmem.totQLat 2420387927 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4417690427 # Sum of mem lat for all requests
system.physmem.totBusLat 546485000 # Total cycles spent in databus access
system.physmem.totBankLat 1450817500 # Total cycles spent in bank access
-system.physmem.avgQLat 22145.01 # Average queueing delay per request
+system.physmem.avgQLat 22145.05 # Average queueing delay per request
system.physmem.avgBankLat 13274.08 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 40419.09 # Average memory access latency
+system.physmem.avgMemAccLat 40419.14 # Average memory access latency
system.physmem.avgRdBW 3.80 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 3.80 # Average consumed read bandwidth in MB/s
system.physmem.avgGap 11888044.99 # Average gap between requests
system.l2c.replacements 337419 # number of replacements
system.l2c.tagsinuse 65421.239766 # Cycle average of tags in use
-system.l2c.total_refs 2475143 # Total number of references to valid blocks.
+system.l2c.total_refs 2475144 # Total number of references to valid blocks.
system.l2c.sampled_refs 402581 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.148186 # Average number of references to valid blocks.
+system.l2c.avg_refs 6.148189 # Average number of references to valid blocks.
system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks 54789.025804 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.inst 2312.416873 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2671.189078 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2671.189079 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 589.820867 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 668.130775 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2.inst 2247.184130 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 2143.472239 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data 2143.472240 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.836014 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.inst 0.035285 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.data 0.040759 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.data 491176 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 126581 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 82893 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 298491 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst 298492 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 243008 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1756064 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1756065 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 836144 # number of Writeback hits
system.l2c.Writeback_hits::total 836144 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
system.l2c.demand_hits::cpu0.data 583228 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 126581 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 109937 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 298491 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 298492 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 310850 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1943002 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1943003 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 513915 # number of overall hits
system.l2c.overall_hits::cpu0.data 583228 # number of overall hits
system.l2c.overall_hits::cpu1.inst 126581 # number of overall hits
system.l2c.overall_hits::cpu1.data 109937 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 298491 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 298492 # number of overall hits
system.l2c.overall_hits::cpu2.data 310850 # number of overall hits
-system.l2c.overall_hits::total 1943002 # number of overall hits
+system.l2c.overall_hits::total 1943003 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 7412 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 226081 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 2348 # number of ReadReq misses
system.l2c.overall_misses::total 403338 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.inst 154067000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 1052058500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 311891000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst 311896500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 1117922000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 2635938500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 2635944000 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 295000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 295000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 978615000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 978614500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1291616000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 2270231000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 2270230500 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.inst 154067000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 2030673500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 311891000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 2030673000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 311896500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 2409538000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 4906169500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 4906174500 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.inst 154067000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 2030673500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 311891000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 2030673000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 311896500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 2409538000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 4906169500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 4906174500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 521327 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 717257 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 128929 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 105873 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 303084 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst 303085 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 267156 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2043626 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2043627 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 836144 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 836144 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.data 886464 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 128929 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 153935 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 303084 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 303085 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 352601 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2346340 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2346341 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 521327 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 886464 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 128929 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 153935 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 303084 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 303085 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 352601 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2346340 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2346341 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.014218 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.315202 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.018212 # miss rate for ReadReq accesses
system.l2c.overall_miss_rate::total 0.171901 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 65616.269165 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 45781.483899 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67905.726105 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 67906.923579 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 46294.599967 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 9166.504962 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 9166.524089 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 26818.181818 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 15526.315789 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46560.805024 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 46560.781235 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 73374.765665 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 19608.822208 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 19608.817890 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 46153.768353 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 67905.726105 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 12163.915872 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 12163.928269 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 65616.269165 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 46153.768353 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 67905.726105 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 46153.756989 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 67906.923579 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 57712.102704 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 12163.915872 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 12163.928269 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.overall_mshr_misses::total 92690 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 124527350 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 769462495 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 254593394 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 254598394 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 825079853 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1973663092 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1973668092 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 271507 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 271507 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 718879972 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1795605345 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 124527350 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 1488342467 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 254593394 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 254598394 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 1901805226 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 3769268437 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 3769273437 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 124527350 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 1488342467 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 254593394 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 254598394 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 1901805226 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 3769268437 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 3769273437 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 269404000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320096500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 589500500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320097000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 589501000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 337106000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 394521000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 731627000 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606510000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 714617500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 1321127500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 714618000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 1321128000 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018212 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217053 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015154 # mshr miss rate for ReadReq accesses
system.l2c.overall_mshr_miss_rate::total 0.039504 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 33484.007615 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 34167.626843 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 36502.674213 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 36502.766687 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 24682.454545 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 24682.454545 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34203.062708 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 46492.979079 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40665.319204 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 53035.498296 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33827.502773 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 55430.741128 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 55431.829741 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 45551.129937 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40665.319204 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40665.373147 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 4870224 # DTB read hits
+system.cpu0.dtb.read_hits 4870222 # DTB read hits
system.cpu0.dtb.read_misses 6004 # DTB read misses
system.cpu0.dtb.read_acv 119 # DTB read access violations
system.cpu0.dtb.read_accesses 427226 # DTB read accesses
system.cpu0.dtb.write_misses 662 # DTB write misses
system.cpu0.dtb.write_acv 82 # DTB write access violations
system.cpu0.dtb.write_accesses 162893 # DTB write accesses
-system.cpu0.dtb.data_hits 8366144 # DTB hits
+system.cpu0.dtb.data_hits 8366142 # DTB hits
system.cpu0.dtb.data_misses 6666 # DTB misses
system.cpu0.dtb.data_acv 201 # DTB access violations
system.cpu0.dtb.data_accesses 590119 # DTB accesses
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 32346409 # Number of instructions committed
system.cpu0.committedOps 32346409 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 30227601 # Number of integer alu accesses
+system.cpu0.num_int_alu_accesses 30227600 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 167714 # Number of float alu accesses
system.cpu0.num_func_calls 807221 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4255838 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 30227601 # number of integer instructions
+system.cpu0.num_int_insts 30227600 # number of integer instructions
system.cpu0.num_fp_insts 167714 # number of float instructions
-system.cpu0.num_int_register_reads 42120333 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 22107858 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 42120330 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 22107857 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 86620 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 88185 # number of times the floating registers were written
-system.cpu0.num_mem_refs 8395831 # number of memory refs
-system.cpu0.num_load_insts 4891260 # Number of load instructions
+system.cpu0.num_mem_refs 8395829 # number of memory refs
+system.cpu0.num_load_insts 4891258 # Number of load instructions
system.cpu0.num_store_insts 3504571 # Number of store instructions
system.cpu0.num_idle_cycles 213109834303.356140 # Number of idle cycles
system.cpu0.num_busy_cycles -212181309746.356140 # Number of busy cycles
system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 73429 49.30% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 148939 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1818585880000 98.75% 98.75% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 39023000 0.00% 98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0 1818585888500 98.75% 98.75% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 39023500 0.00% 98.75% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::22 363355500 0.02% 98.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 22696630500 1.23% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 22696621500 1.23% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1841684889000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.391144 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 29741942000 1.61% 1.61% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2557109000 0.14% 1.75% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel 29741940500 1.61% 1.61% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2557110500 0.14% 1.75% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 1809385834500 98.25% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 4178 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 952687 # number of replacements
+system.cpu0.icache.replacements 952688 # number of replacements
system.cpu0.icache.tagsinuse 511.197182 # Cycle average of tags in use
-system.cpu0.icache.total_refs 41854963 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 953198 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 43.910041 # Average number of references to valid blocks.
+system.cpu0.icache.total_refs 41854962 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 953199 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 43.909994 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 10248069000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.occ_blocks::cpu0.inst 255.807414 # Average occupied blocks per requestor
system.cpu0.icache.occ_blocks::cpu1.inst 79.618511 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu2.inst 175.771256 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu2.inst 175.771257 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.499624 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu1.inst 0.155505 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::cpu2.inst 0.343303 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.998432 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 31831928 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 7734859 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 2288176 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 41854963 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 7734855 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 2288179 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 41854962 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 31831928 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 7734859 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 2288176 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 41854963 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 7734855 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 2288179 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 41854962 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 31831928 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 7734859 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 2288176 # number of overall hits
-system.cpu0.icache.overall_hits::total 41854963 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 7734855 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 2288179 # number of overall hits
+system.cpu0.icache.overall_hits::total 41854962 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 521348 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 128929 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 320069 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 970346 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 320072 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 970349 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 521348 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 128929 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 320069 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 970346 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 320072 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 970349 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 521348 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 128929 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 320069 # number of overall misses
-system.cpu0.icache.overall_misses::total 970346 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 320072 # number of overall misses
+system.cpu0.icache.overall_misses::total 970349 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1813964500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4473822486 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 6287786986 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4473861486 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 6287825986 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1813964500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 4473822486 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 6287786986 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 4473861486 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 6287825986 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1813964500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 4473822486 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 6287786986 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 4473861486 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 6287825986 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32353276 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863788 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608245 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 42825309 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 7863784 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 2608251 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 42825311 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32353276 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 7863788 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 2608245 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 42825309 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 7863784 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 2608251 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 42825311 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32353276 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 7863788 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 2608245 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 42825309 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 7863784 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 2608251 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 42825311 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016114 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016395 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122714 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122715 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.022658 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016114 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016395 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122714 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122715 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.022658 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016114 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016395 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122714 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122715 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.022658 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14069.483980 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.681331 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.943222 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13977.672168 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 6479.963380 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.681331 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 6479.943222 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 6479.963380 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14069.483980 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.681331 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 6479.943222 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13977.672168 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 6479.963380 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 5140 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16973 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 16973 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 16973 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 16973 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 16973 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 16973 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16975 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 16975 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu2.inst 16975 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 16975 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu2.inst 16975 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 16975 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128929 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303096 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 432025 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 303097 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 432026 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 128929 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 303096 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 432025 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 303097 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 432026 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 128929 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 303096 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 432025 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 303097 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 432026 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1556106500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3684192488 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 5240298988 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3684207988 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 5240314488 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1556106500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3684192488 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 5240298988 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3684207988 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 5240314488 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1556106500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3684192488 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 5240298988 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3684207988 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 5240314488 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016395 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010088 # mshr miss rate for ReadReq accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116207 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.010088 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12129.619786 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12129.627587 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12129.619786 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12069.483980 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12155.199963 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12129.619786 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12155.210998 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12129.627587 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 1392453 # number of replacements
system.cpu0.dcache.tagsinuse 511.997817 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13322506 # Total number of references to valid blocks.
+system.cpu0.dcache.total_refs 13322507 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 1392965 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 9.564135 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 9.564136 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 248.356870 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu0.data 248.356869 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu1.data 87.947367 # Average occupied blocks per requestor
system.cpu0.dcache.occ_blocks::cpu2.data 175.693580 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.485072 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu1.data 0.171772 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::cpu2.data 0.343152 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 4047371 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu0.data 4047369 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1097591 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 2422188 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7567150 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 2422191 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 7567151 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3200230 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 858461 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 1312963 # number of WriteReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21336 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 52561 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 199289 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 7247601 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data 7247599 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 1956052 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 3735151 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12938804 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 7247601 # number of overall hits
+system.cpu0.dcache.demand_hits::cpu2.data 3735154 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 12938805 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 7247599 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 1956052 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 3735151 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12938804 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 3735154 # number of overall hits
+system.cpu0.dcache.overall_hits::total 12938805 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 707756 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 103680 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 547661 # number of ReadReq misses
system.cpu0.dcache.overall_misses::cpu2.data 1110663 # number of overall misses
system.cpu0.dcache.overall_misses::total 2139380 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2172880000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9444240500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11617120500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393922000 # number of WriteReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9444239000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 11617119000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1393921500 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 14767149219 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 16161071219 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 16161070719 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28928500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 105213000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 134141500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 3566802000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 24211389719 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 27778191719 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 3566802000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 24211389719 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 27778191719 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 4755127 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu1.data 3566801500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 24211388219 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 27778189719 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 3566801500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 24211388219 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 27778189719 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 4755125 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1201271 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 2969849 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8926247 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 2969852 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8926248 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3369448 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 906524 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 1875965 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21336 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 52561 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 199289 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 8124575 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 8124573 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 2107795 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 4845814 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 15078184 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 8124575 # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 4845817 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 15078185 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 8124573 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 2107795 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 4845814 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 15078184 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 4845817 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 15078185 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.148841 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.086309 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.184407 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.152259 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.152258 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050221 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.053019 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.300113 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.092079 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.107941 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.071991 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229201 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.229200 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.141886 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107941 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.071991 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229201 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.229200 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.141886 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 20957.561728 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17244.683299 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 8547.675773 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29001.976572 # average WriteReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17244.680560 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 8547.674669 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29001.966169 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26229.301528 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 20711.807407 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 20711.806766 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13191.290470 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 15026.135390 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7174.876979 # average LoadLockedReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23505.545561 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21799.042301 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 12984.225205 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23505.545561 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21799.042301 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12984.225205 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 12984.224270 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23505.542266 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 21799.040950 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 12984.224270 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 420237 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 580 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 16818 # number of cycles access was blocked
system.cpu0.dcache.overall_mshr_misses::cpu2.data 347122 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 498865 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1965520000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314581000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280101000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297796000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4314579500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6280099500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1297795500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2151055620 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851620 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3448851120 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 24542500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 69880000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94422500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263316000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465636620 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9728952620 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263316000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465636620 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 9728952620 # number of overall MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3263315500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 6465635120 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9728950620 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3263315500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 6465635120 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 9728950620 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 287578500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342019500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342020000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 629598500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 357171000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 418642000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 775813000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 644749500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760661500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 760662000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1405411500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.086309 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.088191 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040957 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071633 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.033085 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 18957.561728 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.273670 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.801058 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.976572 # average WriteReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16473.267943 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17177.796955 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27001.966169 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25244.761290 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.485342 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25878.481590 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11191.290470 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12723.962127 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12286.597267 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.545561 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.409793 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.175178 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21505.542266 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18626.405471 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19502.171169 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 953544050 # number of cpu cycles simulated
+system.cpu1.numCycles 953544041 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 7861954 # Number of instructions committed
-system.cpu1.committedOps 7861954 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 7314134 # Number of integer alu accesses
+system.cpu1.committedInsts 7861950 # Number of instructions committed
+system.cpu1.committedOps 7861950 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 7314131 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 45433 # Number of float alu accesses
system.cpu1.num_func_calls 212083 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 960162 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 7314134 # number of integer instructions
+system.cpu1.num_int_insts 7314131 # number of integer instructions
system.cpu1.num_fp_insts 45433 # number of float instructions
-system.cpu1.num_int_register_reads 10166177 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 5323216 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 10166174 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 5323213 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 24545 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 24803 # number of times the floating registers were written
system.cpu1.num_mem_refs 2156447 # number of memory refs
system.cpu1.num_load_insts 1225739 # Number of load instructions
system.cpu1.num_store_insts 930708 # Number of store instructions
-system.cpu1.num_idle_cycles 195910529.325868 # Number of idle cycles
-system.cpu1.num_busy_cycles 757633520.674132 # Number of busy cycles
+system.cpu1.num_idle_cycles 195910527.476772 # Number of idle cycles
+system.cpu1.num_busy_cycles 757633513.523228 # Number of busy cycles
system.cpu1.not_idle_fraction 0.794545 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.205455 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
-system.cpu2.branchPred.lookups 8412637 # Number of BP lookups
+system.cpu2.branchPred.lookups 8412639 # Number of BP lookups
system.cpu2.branchPred.condPredicted 7718594 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 129281 # Number of conditional branches incorrect
+system.cpu2.branchPred.condIncorrect 129283 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 6816710 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 5762098 # Number of BTB hits
+system.cpu2.branchPred.BTBHits 5762097 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 84.529018 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 288280 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct 84.529003 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 288281 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 15520 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.dtb.fetch_accesses 0 # ITB accesses
-system.cpu2.dtb.read_hits 3230835 # DTB read hits
+system.cpu2.dtb.read_hits 3230838 # DTB read hits
system.cpu2.dtb.read_misses 11458 # DTB read misses
system.cpu2.dtb.read_acv 112 # DTB read access violations
system.cpu2.dtb.read_accesses 217040 # DTB read accesses
-system.cpu2.dtb.write_hits 2001660 # DTB write hits
+system.cpu2.dtb.write_hits 2001661 # DTB write hits
system.cpu2.dtb.write_misses 2605 # DTB write misses
system.cpu2.dtb.write_acv 143 # DTB write access violations
system.cpu2.dtb.write_accesses 81606 # DTB write accesses
-system.cpu2.dtb.data_hits 5232495 # DTB hits
+system.cpu2.dtb.data_hits 5232499 # DTB hits
system.cpu2.dtb.data_misses 14063 # DTB misses
system.cpu2.dtb.data_acv 255 # DTB access violations
system.cpu2.dtb.data_accesses 298646 # DTB accesses
-system.cpu2.itb.fetch_hits 371714 # ITB hits
+system.cpu2.itb.fetch_hits 371716 # ITB hits
system.cpu2.itb.fetch_misses 5691 # ITB misses
system.cpu2.itb.fetch_acv 245 # ITB acv
-system.cpu2.itb.fetch_accesses 377405 # ITB accesses
+system.cpu2.itb.fetch_accesses 377407 # ITB accesses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.read_acv 0 # DTB read access violations
system.cpu2.itb.data_misses 0 # DTB misses
system.cpu2.itb.data_acv 0 # DTB access violations
system.cpu2.itb.data_accesses 0 # DTB accesses
-system.cpu2.numCycles 30535701 # number of cpu cycles simulated
+system.cpu2.numCycles 30535693 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 8533986 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 34964689 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 8412637 # Number of branches that fetch encountered
+system.cpu2.fetch.icacheStallCycles 8533990 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 34964700 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 8412639 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 6050378 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 8133499 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 621333 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles 9684422 # Number of cycles fetch has spent blocked
+system.cpu2.fetch.Cycles 8133501 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 621341 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles 9684407 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 10316 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 62496 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 78611 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 2608249 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 90274 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 26910354 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.299302 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.CacheLines 2608255 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 90277 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 26910349 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.299303 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.309788 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 18776855 69.78% 69.78% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 18776848 69.78% 69.78% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 272793 1.01% 70.79% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 440434 1.64% 72.43% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4254201 15.81% 88.23% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4254202 15.81% 88.23% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 737771 2.74% 90.98% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 167398 0.62% 91.60% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 196636 0.73% 92.33% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 433593 1.61% 93.94% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 1630673 6.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 1630674 6.06% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 26910354 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total 26910349 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.275502 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.145043 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 8661365 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 9779402 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 7537150 # Number of cycles decode is running
+system.cpu2.fetch.rate 1.145044 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 8661368 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 9779389 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 7537152 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 294171 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 392382 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 168927 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 12968 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 34563094 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 40757 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 392382 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 9017323 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 2819487 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 5795757 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 7393744 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1245786 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 33400489 # Number of instructions processed by rename
+system.cpu2.decode.SquashCycles 392385 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 168928 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 12969 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 34563096 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 40760 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 392385 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 9017327 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 2819479 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 5795758 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 7393745 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 1245780 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 33400490 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 234346 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 410991 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands 22419821 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 41624595 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 41459018 # Number of integer rename lookups
+system.cpu2.rename.LSQFullEvents 410986 # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands 22419818 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 41624592 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 41459015 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 165577 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 20586998 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 1832823 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.CommittedMaps 20587002 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 1832816 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 505460 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 60216 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3692928 # count of insts added to the skid buffer
+system.cpu2.rename.skidInsts 3692921 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 3393863 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 2097985 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 374320 # Number of conflicting loads.
+system.cpu2.memDep0.insertedStores 2097986 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 374319 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 252386 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 30872998 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqInstsAdded 30873003 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 630971 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 30415497 # Number of instructions issued
+system.cpu2.iq.iqInstsIssued 30415505 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 38395 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 2194504 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 1105046 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedInstsExamined 2194500 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 1105040 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 445283 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 26910354 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::samples 26910349 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.130253 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.565604 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.565605 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 15319537 56.93% 56.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3107474 11.55% 68.48% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 1555934 5.78% 74.26% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 5075643 18.86% 93.12% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 913365 3.39% 96.51% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 492006 1.83% 98.34% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 286832 1.07% 99.41% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 15319532 56.93% 56.93% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 3107477 11.55% 68.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 1555924 5.78% 74.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 5075651 18.86% 93.12% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 913363 3.39% 96.51% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 492005 1.83% 98.34% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 286833 1.07% 99.41% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 141760 0.53% 99.93% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 17803 0.07% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 17804 0.07% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 26910354 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 26910349 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 34989 13.90% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 13.90% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 2444 0.01% 0.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 24705605 81.23% 81.24% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 24705611 81.23% 81.24% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 20302 0.07% 81.30% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.30% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 8486 0.03% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 3362289 11.05% 92.39% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 2024695 6.66% 99.05% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 3362290 11.05% 92.39% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 2024696 6.66% 99.05% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 290454 0.95% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 30415497 # Type of FU issued
-system.cpu2.iq.rate 0.996063 # Inst issue rate
+system.cpu2.iq.FU_type_0::total 30415505 # Type of FU issued
+system.cpu2.iq.rate 0.996064 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 251803 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.008279 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 87793643 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 33586183 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 30009832 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.int_inst_queue_reads 87793654 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 33586184 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 30009842 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 237903 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 116334 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 112629 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 30540939 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 30540947 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 123917 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 191281 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 420182 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 420180 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 991 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 4150 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 166078 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedStores 166079 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 4737 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 23355 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 392382 # Number of cycles IEW is squashing
+system.cpu2.iew.iewSquashCycles 392385 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 2039220 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 211536 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32790346 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 224393 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispatchedInsts 32790350 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 224390 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 3393863 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 2097985 # Number of dispatched store instructions
+system.cpu2.iew.iewDispStoreInsts 2097986 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 560382 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2248 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 4150 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 66680 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 129830 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 196510 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 30250738 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 3250585 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 164759 # Number of squashed instructions skipped in execute
+system.cpu2.iew.predictedNotTakenIncorrect 129831 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 196511 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 30250749 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 3250588 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 164756 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 1286377 # number of nop insts executed
-system.cpu2.iew.exec_refs 5259361 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 6817854 # Number of branches executed
-system.cpu2.iew.exec_stores 2008776 # Number of stores executed
+system.cpu2.iew.exec_nop 1286376 # number of nop insts executed
+system.cpu2.iew.exec_refs 5259365 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 6817857 # Number of branches executed
+system.cpu2.iew.exec_stores 2008777 # Number of stores executed
system.cpu2.iew.exec_rate 0.990668 # Inst execution rate
-system.cpu2.iew.wb_sent 30155470 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 30122461 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 17393526 # num instructions producing a value
-system.cpu2.iew.wb_consumers 20640191 # num instructions consuming a value
+system.cpu2.iew.wb_sent 30155480 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 30122471 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 17393530 # num instructions producing a value
+system.cpu2.iew.wb_consumers 20640200 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.986467 # insts written-back per cycle
+system.cpu2.iew.wb_rate 0.986468 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.842702 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 2374784 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 185688 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 182288 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 26517972 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.145282 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.851176 # Number of insts commited each cycle
+system.cpu2.commit.branchMispredicts 182289 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 26517964 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.145283 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.851177 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 16375650 61.75% 61.75% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 2329506 8.78% 70.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1218962 4.60% 75.13% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 4807374 18.13% 93.26% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 16375646 61.75% 61.75% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 2329504 8.78% 70.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 1218959 4.60% 75.13% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 4807373 18.13% 93.26% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 502647 1.90% 95.16% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 186920 0.70% 95.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 179412 0.68% 96.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 186921 0.70% 95.86% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 179411 0.68% 96.54% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 180660 0.68% 97.22% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 736841 2.78% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 736843 2.78% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 26517972 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 30370560 # Number of instructions committed
-system.cpu2.commit.committedOps 30370560 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 26517964 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 30370564 # Number of instructions committed
+system.cpu2.commit.committedOps 30370564 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 4905588 # Number of memory references committed
-system.cpu2.commit.loads 2973681 # Number of loads committed
+system.cpu2.commit.refs 4905590 # Number of memory references committed
+system.cpu2.commit.loads 2973683 # Number of loads committed
system.cpu2.commit.membars 65235 # Number of memory barriers committed
system.cpu2.commit.branches 6667985 # Number of branches committed
system.cpu2.commit.fp_insts 111312 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 28908362 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 28908366 # Number of committed integer instructions.
system.cpu2.commit.function_calls 232233 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 736841 # number cycles where commit BW limit reached
+system.cpu2.commit.bw_lim_events 736843 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 58454827 # The number of ROB reads
-system.cpu2.rob.rob_writes 65882898 # The number of ROB writes
-system.cpu2.timesIdled 242873 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 3625347 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.rob.rob_reads 58454819 # The number of ROB reads
+system.cpu2.rob.rob_writes 65882909 # The number of ROB writes
+system.cpu2.timesIdled 242872 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 3625344 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 1745288097 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 29192891 # Number of Instructions Simulated
-system.cpu2.committedOps 29192891 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 29192891 # Number of Instructions Simulated
-system.cpu2.cpi 1.045998 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.045998 # CPI: Total CPI of All Threads
+system.cpu2.committedInsts 29192895 # Number of Instructions Simulated
+system.cpu2.committedOps 29192895 # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total 29192895 # Number of Instructions Simulated
+system.cpu2.cpi 1.045997 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.045997 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.956025 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.956025 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 39779581 # number of integer regfile reads
-system.cpu2.int_regfile_writes 21289103 # number of integer regfile writes
+system.cpu2.int_regfile_reads 39779596 # number of integer regfile reads
+system.cpu2.int_regfile_writes 21289109 # number of integer regfile writes
system.cpu2.fp_regfile_reads 68643 # number of floating regfile reads
system.cpu2.fp_regfile_writes 68941 # number of floating regfile writes
system.cpu2.misc_regfile_reads 4607989 # number of misc regfile reads
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
-warn: 5659150500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5667223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 5701468500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 5716197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6234360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 5720641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 5728757500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 5763076500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 5777835500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6298513500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
-warn: 51492621000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 52553050000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 2291164927000: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
-warn: 2473679746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2487454314500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2488664454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2509713816500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2510230497500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2515951942000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2516461974500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
-warn: 2517022987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2517024145000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-warn: 2517574344000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
+warn: 2483733168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2497502762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2498707540000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2519748168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2520262198000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2525920507000: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0x200da
+warn: 2525942893500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2526450197000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
+warn: 2527009496000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2527010611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2527557612000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
hack: be nice to actually delete the event here
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:57:44
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 13 2013 11:38:19
+gem5 started Feb 13 2013 20:59:50
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2523204701000 because m5_exit instruction encountered
+Exiting @ tick 2533147650000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533245 # Number of seconds simulated
-sim_ticks 2533245380500 # Number of ticks simulated
-final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.533148 # Number of seconds simulated
+sim_ticks 2533147650000 # Number of ticks simulated
+final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 68339 # Simulator instruction rate (inst/s)
-host_op_rate 87933 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2870562080 # Simulator tick rate (ticks/s)
-host_mem_usage 409768 # Number of bytes of host memory used
-host_seconds 882.49 # Real time elapsed on the host
-sim_insts 60308251 # Number of instructions simulated
-sim_ops 77599937 # Number of ops (including micro ops) simulated
+host_inst_rate 55856 # Simulator instruction rate (inst/s)
+host_op_rate 71871 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2346171672 # Simulator tick rate (ticks/s)
+host_mem_usage 407620 # Number of bytes of host memory used
+host_seconds 1079.69 # Real time elapsed on the host
+sim_insts 60307315 # Number of instructions simulated
+sim_ops 77598799 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096850 # Total number of read requests seen
-system.physmem.writeReqs 813145 # Total number of write requests seen
-system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966198400 # Total number of bytes read from memory
-system.physmem.bytesWritten 52041280 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
+system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096808 # Total number of read requests seen
+system.physmem.writeReqs 813112 # Total number of write requests seen
+system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966195712 # Total number of bytes read from memory
+system.physmem.bytesWritten 52039168 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533244279000 # Total gap between requests
+system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2533146526000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154606 # Categorize read packet sizes
+system.physmem.readPktSize::6 154564 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2927056 # categorize write packet sizes
+system.physmem.writePktSize::2 2990994 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59127 # categorize write packet sizes
+system.physmem.writePktSize::6 59094 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482595000 # Total cycles spent in databus access
-system.physmem.totBankLat 16916941250 # Total cycles spent in bank access
-system.physmem.avgQLat 26034.38 # Average queueing delay per request
-system.physmem.avgBankLat 1120.59 # Average bank access latency per request
+system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests
+system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
+system.physmem.totBankLat 16909805000 # Total cycles spent in bank access
+system.physmem.avgQLat 26047.29 # Average queueing delay per request
+system.physmem.avgBankLat 1120.11 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32154.97 # Average memory access latency
-system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 32167.41 # Average memory access latency
+system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 12.52 # Average write queue length over time
-system.physmem.readRowHits 15020214 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793069 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 11.48 # Average write queue length over time
+system.physmem.readRowHits 15020221 # Number of row buffer hits during reads
+system.physmem.writeRowHits 793131 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
-system.physmem.avgGap 159223.45 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes
+system.physmem.avgGap 159218.06 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14667589 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits
+system.cpu.branchPred.lookups 14676489 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 14987593 # DTB read hits
-system.cpu.checker.dtb.read_misses 7307 # DTB read misses
-system.cpu.checker.dtb.write_hits 11227866 # DTB write hits
+system.cpu.checker.dtb.read_hits 14987326 # DTB read hits
+system.cpu.checker.dtb.read_misses 7302 # DTB read misses
+system.cpu.checker.dtb.write_hits 11227680 # DTB write hits
system.cpu.checker.dtb.write_misses 2189 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 14994900 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 11230055 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 14994628 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 11229869 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 26215459 # DTB hits
-system.cpu.checker.dtb.misses 9496 # DTB misses
-system.cpu.checker.dtb.accesses 26224955 # DTB accesses
-system.cpu.checker.itb.inst_hits 61482253 # ITB inst hits
+system.cpu.checker.dtb.hits 26215006 # DTB hits
+system.cpu.checker.dtb.misses 9491 # DTB misses
+system.cpu.checker.dtb.accesses 26224497 # DTB accesses
+system.cpu.checker.itb.inst_hits 61481313 # ITB inst hits
system.cpu.checker.itb.inst_misses 4471 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 61486724 # ITB inst accesses
-system.cpu.checker.itb.hits 61482253 # DTB hits
+system.cpu.checker.itb.inst_accesses 61485784 # ITB inst accesses
+system.cpu.checker.itb.hits 61481313 # DTB hits
system.cpu.checker.itb.misses 4471 # DTB misses
-system.cpu.checker.itb.accesses 61486724 # DTB accesses
-system.cpu.checker.numCycles 77885746 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 61485784 # DTB accesses
+system.cpu.checker.numCycles 77884604 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51389080 # DTB read hits
-system.cpu.dtb.read_misses 73326 # DTB read misses
-system.cpu.dtb.write_hits 11702658 # DTB write hits
-system.cpu.dtb.write_misses 17128 # DTB write misses
+system.cpu.dtb.read_hits 51394402 # DTB read hits
+system.cpu.dtb.read_misses 64202 # DTB read misses
+system.cpu.dtb.write_hits 11700782 # DTB write hits
+system.cpu.dtb.write_misses 15842 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 7749 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51462406 # DTB read accesses
-system.cpu.dtb.write_accesses 11719786 # DTB write accesses
+system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51458604 # DTB read accesses
+system.cpu.dtb.write_accesses 11716624 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63091738 # DTB hits
-system.cpu.dtb.misses 90454 # DTB misses
-system.cpu.dtb.accesses 63182192 # DTB accesses
-system.cpu.itb.inst_hits 12277036 # ITB inst hits
-system.cpu.itb.inst_misses 11490 # ITB inst misses
+system.cpu.dtb.hits 63095184 # DTB hits
+system.cpu.dtb.misses 80044 # DTB misses
+system.cpu.dtb.accesses 63175228 # DTB accesses
+system.cpu.itb.inst_hits 12330326 # ITB inst hits
+system.cpu.itb.inst_misses 11351 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 5150 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 4952 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12288526 # ITB inst accesses
-system.cpu.itb.hits 12277036 # DTB hits
-system.cpu.itb.misses 11490 # DTB misses
-system.cpu.itb.accesses 12288526 # DTB accesses
-system.cpu.numCycles 472097236 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12341677 # ITB inst accesses
+system.cpu.itb.hits 12330326 # DTB hits
+system.cpu.itb.misses 11351 # DTB misses
+system.cpu.itb.accesses 12341677 # DTB accesses
+system.cpu.numCycles 471833351 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued
-system.cpu.iq.rate 0.263176 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued
+system.cpu.iq.rate 0.263486 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 220577 # number of nop insts executed
-system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11563754 # Number of branches executed
-system.cpu.iew.exec_stores 12214366 # Number of stores executed
-system.cpu.iew.exec_rate 0.257379 # Inst execution rate
-system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47207424 # num instructions producing a value
-system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value
+system.cpu.iew.exec_nop 220665 # number of nop insts executed
+system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11561887 # Number of branches executed
+system.cpu.iew.exec_stores 12212575 # Number of stores executed
+system.cpu.iew.exec_rate 0.257603 # Inst execution rate
+system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47219839 # num instructions producing a value
+system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458632 # Number of instructions committed
-system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60457696 # Number of instructions committed
+system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386920 # Number of memory references committed
-system.cpu.commit.loads 15654712 # Number of loads committed
-system.cpu.commit.membars 403607 # Number of memory barriers committed
-system.cpu.commit.branches 9961406 # Number of branches committed
+system.cpu.commit.refs 27386450 # Number of memory references committed
+system.cpu.commit.loads 15654440 # Number of loads committed
+system.cpu.commit.membars 403595 # Number of memory barriers committed
+system.cpu.commit.branches 9961299 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68855494 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991273 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68854449 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991256 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242460133 # The number of ROB reads
-system.cpu.rob.rob_writes 201635862 # The number of ROB writes
-system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60308251 # Number of Instructions Simulated
-system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated
-system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550197997 # number of integer regfile reads
-system.cpu.int_regfile_writes 88410648 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8198 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2906 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831902 # number of misc regfile writes
-system.cpu.icache.replacements 980802 # number of replacements
-system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use
-system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits
-system.cpu.icache.overall_hits::total 11213050 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses
-system.cpu.icache.overall_misses::total 1060138 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked
+system.cpu.rob.rob_reads 242385214 # The number of ROB reads
+system.cpu.rob.rob_writes 202032533 # The number of ROB writes
+system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60307315 # Number of Instructions Simulated
+system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated
+system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 550300284 # number of integer regfile reads
+system.cpu.int_regfile_writes 88460224 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8330 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831885 # number of misc regfile writes
+system.cpu.icache.replacements 979919 # number of replacements
+system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use
+system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.615669 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 11266751 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 11266751 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 11266751 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 11266751 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 11266751 # number of overall hits
+system.cpu.icache.overall_hits::total 11266751 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1059755 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1059755 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1059755 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1059755 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1059755 # number of overall misses
+system.cpu.icache.overall_misses::total 1059755 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 13997065496 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 13997065496 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 13997065496 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 13997065496 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 13997065496 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 13997065496 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 12326506 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 12326506 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 12326506 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 4420 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 15.136986 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78782 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 78782 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 78782 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 78782 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 78782 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 78782 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981356 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 981356 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 981356 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 981356 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 981356 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 981356 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11396806498 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11396806498 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11396806498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11396806498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11396806498 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11396806498 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79294 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 79294 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 79294 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 79294 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 79294 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 79294 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980461 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 980461 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 980461 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 980461 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 980461 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 980461 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11381703997 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11381703997 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11381703997 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11381703997 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11381703997 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11381703997 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079959 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.079959 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.079959 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11613.325336 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11613.325336 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079541 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.079541 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.079541 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.522926 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.522926 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64377 # number of replacements
-system.cpu.l2cache.tagsinuse 51361.576516 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1911659 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129770 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.731132 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2498200145000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36918.334944 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 32.795639 # Average occupied blocks per requestor
+system.cpu.l2cache.replacements 64335 # number of replacements
+system.cpu.l2cache.tagsinuse 51343.588717 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1886166 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129730 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.539166 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2498200830000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36928.997165 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 25.134248 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8184.403113 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6226.042472 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.563329 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000500 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 8156.882895 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6232.574061 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.563492 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000384 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124884 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.095002 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.783715 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79915 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11190 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 967706 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 386775 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1445586 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607265 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607265 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112880 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112880 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 79915 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 11190 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 967706 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 499655 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1558466 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 79915 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 11190 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 967706 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 499655 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1558466 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses
+system.cpu.l2cache.occ_percent::cpu.inst 0.124464 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.095102 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.783441 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53181 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10674 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 967006 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387028 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1417889 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607515 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607515 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 53181 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10674 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 967006 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 499935 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1530796 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 53181 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10674 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 967006 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 499935 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1530796 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12360 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12329 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10702 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23074 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12360 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143917 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156325 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst 12329 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143902 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156274 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12360 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143917 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156325 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3160000 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst 12329 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143902 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156274 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2844500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 702880500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 627994499 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1334152999 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 589500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 589500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6741992998 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6741992998 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3160000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695710500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 632225999 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1330898999 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 476500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732832500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6732832500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2844500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 702880500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7369987497 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8076145997 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3160000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 695710500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7365058499 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 8063731499 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2844500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 702880500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7369987497 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8076145997 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79961 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11192 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980066 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397492 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1468711 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607265 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607265 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246080 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246080 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79961 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 11192 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980066 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 643572 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1714791 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79961 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 11192 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980066 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 643572 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1714791 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000575 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000179 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012611 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015745 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985145 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985145 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.105263 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.105263 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541287 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541287 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000575 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000179 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012611 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223622 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.091163 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000575 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000179 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012611 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223622 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.091163 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68695.652174 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_latency::cpu.inst 695710500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7365058499 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 8063731499 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53222 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10676 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 979335 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 397730 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1440963 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607515 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607515 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246107 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246107 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53222 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10676 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 979335 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 643837 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1687070 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53222 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10676 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 979335 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 643837 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1687070 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000770 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000187 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.016013 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985488 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985488 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.300000 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541228 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541228 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000770 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000187 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.092630 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000770 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000187 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223507 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.092630 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69378.048780 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56867.354369 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58597.975086 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 57693.102659 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 202.021933 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 202.021933 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50615.563048 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50615.563048 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68695.652174 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56428.785790 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59075.499813 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 57679.596039 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.184932 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.184932 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50546.790541 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50546.790541 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56867.354369 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51209.985596 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51662.536363 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68695.652174 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51599.955840 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56867.354369 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51209.985596 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51662.536363 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51599.955840 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59127 # number of writebacks
-system.cpu.l2cache.writebacks::total 59127 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 59094 # number of writebacks
+system.cpu.l2cache.writebacks::total 59094 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12347 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23051 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12316 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 22999 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12347 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143856 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156251 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12316 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143840 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156199 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12347 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143856 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156251 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2584839 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12316 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143840 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156199 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2335079 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93252 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 548548146 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 492444540 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043670777 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29186917 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29186917 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5081813058 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5081813058 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2584839 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541798119 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 497025991 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1041252441 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072736540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072736540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2335079 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93252 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 548548146 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5574257598 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6125483835 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2584839 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541798119 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5569762531 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6113988981 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2335079 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93252 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 548548146 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5574257598 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6125483835 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541798119 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5569762531 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6113988981 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079407 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167001894776 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167006974183 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26372604056 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26372604056 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002423276 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007502683 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26890048041 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26890048041 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079407 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193374498832 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193379578239 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026808 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015695 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985145 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985145 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.105263 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.105263 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541287 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541287 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223527 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.091120 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223527 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.091120 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193892471317 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193897550724 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026752 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015961 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985488 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985488 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.300000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541228 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541228 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.092586 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.092586 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46626 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44427.646068 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46212.888514 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45276.594378 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.370459 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.370459 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43991.402972 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46712.969079 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45273.813688 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38151.749685 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38151.749685 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38083.607658 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38083.607658 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 643060 # number of replacements
-system.cpu.dcache.tagsinuse 511.992813 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21518829 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 643572 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.436553 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 42289000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.992813 # Average occupied blocks per requestor
+system.cpu.dcache.replacements 643325 # number of replacements
+system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
+system.cpu.dcache.total_refs 21505081 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 643837 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.401437 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13762862 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13762862 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7262343 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7262343 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 242888 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 242888 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21025205 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21025205 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21025205 # number of overall hits
-system.cpu.dcache.overall_hits::total 21025205 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 731521 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 731521 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2960125 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2960125 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13538 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13538 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3691646 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3691646 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3691646 # number of overall misses
-system.cpu.dcache.overall_misses::total 3691646 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9676520000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9676520000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 104419203240 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 104419203240 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181802500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 181802500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 271000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 271000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 114095723240 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 114095723240 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 114095723240 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 114095723240 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14494383 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14494383 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10222468 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10222468 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256426 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 256426 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247620 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247620 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24716851 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24716851 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24716851 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24716851 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050469 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050469 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289570 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.289570 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052795 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052795 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000077 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000077 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13227.945609 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13227.945609 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35275.268186 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35275.268186 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13429.051559 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13429.051559 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14263.157895 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14263.157895 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30906.463740 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30906.463740 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 28001 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 14318 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2522 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.102696 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 57.733871 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data 13751349 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13751349 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7259815 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7259815 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 243177 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 243177 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247604 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247604 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21011164 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21011164 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21011164 # number of overall hits
+system.cpu.dcache.overall_hits::total 21011164 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 737485 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 737485 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2962473 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2962473 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3699958 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3699958 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3699958 # number of overall misses
+system.cpu.dcache.overall_misses::total 3699958 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9781666500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9781666500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 104377974730 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 104377974730 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180159500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 180159500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 114159641230 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 114159641230 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 114159641230 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 114159641230 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14488834 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14488834 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222288 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222288 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256686 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256686 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247614 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247614 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24711122 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24711122 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24711122 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24711122 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050900 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050900 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289805 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.289805 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052629 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052629 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000040 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.149728 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.149728 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.149728 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.149728 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13263.546377 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13263.546377 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35233.392753 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35233.392753 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13336.257310 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13336.257310 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16600 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16600 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30854.307327 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30854.307327 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 29793 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 16864 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2613 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.401837 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 67.187251 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607265 # number of writebacks
-system.cpu.dcache.writebacks::total 607265 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346124 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 346124 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711175 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2711175 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1351 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3057299 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3057299 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3057299 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3057299 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385397 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385397 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248950 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 248950 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12187 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634347 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634347 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634347 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634347 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4799633500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4799633500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8191877422 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8191877422 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142320500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142320500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 233000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 233000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12991510922 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12991510922 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12991510922 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12991510922 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395110500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395110500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36212514849 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36212514849 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218607625349 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 218607625349 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026589 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047526 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047526 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000077 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12453.738612 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12453.738612 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32905.713685 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32905.713685 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11678.058587 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11678.058587 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12263.157895 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12263.157895 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607515 # number of writebacks
+system.cpu.dcache.writebacks::total 607515 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351842 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 351842 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713489 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2713489 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1336 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1336 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3065331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3065331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3065331 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3065331 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385643 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385643 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248984 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 22:02:35
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 13 2013 11:38:19
+gem5 started Feb 13 2013 21:11:40
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1092968826500 because m5_exit instruction encountered
+Exiting @ tick 1102937390000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.103053 # Number of seconds simulated
-sim_ticks 1103052934500 # Number of ticks simulated
-final_tick 1103052934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.102937 # Number of seconds simulated
+sim_ticks 1102937390000 # Number of ticks simulated
+final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 84555 # Simulator instruction rate (inst/s)
-host_op_rate 108843 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1514437253 # Simulator tick rate (ticks/s)
-host_mem_usage 415912 # Number of bytes of host memory used
-host_seconds 728.36 # Real time elapsed on the host
-sim_insts 61586372 # Number of instructions simulated
-sim_ops 79276491 # Number of ops (including micro ops) simulated
+host_inst_rate 67484 # Simulator instruction rate (inst/s)
+host_op_rate 86868 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1208579190 # Simulator tick rate (ticks/s)
+host_mem_usage 412736 # Number of bytes of host memory used
+host_seconds 912.59 # Real time elapsed on the host
+sim_insts 61585042 # Number of instructions simulated
+sim_ops 79274675 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 409536 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4368116 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 405952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5246000 # Number of bytes read from this memory
-system.physmem.bytes_read::total 59190564 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 409536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 405952 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4268032 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory
+system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7295376 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6399 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 68324 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 6343 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 81995 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6257943 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66688 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 823524 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 44203485 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 371275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3960024 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 1102 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 368026 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 4755891 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 53660674 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 371275 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 368026 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 739301 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3869290 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 15412 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 2729102 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 6613804 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3869290 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 44203485 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 371275 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3975436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 1102 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 368026 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 7484993 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 60274478 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 6257943 # Total number of read requests seen
-system.physmem.writeReqs 823524 # Total number of write requests seen
-system.physmem.cpureqs 281760 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 400508352 # Total number of bytes read from memory
-system.physmem.bytesWritten 52705536 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 59190564 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7295376 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 12603 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 391392 # Track reads on a per bank basis
+system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 6257788 # Total number of read requests seen
+system.physmem.writeReqs 823390 # Total number of write requests seen
+system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 400498432 # Total number of bytes read from memory
+system.physmem.bytesWritten 52696960 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 390903 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 391629 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 391534 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 390909 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 391652 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 391399 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 390860 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 390463 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 391269 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 51232 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51695 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50999 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 51006 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 51676 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 51498 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51880 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51836 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2168609 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1103051731500 # Total gap between requests
+system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1102936257500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 105 # Categorize read packet sizes
system.physmem.readPktSize::3 6094848 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 162990 # Categorize read packet sizes
+system.physmem.readPktSize::6 162835 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2925445 # categorize write packet sizes
+system.physmem.writePktSize::2 2999773 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 66688 # categorize write packet sizes
+system.physmem.writePktSize::6 66554 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 12603 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 12623 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 494466 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 430633 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 391954 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1441360 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 1085395 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1097883 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1063934 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 26865 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 24928 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 44608 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 63920 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 44461 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 12221 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 11894 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 16880 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 6309 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 493621 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 430392 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 391768 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 1441431 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 1086063 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1098338 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1064335 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 26976 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 24854 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 44565 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 63872 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 44300 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 12061 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 11818 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 17153 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 5993 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2971 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3069 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3394 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3530 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3628 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3727 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3843 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3929 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32835 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32737 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32580 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32412 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32276 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32178 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32079 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31877 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2895 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2949 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2985 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 3021 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 3044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 3067 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 3100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 3123 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 3149 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32851 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32815 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32779 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32756 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32733 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32700 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32677 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32651 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 198980528034 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 238811291784 # Sum of mem lat for all requests
-system.physmem.totBusLat 31289360000 # Total cycles spent in databus access
-system.physmem.totBankLat 8541403750 # Total cycles spent in bank access
-system.physmem.avgQLat 31796.84 # Average queueing delay per request
-system.physmem.avgBankLat 1364.91 # Average bank access latency per request
+system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests
+system.physmem.totBusLat 31288540000 # Total cycles spent in databus access
+system.physmem.totBankLat 8531820000 # Total cycles spent in bank access
+system.physmem.avgQLat 31828.06 # Average queueing delay per request
+system.physmem.avgBankLat 1363.41 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 38161.74 # Average memory access latency
-system.physmem.avgRdBW 363.09 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 38191.47 # Average memory access latency
+system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.21 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.22 # Average read queue length over time
-system.physmem.avgWrQLen 10.13 # Average write queue length over time
-system.physmem.readRowHits 6214096 # Number of row buffer hits during reads
-system.physmem.writeRowHits 800077 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 10.24 # Average write queue length over time
+system.physmem.readRowHits 6213872 # Number of row buffer hits during reads
+system.physmem.writeRowHits 799892 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes
-system.physmem.avgGap 155765.99 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 72694 # number of replacements
-system.l2c.tagsinuse 53751.744794 # Cycle average of tags in use
-system.l2c.total_refs 1868125 # Total number of references to valid blocks.
-system.l2c.sampled_refs 137855 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.551376 # Average number of references to valid blocks.
+system.physmem.avgGap 155756.04 # Average gap between requests
+system.l2c.replacements 72539 # number of replacements
+system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use
+system.l2c.total_refs 1841179 # Total number of references to valid blocks.
+system.l2c.sampled_refs 137732 # Sample count of references to valid blocks.
+system.l2c.avg_refs 13.367838 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 39374.569084 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 4.396186 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4014.541431 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 2824.438134 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 12.707800 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3714.133429 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 3806.957928 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.600808 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000067 # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.061257 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.043098 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.056673 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.058090 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 30721 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 4484 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 386372 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 166390 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 49432 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 5306 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 590682 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 197805 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1431192 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 580622 # number of Writeback hits
-system.l2c.Writeback_hits::total 580622 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 1197 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 732 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1929 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 144 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 337 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 48357 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 58516 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 106873 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 30721 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 4484 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 386372 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 214747 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 49432 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 5306 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 590682 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 256321 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1538065 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 30721 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 4484 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 386372 # number of overall hits
-system.l2c.overall_hits::cpu0.data 214747 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 49432 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 5306 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 590682 # number of overall hits
-system.l2c.overall_hits::cpu1.data 256321 # number of overall hits
-system.l2c.overall_hits::total 1538065 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses
+system.l2c.occ_percent::cpu0.inst 0.061172 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.042983 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.056720 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.058048 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.820194 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 21699 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 4247 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 385844 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 166771 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 30512 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 5160 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 591639 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 198020 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1403892 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 581178 # number of Writeback hits
+system.l2c.Writeback_hits::total 581178 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 1163 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 739 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 1902 # number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 58985 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 107027 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 21699 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 4247 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 385844 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 214813 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 30512 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 5160 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 591639 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 257005 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1510919 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 21699 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 4247 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 385844 # number of overall hits
+system.l2c.overall_hits::cpu0.data 214813 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 30512 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 5160 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 591639 # number of overall hits
+system.l2c.overall_hits::cpu1.data 257005 # number of overall hits
+system.l2c.overall_hits::total 1510919 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 6279 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6405 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 6268 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6367 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 20 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 6307 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 6279 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 25304 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 5117 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 3778 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 8895 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 645 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 410 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1055 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 63308 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 76937 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140245 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu1.data 6294 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 25269 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 5150 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 3804 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 8954 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data 644 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 418 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 1062 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 63486 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 76591 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140077 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 6279 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 69713 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 6268 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 69853 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 6307 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 83216 # number of demand (read+write) misses
-system.l2c.demand_misses::total 165549 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 13 # number of overall misses
+system.l2c.demand_misses::cpu1.data 82885 # number of demand (read+write) misses
+system.l2c.demand_misses::total 165346 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 6279 # number of overall misses
-system.l2c.overall_misses::cpu0.data 69713 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 6268 # number of overall misses
+system.l2c.overall_misses::cpu0.data 69853 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 20 # number of overall misses
system.l2c.overall_misses::cpu1.inst 6307 # number of overall misses
-system.l2c.overall_misses::cpu1.data 83216 # number of overall misses
-system.l2c.overall_misses::total 165549 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 866000 # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu1.data 82885 # number of overall misses
+system.l2c.overall_misses::total 165346 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 727500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 346153000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 371240998 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1307000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 373262000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 389251500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1482198498 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 8863481 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 11767500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 20630981 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu0.data 635500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2866500 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 3502000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 3126825491 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 4141243497 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7268068988 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 866000 # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 346856000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 362407499 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1360500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 380856500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 395446999 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1487772998 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 8791989 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 11737000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 20528989 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2890499 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 3481499 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 3145264486 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 4121590993 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7266855479 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 727500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 346153000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 3498066489 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 1307000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 373262000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 4530494997 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 8750267486 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 866000 # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 346856000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 3507671985 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 1360500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 380856500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 4517037992 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 8754628477 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 727500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 346153000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 3498066489 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 1307000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 373262000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 4530494997 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 8750267486 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 30734 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 4486 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 392651 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 172795 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 49451 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 5306 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 596989 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 204084 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1456496 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 580622 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 580622 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 6314 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 4510 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 10824 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 838 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 554 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1392 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 111665 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 135453 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 247118 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 30734 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 4486 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 392651 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 284460 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 49451 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 5306 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 596989 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 339537 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1703614 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 30734 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 4486 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 392651 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 284460 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 49451 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 5306 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 596989 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 339537 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1703614 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000423 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000446 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015991 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.037067 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.010565 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.030767 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.017373 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.810421 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.837694 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.821785 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.769690 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.740072 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.757902 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.566946 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.567998 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.567522 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000423 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000446 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015991 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.245071 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.010565 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.245087 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.097175 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000423 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000446 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015991 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.245071 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000384 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.010565 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.245087 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.097175 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66615.384615 # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst 346856000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 3507671985 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 1360500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 380856500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 4517037992 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 8754628477 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 21710 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 4249 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 392112 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 173138 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 30532 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 5160 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 597946 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 204314 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1429161 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 581178 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 581178 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 6313 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 4543 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 10856 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 845 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 561 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 1406 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 111528 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 135576 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 247104 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 21710 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 4249 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 392112 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 284666 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 30532 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 5160 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 597946 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 339890 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1676265 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 21710 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 4249 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 392112 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 284666 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 30532 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 5160 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 597946 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 339890 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1676265 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000471 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015985 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.036774 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.010548 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.030806 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.017681 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.815777 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.837332 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.824797 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.762130 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.745098 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.755334 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.569238 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.564930 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.566875 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000471 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015985 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.245386 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.010548 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.243858 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.098640 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000507 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000471 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015985 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.245386 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000655 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.010548 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.243858 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.098640 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55128.682911 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 57961.123810 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68789.473684 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 59182.178532 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 61992.594362 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 58575.659896 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1732.163572 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3114.743250 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 2319.390781 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 985.271318 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6991.463415 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 3319.431280 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49390.685079 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53826.422878 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 51824.086335 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66615.384615 # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55337.587747 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 56919.663735 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 68025 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60386.316791 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 62829.202256 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 58877.399106 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1707.182330 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3085.436383 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 2292.717110 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 917.701863 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6915.069378 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 3278.247646 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49542.646977 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53812.993602 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 51877.577896 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 55128.682911 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 50178.108660 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68789.473684 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 59182.178532 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 54442.595138 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 52856.057639 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66615.384615 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 55337.587747 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 50215.051394 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 68025 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 60386.316791 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 54497.653279 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 52947.325469 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66136.363636 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 55128.682911 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 50178.108660 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68789.473684 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 59182.178532 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 54442.595138 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 52856.057639 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 55337.587747 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 50215.051394 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 68025 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 60386.316791 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 54497.653279 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 52947.325469 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 66688 # number of writebacks
-system.l2c.writebacks::total 66688 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks 66554 # number of writebacks
+system.l2c.writebacks::total 66554 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data 36 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data 36 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 8 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data 36 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 13 # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 6274 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 6367 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 6300 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 6255 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 25230 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 5117 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 3778 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 8895 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 645 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 410 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1055 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 63308 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 76937 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 140245 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 13 # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 6264 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 6331 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 20 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 6299 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 6270 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 25197 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 5150 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 3804 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 8954 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 644 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 418 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 1062 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 63486 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 76591 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 140077 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 6274 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 69675 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 6300 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 83192 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 165475 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 13 # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 6264 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 69817 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 20 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 6299 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 82861 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 165274 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 6274 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 69675 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 6300 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 83192 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 165475 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 703776 # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu0.inst 6264 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 69817 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 20 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 6299 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 82861 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 165274 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 591272 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93252 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 267795677 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 290384918 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 294482820 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 309773212 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1164302443 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51487468 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38421208 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 89908676 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6482629 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4115405 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 10598034 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2342205029 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3178812212 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5521017241 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 703776 # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 268680120 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 282241162 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1109289 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 302073229 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 316163964 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1170952288 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51809007 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38459231 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 90268238 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6463131 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4201410 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 10664541 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2358483918 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3163514299 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5521998217 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 591272 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93252 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 267795677 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2632589947 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 294482820 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 3488585424 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 6685319684 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 703776 # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 268680120 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 2640725080 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1109289 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 302073229 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 3479678263 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 6692950505 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 591272 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93252 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 267795677 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2632589947 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1068788 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 294482820 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 3488585424 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 6685319684 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 268680120 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 2640725080 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1109289 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 302073229 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 3479678263 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 6692950505 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299167 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408113059 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2070313 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667167003 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 167082649542 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050139238 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25325633830 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 26375773068 # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12406738561 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100314 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667521253 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 167081659295 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050184240 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25918449225 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 26968633465 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299167 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458252297 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2070313 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 179992800833 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 193458422610 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036847 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030649 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.017322 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810421 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837694 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.821785 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769690 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.740072 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.757902 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566946 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567998 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.567522 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.097132 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.244938 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010553 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.245016 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.097132 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13456922801 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100314 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180585970478 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 194050292760 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000507 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000471 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015975 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036566 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000655 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010534 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030688 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.017631 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.815777 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837332 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.824797 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.762130 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.745098 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755334 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569238 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564930 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.566875 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000507 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000471 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015975 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.245259 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000655 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010534 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.243788 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.098597 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000507 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000471 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015975 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.245259 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000655 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010534 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.243788 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.098597 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45607.808701 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49524.094644 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 46147.540349 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10062.041821 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10169.721546 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.776953 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10050.587597 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.573171 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10045.529858 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36996.983462 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41317.080364 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 39366.945281 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44580.818512 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50424.874641 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 46471.893003 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.001359 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10110.207939 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10081.331025 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.917702 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10051.220096 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.940678 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37149.669502 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41303.995234 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 39421.162768 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37823.525502 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41994.162067 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 40496.088344 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53752 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37823.525502 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41994.162067 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 40496.088344 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 6009414 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 4584575 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 296794 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 3746905 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 2916795 # Number of BTB hits
+system.cpu0.branchPred.lookups 5998436 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 77.845448 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 672462 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 28490 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8911826 # DTB read hits
-system.cpu0.dtb.read_misses 33481 # DTB read misses
-system.cpu0.dtb.write_hits 5139826 # DTB write hits
-system.cpu0.dtb.write_misses 6231 # DTB write misses
+system.cpu0.dtb.read_hits 8902974 # DTB read hits
+system.cpu0.dtb.read_misses 28685 # DTB read misses
+system.cpu0.dtb.write_hits 5134917 # DTB write hits
+system.cpu0.dtb.write_misses 5599 # DTB write misses
system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2125 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 943 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 378 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8945307 # DTB read accesses
-system.cpu0.dtb.write_accesses 5146057 # DTB write accesses
+system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 8931659 # DTB read accesses
+system.cpu0.dtb.write_accesses 5140516 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14051652 # DTB hits
-system.cpu0.dtb.misses 39712 # DTB misses
-system.cpu0.dtb.accesses 14091364 # DTB accesses
-system.cpu0.itb.inst_hits 4224274 # ITB inst hits
-system.cpu0.itb.inst_misses 5167 # ITB inst misses
+system.cpu0.dtb.hits 14037891 # DTB hits
+system.cpu0.dtb.misses 34284 # DTB misses
+system.cpu0.dtb.accesses 14072175 # DTB accesses
+system.cpu0.itb.inst_hits 4215172 # ITB inst hits
+system.cpu0.itb.inst_misses 5141 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 4229441 # ITB inst accesses
-system.cpu0.itb.hits 4224274 # DTB hits
-system.cpu0.itb.misses 5167 # DTB misses
-system.cpu0.itb.accesses 4229441 # DTB accesses
-system.cpu0.numCycles 67942321 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses
+system.cpu0.itb.hits 4215172 # DTB hits
+system.cpu0.itb.misses 5141 # DTB misses
+system.cpu0.itb.accesses 4220313 # DTB accesses
+system.cpu0.numCycles 67779631 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 11770700 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 32037426 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 6009414 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 3589257 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 7522750 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1459790 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 61665 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 20761422 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 4873 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 52782 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 85653 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 4222584 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 157713 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 41308500 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.002087 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.382378 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 33793144 81.81% 81.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 566641 1.37% 83.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 818694 1.98% 85.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 676082 1.64% 86.80% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 774764 1.88% 88.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 559890 1.36% 90.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 668973 1.62% 91.65% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 352395 0.85% 92.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 3097917 7.50% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 41308500 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.088449 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.471539 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 12285141 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 20700852 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 6822655 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 515208 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 984644 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 935535 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 64887 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 40031733 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 213257 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 984644 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 12853776 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 5827758 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 12754498 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 6718585 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 2169239 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 38928303 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2058 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 438319 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1238743 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 39288298 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 175811025 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 175776420 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 34605 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 30930446 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 8357851 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 411337 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 370395 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5357325 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 7655234 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5687790 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1133384 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1222152 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 36851355 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 895739 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 37254250 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 80693 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 6299190 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13209610 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 256967 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 41308500 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.901854 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.509387 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 26145285 63.29% 63.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 5753076 13.93% 77.22% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3163283 7.66% 84.88% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2484845 6.02% 90.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2098538 5.08% 95.97% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 943313 2.28% 98.26% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 484190 1.17% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 183544 0.44% 99.87% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 52426 0.13% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 41308500 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 25686 2.41% 2.41% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 841970 78.85% 81.30% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 199670 18.70% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 22338200 59.96% 60.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 46968 0.13% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 17 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 14 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 60.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 9368796 25.15% 85.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5447325 14.62% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 37254250 # Type of FU issued
-system.cpu0.iq.rate 0.548322 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1067780 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.028662 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 116996499 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 44054105 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 34350443 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 8454 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 4728 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 3907 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 38265398 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 307211 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued
+system.cpu0.iq.rate 0.549060 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1378796 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2415 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 13078 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 537331 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2192757 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 5650 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 984644 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 4190634 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 100027 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 37865226 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 85653 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 7655234 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5687790 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 571722 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 40568 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3395 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 13078 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 150532 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 118543 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 269075 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 36877414 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 9226875 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 376836 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 118132 # number of nop insts executed
-system.cpu0.iew.exec_refs 14626534 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 4859341 # Number of branches executed
-system.cpu0.iew.exec_stores 5399659 # Number of stores executed
-system.cpu0.iew.exec_rate 0.542775 # Inst execution rate
-system.cpu0.iew.wb_sent 36683533 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 34354350 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 18308250 # num instructions producing a value
-system.cpu0.iew.wb_consumers 35218685 # num instructions consuming a value
+system.cpu0.iew.exec_nop 118422 # number of nop insts executed
+system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 4852888 # Number of branches executed
+system.cpu0.iew.exec_stores 5394475 # Number of stores executed
+system.cpu0.iew.exec_rate 0.543552 # Inst execution rate
+system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 18273947 # num instructions producing a value
+system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.505640 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.519845 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6121232 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 638772 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 232995 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 40323856 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.775878 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.738297 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 28652168 71.06% 71.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 5718960 14.18% 85.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1913940 4.75% 89.98% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 975658 2.42% 92.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 781823 1.94% 94.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 527081 1.31% 95.65% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 383426 0.95% 96.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 217091 0.54% 97.14% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1153709 2.86% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 40323856 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 23679897 # Number of instructions committed
-system.cpu0.commit.committedOps 31286376 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 23670531 # Number of instructions committed
+system.cpu0.commit.committedOps 31269562 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 11426897 # Number of memory references committed
-system.cpu0.commit.loads 6276438 # Number of loads committed
-system.cpu0.commit.membars 229667 # Number of memory barriers committed
-system.cpu0.commit.branches 4245099 # Number of branches committed
+system.cpu0.commit.refs 11418468 # Number of memory references committed
+system.cpu0.commit.loads 6271892 # Number of loads committed
+system.cpu0.commit.membars 229609 # Number of memory barriers committed
+system.cpu0.commit.branches 4243643 # Number of branches committed
system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 27642973 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 489349 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1153709 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 27627358 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 489165 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1149237 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 75726635 # The number of ROB reads
-system.cpu0.rob.rob_writes 75801988 # The number of ROB writes
-system.cpu0.timesIdled 359866 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26633821 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2138121828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 23599155 # Number of Instructions Simulated
-system.cpu0.committedOps 31205634 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 23599155 # Number of Instructions Simulated
-system.cpu0.cpi 2.879015 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.879015 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.347341 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.347341 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 171917289 # number of integer regfile reads
-system.cpu0.int_regfile_writes 34107060 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 3422 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 966 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 13053108 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 451057 # number of misc regfile writes
-system.cpu0.icache.replacements 392744 # number of replacements
-system.cpu0.icache.tagsinuse 511.016860 # Cycle average of tags in use
-system.cpu0.icache.total_refs 3798516 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 393256 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 9.659143 # Average number of references to valid blocks.
+system.cpu0.rob.rob_reads 75500320 # The number of ROB reads
+system.cpu0.rob.rob_writes 75691570 # The number of ROB writes
+system.cpu0.timesIdled 360084 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26658070 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2138053443 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 23589789 # Number of Instructions Simulated
+system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated
+system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 171728285 # number of integer regfile reads
+system.cpu0.int_regfile_writes 34072180 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 3295 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 900 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 12998314 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 450987 # number of misc regfile writes
+system.cpu0.icache.replacements 392135 # number of replacements
+system.cpu0.icache.tagsinuse 511.076170 # Cycle average of tags in use
+system.cpu0.icache.total_refs 3790159 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 392647 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 9.652841 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 511.016860 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.998080 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.998080 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 3798516 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 3798516 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 3798516 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 3798516 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 3798516 # number of overall hits
-system.cpu0.icache.overall_hits::total 3798516 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 423935 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 423935 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 423935 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 423935 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 423935 # number of overall misses
-system.cpu0.icache.overall_misses::total 423935 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803194996 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5803194996 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 5803194996 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5803194996 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 5803194996 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5803194996 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222451 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 4222451 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 4222451 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 4222451 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 4222451 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 4222451 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100400 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.100400 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100400 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.100400 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100400 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.100400 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13688.879182 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13688.879182 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13688.879182 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13688.879182 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3086 # number of cycles access was blocked
+system.cpu0.icache.occ_blocks::cpu0.inst 511.076170 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 3790159 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 3790159 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 3790159 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 3790159 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 3790159 # number of overall hits
+system.cpu0.icache.overall_hits::total 3790159 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 423214 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 423214 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 423214 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 423214 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 423214 # number of overall misses
+system.cpu0.icache.overall_misses::total 423214 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5793685997 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 5793685997 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 5793685997 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 5793685997 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 5793685997 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 5793685997 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213373 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 4213373 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 4213373 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 4213373 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 4213373 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 4213373 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100445 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.100445 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100445 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.100445 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100445 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.100445 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13689.731429 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13689.731429 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 2401 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 146 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.932515 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.445205 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30660 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 30660 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 30660 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 30660 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 30660 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 30660 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393275 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 393275 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 393275 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 393275 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 393275 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 393275 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745687496 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745687496 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745687496 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4745687496 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745687496 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4745687496 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30547 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 30547 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 30547 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 30547 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 30547 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 30547 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392667 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 392667 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 392667 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 392667 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 392667 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 392667 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4739152997 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 4739152997 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4739152997 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 4739152997 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4739152997 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 4739152997 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093139 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.093139 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.093139 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.096805 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093195 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.093195 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.093195 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 275861 # number of replacements
-system.cpu0.dcache.tagsinuse 459.614904 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 9266976 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 276373 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 33.530685 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 43517000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 459.614904 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.897685 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.897685 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 5785932 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 5785932 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3160921 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3160921 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139137 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 139137 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137051 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 137051 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 8946853 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 8946853 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 8946853 # number of overall hits
-system.cpu0.dcache.overall_hits::total 8946853 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 390976 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 390976 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1582272 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1582272 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1973248 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1973248 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1973248 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1973248 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5434487500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5434487500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60315071371 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 60315071371 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88202500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 88202500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46670000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 46670000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 65749558871 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 65749558871 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 65749558871 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 65749558871 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176908 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 6176908 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743193 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 4743193 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147912 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 147912 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144535 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 144535 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 10920101 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 10920101 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 10920101 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 10920101 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063296 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.063296 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333588 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.333588 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059326 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059326 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051780 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051780 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180699 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.180699 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180699 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.180699 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13899.798197 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13899.798197 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38119.281243 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38119.281243 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10051.566952 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10051.566952 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6235.970069 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6235.970069 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33320.474097 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33320.474097 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33320.474097 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 8364 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 5666 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 593 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.104553 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 69.950617 # average number of cycles each access was blocked
+system.cpu0.dcache.replacements 276137 # number of replacements
+system.cpu0.dcache.tagsinuse 461.136878 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 9254727 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 276649 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 33.452957 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 43495000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data 461.136878 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.900658 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total 0.900658 # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data 5777010 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 5777010 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3157960 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3157960 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139054 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 139054 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137010 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 137010 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 8934970 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 8934970 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 8934970 # number of overall hits
+system.cpu0.dcache.overall_hits::total 8934970 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 392909 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 392909 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1581686 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1581686 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8773 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 8773 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7509 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 7509 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1974595 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 1974595 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1974595 # number of overall misses
+system.cpu0.dcache.overall_misses::total 1974595 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5473319500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 5473319500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60618366371 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 60618366371 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87499000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 87499000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46786000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 46786000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 66091685871 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 66091685871 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 66091685871 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 66091685871 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 6169919 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 6169919 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739646 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4739646 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147827 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 147827 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144519 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 144519 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 10909565 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 10909565 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 10909565 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 10909565 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063681 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.063681 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333714 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.333714 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059346 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059346 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051959 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051959 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180997 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.180997 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180997 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.180997 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9973.669212 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9973.669212 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6230.656545 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6230.656545 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 9022 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 2690 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 641 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.074883 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 33.625000 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 256398 # number of writebacks
-system.cpu0.dcache.writebacks::total 256398 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202708 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 202708 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451928 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1451928 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 451 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 451 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1654636 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1654636 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1654636 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1654636 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188268 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 188268 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130344 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 130344 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8324 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 318612 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 318612 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 318612 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 318612 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2372133500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2372133500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4018964492 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4018964492 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66568500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66568500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31704000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31704000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6391097992 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 6391097992 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6391097992 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 6391097992 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514906500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514906500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180228378 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180228378 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695134878 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695134878 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030479 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030479 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027480 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027480 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056277 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056277 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051773 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051773 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.029177 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.029177 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12599.770009 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12599.770009 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30833.521236 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30833.521236 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7997.176838 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7997.176838 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4236.803421 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4236.803421 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 256527 # number of writebacks
+system.cpu0.dcache.writebacks::total 256527 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204116 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 204116 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451395 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1451395 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655511 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1655511 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655511 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1655511 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188793 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 188793 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130291 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 130291 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8302 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8302 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7505 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 7505 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 319084 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 319084 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 319084 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 319084 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371443000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371443000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4036122491 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4036122491 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65692500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65692500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31776000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31776000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6407565491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 6407565491 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6407565491 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 6407565491 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513513000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513513000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180350378 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180350378 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693863378 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693863378 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030599 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030599 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027490 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027490 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056160 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056160 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051931 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051931 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.029248 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.029248 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.852325 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.852325 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4233.977348 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4233.977348 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 9060826 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 7443379 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 410189 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 6060421 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 5228505 # Number of BTB hits
+system.cpu1.branchPred.lookups 9086614 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 86.272967 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 772521 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 43024 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 42893856 # DTB read hits
-system.cpu1.dtb.read_misses 41286 # DTB read misses
-system.cpu1.dtb.write_hits 6825448 # DTB write hits
-system.cpu1.dtb.write_misses 11345 # DTB write misses
+system.cpu1.dtb.read_hits 42908069 # DTB read hits
+system.cpu1.dtb.read_misses 37093 # DTB read misses
+system.cpu1.dtb.write_hits 6828111 # DTB write hits
+system.cpu1.dtb.write_misses 10566 # DTB write misses
system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2300 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 2725 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 348 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 42935142 # DTB read accesses
-system.cpu1.dtb.write_accesses 6836793 # DTB write accesses
+system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 42945162 # DTB read accesses
+system.cpu1.dtb.write_accesses 6838677 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 49719304 # DTB hits
-system.cpu1.dtb.misses 52631 # DTB misses
-system.cpu1.dtb.accesses 49771935 # DTB accesses
-system.cpu1.itb.inst_hits 8340296 # ITB inst hits
-system.cpu1.itb.inst_misses 5581 # ITB inst misses
+system.cpu1.dtb.hits 49736180 # DTB hits
+system.cpu1.dtb.misses 47659 # DTB misses
+system.cpu1.dtb.accesses 49783839 # DTB accesses
+system.cpu1.itb.inst_hits 8400139 # ITB inst hits
+system.cpu1.itb.inst_misses 5511 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1543 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1561 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8345877 # ITB inst accesses
-system.cpu1.itb.hits 8340296 # DTB hits
-system.cpu1.itb.misses 5581 # DTB misses
-system.cpu1.itb.accesses 8345877 # DTB accesses
-system.cpu1.numCycles 408908787 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses
+system.cpu1.itb.hits 8400139 # DTB hits
+system.cpu1.itb.misses 5511 # DTB misses
+system.cpu1.itb.accesses 8405650 # DTB accesses
+system.cpu1.numCycles 408778710 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 19741855 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 65652351 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 9060826 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 6001026 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 14075401 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3918937 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 65639 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 77552970 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 4686 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 46851 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 129796 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 8338330 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 726090 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3044 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 114288783 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.696009 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.038635 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 100220679 87.69% 87.69% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 798295 0.70% 88.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 938778 0.82% 89.21% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1873808 1.64% 90.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1510998 1.32% 92.17% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 574008 0.50% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 2116066 1.85% 94.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 410869 0.36% 94.89% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 5845282 5.11% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 114288783 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.022159 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.160555 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 21260604 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 77197159 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 12728983 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 527252 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2574785 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1107873 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 98231 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 74815491 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 327601 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 2574785 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 22637961 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 32138028 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 40746993 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11784015 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 4407001 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 69468156 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 19628 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 681075 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 3151682 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 32928 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 73408550 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 319754725 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 319695969 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 58756 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 49044244 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 24364306 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 444465 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 387610 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 7946566 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 13166209 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 8131289 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 1039797 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1544280 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 63306558 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1157694 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 89041269 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 96485 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 16034557 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 45010776 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 277192 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 114288783 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.779090 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.516652 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 83847546 73.36% 73.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 8475969 7.42% 80.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 4322490 3.78% 84.56% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3758453 3.29% 87.85% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 10560015 9.24% 97.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1959947 1.71% 98.81% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1018953 0.89% 99.70% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 271832 0.24% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 73578 0.06% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 114288783 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 29343 0.37% 0.37% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 994 0.01% 0.39% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 7546096 95.87% 96.25% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 294849 3.75% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 37546524 42.17% 42.52% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 59182 0.07% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 43946850 49.36% 91.94% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 7173254 8.06% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 89041269 # Type of FU issued
-system.cpu1.iq.rate 0.217753 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 7871282 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.088400 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 300376626 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 80507257 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 53605393 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 14907 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6781 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 96590759 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7860 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 340884 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued
+system.cpu1.iq.rate 0.218115 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 3415033 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 17027 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1294633 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 31913246 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 874031 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2574785 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 24237525 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 363690 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 64568060 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 112440 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 13166209 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 8131289 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 869125 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 67667 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 3747 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 17027 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 202949 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 155576 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 358525 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 86656974 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 43263445 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2384295 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 103808 # number of nop insts executed
-system.cpu1.iew.exec_refs 50374669 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 6998395 # Number of branches executed
-system.cpu1.iew.exec_stores 7111224 # Number of stores executed
-system.cpu1.iew.exec_rate 0.211923 # Inst execution rate
-system.cpu1.iew.wb_sent 85695257 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 53612174 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 29896757 # num instructions producing a value
-system.cpu1.iew.wb_consumers 53335024 # num instructions consuming a value
+system.cpu1.iew.exec_nop 104517 # number of nop insts executed
+system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 7007502 # Number of branches executed
+system.cpu1.iew.exec_stores 7113991 # Number of stores executed
+system.cpu1.iew.exec_rate 0.212186 # Inst execution rate
+system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 29917161 # num instructions producing a value
+system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.131110 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.560546 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 15938596 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 880502 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 313478 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 111713998 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.430926 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.399973 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 94998150 85.04% 85.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 8214546 7.35% 92.39% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2111823 1.89% 94.28% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1251354 1.12% 95.40% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1240107 1.11% 96.51% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 568335 0.51% 97.02% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 995989 0.89% 97.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 499347 0.45% 98.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1834347 1.64% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 111713998 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 38056856 # Number of instructions committed
-system.cpu1.commit.committedOps 48140496 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 38064892 # Number of instructions committed
+system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16587832 # Number of memory references committed
-system.cpu1.commit.loads 9751176 # Number of loads committed
-system.cpu1.commit.membars 190071 # Number of memory barriers committed
-system.cpu1.commit.branches 5966416 # Number of branches committed
-system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 42676497 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 534458 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1834347 # number cycles where commit BW limit reached
+system.cpu1.commit.refs 16595277 # Number of memory references committed
+system.cpu1.commit.loads 9755144 # Number of loads committed
+system.cpu1.commit.membars 190149 # Number of memory barriers committed
+system.cpu1.commit.branches 5967637 # Number of branches committed
+system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 534638 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 172914942 # The number of ROB reads
-system.cpu1.rob.rob_writes 130824932 # The number of ROB writes
-system.cpu1.timesIdled 1407670 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 294620004 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 1796556351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 37987217 # Number of Instructions Simulated
-system.cpu1.committedOps 48070857 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 37987217 # Number of Instructions Simulated
-system.cpu1.cpi 10.764379 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 10.764379 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.092899 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.092899 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 387772369 # number of integer regfile reads
-system.cpu1.int_regfile_writes 56145305 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 4887 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 18518507 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 405334 # number of misc regfile writes
-system.cpu1.icache.replacements 597077 # number of replacements
-system.cpu1.icache.tagsinuse 480.917703 # Cycle average of tags in use
-system.cpu1.icache.total_refs 7696282 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 597589 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 12.878888 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 74223543500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 480.917703 # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst 0.939292 # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total 0.939292 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 7696282 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 7696282 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 7696282 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 7696282 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 7696282 # number of overall hits
-system.cpu1.icache.overall_hits::total 7696282 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 641998 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 641998 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 641998 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 641998 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 641998 # number of overall misses
-system.cpu1.icache.overall_misses::total 641998 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8633779496 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 8633779496 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 8633779496 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 8633779496 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 8633779496 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 8633779496 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 8338280 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 8338280 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 8338280 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 8338280 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 8338280 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 8338280 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076994 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.076994 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076994 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.076994 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076994 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.076994 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13448.296562 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13448.296562 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13448.296562 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13448.296562 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13448.296562 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked
+system.cpu1.rob.rob_reads 173015978 # The number of ROB reads
+system.cpu1.rob.rob_writes 131360292 # The number of ROB writes
+system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 37995253 # Number of Instructions Simulated
+system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 37995253 # Number of Instructions Simulated
+system.cpu1.cpi 10.758678 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 10.758678 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.092948 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.092948 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 388090475 # number of integer regfile reads
+system.cpu1.int_regfile_writes 56232580 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 4956 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 18472941 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 405527 # number of misc regfile writes
+system.cpu1.icache.replacements 597992 # number of replacements
+system.cpu1.icache.tagsinuse 480.750463 # Cycle average of tags in use
+system.cpu1.icache.total_refs 7754983 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 598504 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 12.957278 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 74232640500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 480.750463 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.938966 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.938966 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 7754983 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 7754983 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 7754983 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 7754983 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 7754983 # number of overall hits
+system.cpu1.icache.overall_hits::total 7754983 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 643188 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 643188 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 643188 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 643188 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 643188 # number of overall misses
+system.cpu1.icache.overall_misses::total 643188 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8662129496 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 8662129496 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 8662129496 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 8662129496 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 8662129496 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 8662129496 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 8398171 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 8398171 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 8398171 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 8398171 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 8398171 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 8398171 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076587 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.076587 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076587 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.076587 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076587 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.076587 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.492391 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.492391 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13467.492391 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13467.492391 # average overall miss latency
+system.cpu1.icache.blocked_cycles::no_mshrs 2692 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 184 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.203488 # average number of cycles each access was blocked
+system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.630435 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44386 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 44386 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 44386 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 44386 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 44386 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 44386 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597612 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 597612 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 597612 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 597612 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 597612 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 597612 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7074093496 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 7074093496 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7074093496 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 7074093496 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7074093496 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 7074093496 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3068500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3068500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3068500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 3068500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071671 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.071671 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.071671 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11837.268154 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44654 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 44654 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 44654 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 44654 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 44654 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 44654 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 598534 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 598534 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 598534 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 598534 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 598534 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 598534 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7093435997 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 7093435997 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7093435997 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 7093435997 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7093435997 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 7093435997 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071270 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.071270 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.071270 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.350127 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 360159 # number of replacements
-system.cpu1.dcache.tagsinuse 474.597840 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 12677942 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 360527 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 35.165028 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 70354983000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data 474.597840 # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data 0.926949 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total 0.926949 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data 8310534 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 8310534 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 4138624 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 4138624 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97469 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 97469 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94858 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 94858 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 12449158 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 12449158 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 12449158 # number of overall hits
-system.cpu1.dcache.overall_hits::total 12449158 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 397542 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 397542 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1554744 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1554744 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13907 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 13907 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10598 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10598 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 1952286 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 1952286 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 1952286 # number of overall misses
-system.cpu1.dcache.overall_misses::total 1952286 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6044984000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 6044984000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61833185511 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 61833185511 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129279000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 129279000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53828000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 53828000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 67878169511 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 67878169511 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 67878169511 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 67878169511 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708076 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 8708076 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693368 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 5693368 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111376 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 111376 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105456 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 105456 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 14401444 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 14401444 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 14401444 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 14401444 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045652 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.045652 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273080 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.273080 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124865 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124865 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100497 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100497 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135562 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.135562 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135562 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.135562 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.900257 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.900257 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39770.653890 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 39770.653890 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9295.966060 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9295.966060 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.071523 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.071523 # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 34768.558250 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 34768.558250 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 26588 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 13412 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 3258 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.160835 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 82.790123 # average number of cycles each access was blocked
+system.cpu1.dcache.replacements 360685 # number of replacements
+system.cpu1.dcache.tagsinuse 474.635478 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 12674649 # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs 361036 # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs 35.106330 # Average number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 70356699000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.occ_blocks::cpu1.data 474.635478 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.927022 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.927022 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 8306809 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 8306809 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 4139176 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 4139176 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97757 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 97757 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94875 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 94875 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 12445985 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 12445985 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 12445985 # number of overall hits
+system.cpu1.dcache.overall_hits::total 12445985 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 399972 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 399972 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1557467 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1557467 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14022 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 14022 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10623 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 10623 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 1957439 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 1957439 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 1957439 # number of overall misses
+system.cpu1.dcache.overall_misses::total 1957439 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6115655000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 6115655000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61487432499 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 61487432499 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129927000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 129927000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53882500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 53882500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 67603087499 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 67603087499 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 67603087499 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 67603087499 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706781 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 8706781 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696643 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 5696643 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111779 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 111779 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105498 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 105498 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 14403424 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 14403424 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 14403424 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 14403424 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045938 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.045938 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273401 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.273401 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125444 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125444 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100694 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100694 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135901 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.135901 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135901 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.135901 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15290.207815 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9265.939238 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9265.939238 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.248894 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.248894 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 34536.497689 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 34536.497689 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 30853 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 12637 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 3329 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.267948 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 80.490446 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 324224 # number of writebacks
-system.cpu1.dcache.writebacks::total 324224 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169594 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 169594 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393339 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 1393339 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562933 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 1562933 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562933 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1562933 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227948 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 227948 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161405 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 161405 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12460 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12460 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10596 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 10596 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 389353 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 389353 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 389353 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 389353 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2844990000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2844990000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5144127207 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5144127207 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88536000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88536000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32636000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32636000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989117207 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 7989117207 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989117207 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 7989117207 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989822500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989822500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35094178017 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35094178017 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204084000517 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204084000517 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026177 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026177 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111873 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111873 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100478 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100478 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.027036 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.027036 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.872831 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12480.872831 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31870.928453 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31870.928453 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7105.617978 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7105.617978 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3080.030200 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3080.030200 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 324651 # number of writebacks
+system.cpu1.dcache.writebacks::total 324651 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171732 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 171732 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395801 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 1395801 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1444 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1444 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567533 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 1567533 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567533 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 1567533 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228240 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 228240 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161666 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 161666 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12578 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12578 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10618 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 10618 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 389906 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 389906 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 389906 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 389906 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2856522500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2856522500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131083207 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131083207 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89046000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89046000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32648500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32648500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7987605707 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 7987605707 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7987605707 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 7987605707 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35686741676 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35686741676 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026214 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028379 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028379 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112526 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112526 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100646 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.027070 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.027070 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.503896 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.503896 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.825768 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.825768 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 539953604456 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 539953604456 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 539953604456 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 539953604456 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 41721 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 48838 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu]
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:42:21
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 13 2013 11:38:19
+gem5 started Feb 13 2013 20:56:17
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2523204701000 because m5_exit instruction encountered
+Exiting @ tick 2533147650000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533245 # Number of seconds simulated
-sim_ticks 2533245380500 # Number of ticks simulated
-final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.533148 # Number of seconds simulated
+sim_ticks 2533147650000 # Number of ticks simulated
+final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67317 # Simulator instruction rate (inst/s)
-host_op_rate 86618 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2827634962 # Simulator tick rate (ticks/s)
-host_mem_usage 409784 # Number of bytes of host memory used
-host_seconds 895.89 # Real time elapsed on the host
-sim_insts 60308251 # Number of instructions simulated
-sim_ops 77599937 # Number of ops (including micro ops) simulated
+host_inst_rate 66149 # Simulator instruction rate (inst/s)
+host_op_rate 85115 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2778505291 # Simulator tick rate (ticks/s)
+host_mem_usage 406592 # Number of bytes of host memory used
+host_seconds 911.69 # Real time elapsed on the host
+sim_insts 60307315 # Number of instructions simulated
+sim_ops 77598799 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096850 # Total number of read requests seen
-system.physmem.writeReqs 813145 # Total number of write requests seen
-system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966198400 # Total number of bytes read from memory
-system.physmem.bytesWritten 52041280 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
+system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096808 # Total number of read requests seen
+system.physmem.writeReqs 813112 # Total number of write requests seen
+system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966195712 # Total number of bytes read from memory
+system.physmem.bytesWritten 52039168 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533244279000 # Total gap between requests
+system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2533146526000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154606 # Categorize read packet sizes
+system.physmem.readPktSize::6 154564 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2927056 # categorize write packet sizes
+system.physmem.writePktSize::2 2990994 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59127 # categorize write packet sizes
+system.physmem.writePktSize::6 59094 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482595000 # Total cycles spent in databus access
-system.physmem.totBankLat 16916941250 # Total cycles spent in bank access
-system.physmem.avgQLat 26034.38 # Average queueing delay per request
-system.physmem.avgBankLat 1120.59 # Average bank access latency per request
+system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests
+system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
+system.physmem.totBankLat 16909805000 # Total cycles spent in bank access
+system.physmem.avgQLat 26047.29 # Average queueing delay per request
+system.physmem.avgBankLat 1120.11 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32154.97 # Average memory access latency
-system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 32167.41 # Average memory access latency
+system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 12.52 # Average write queue length over time
-system.physmem.readRowHits 15020214 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793069 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 11.48 # Average write queue length over time
+system.physmem.readRowHits 15020221 # Number of row buffer hits during reads
+system.physmem.writeRowHits 793131 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
-system.physmem.avgGap 159223.45 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes
+system.physmem.avgGap 159218.06 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14667589 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits
+system.cpu.branchPred.lookups 14676489 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51389080 # DTB read hits
-system.cpu.dtb.read_misses 73326 # DTB read misses
-system.cpu.dtb.write_hits 11702658 # DTB write hits
-system.cpu.dtb.write_misses 17128 # DTB write misses
+system.cpu.dtb.read_hits 51394402 # DTB read hits
+system.cpu.dtb.read_misses 64202 # DTB read misses
+system.cpu.dtb.write_hits 11700782 # DTB write hits
+system.cpu.dtb.write_misses 15842 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51462406 # DTB read accesses
-system.cpu.dtb.write_accesses 11719786 # DTB write accesses
+system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51458604 # DTB read accesses
+system.cpu.dtb.write_accesses 11716624 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63091738 # DTB hits
-system.cpu.dtb.misses 90454 # DTB misses
-system.cpu.dtb.accesses 63182192 # DTB accesses
-system.cpu.itb.inst_hits 12277036 # ITB inst hits
-system.cpu.itb.inst_misses 11490 # ITB inst misses
+system.cpu.dtb.hits 63095184 # DTB hits
+system.cpu.dtb.misses 80044 # DTB misses
+system.cpu.dtb.accesses 63175228 # DTB accesses
+system.cpu.itb.inst_hits 12330326 # ITB inst hits
+system.cpu.itb.inst_misses 11351 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2578 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2478 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12288526 # ITB inst accesses
-system.cpu.itb.hits 12277036 # DTB hits
-system.cpu.itb.misses 11490 # DTB misses
-system.cpu.itb.accesses 12288526 # DTB accesses
-system.cpu.numCycles 472097236 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12341677 # ITB inst accesses
+system.cpu.itb.hits 12330326 # DTB hits
+system.cpu.itb.misses 11351 # DTB misses
+system.cpu.itb.accesses 12341677 # DTB accesses
+system.cpu.numCycles 471833351 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued
-system.cpu.iq.rate 0.263176 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued
+system.cpu.iq.rate 0.263486 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 220577 # number of nop insts executed
-system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11563754 # Number of branches executed
-system.cpu.iew.exec_stores 12214366 # Number of stores executed
-system.cpu.iew.exec_rate 0.257379 # Inst execution rate
-system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47207424 # num instructions producing a value
-system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value
+system.cpu.iew.exec_nop 220665 # number of nop insts executed
+system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11561887 # Number of branches executed
+system.cpu.iew.exec_stores 12212575 # Number of stores executed
+system.cpu.iew.exec_rate 0.257603 # Inst execution rate
+system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47219839 # num instructions producing a value
+system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 147889914 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.525723 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.514974 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458632 # Number of instructions committed
-system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60457696 # Number of instructions committed
+system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386920 # Number of memory references committed
-system.cpu.commit.loads 15654712 # Number of loads committed
-system.cpu.commit.membars 403607 # Number of memory barriers committed
-system.cpu.commit.branches 9961406 # Number of branches committed
+system.cpu.commit.refs 27386450 # Number of memory references committed
+system.cpu.commit.loads 15654440 # Number of loads committed
+system.cpu.commit.membars 403595 # Number of memory barriers committed
+system.cpu.commit.branches 9961299 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68855494 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991273 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68854449 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991256 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242460133 # The number of ROB reads
-system.cpu.rob.rob_writes 201635862 # The number of ROB writes
-system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60308251 # Number of Instructions Simulated
-system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated
-system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550197994 # number of integer regfile reads
-system.cpu.int_regfile_writes 88410647 # number of integer regfile writes
-system.cpu.fp_regfile_reads 8198 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2906 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831902 # number of misc regfile writes
-system.cpu.icache.replacements 980802 # number of replacements
-system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use
-system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.999174 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 11213050 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 11213050 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 11213050 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 11213050 # number of overall hits
-system.cpu.icache.overall_hits::total 11213050 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1060138 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1060138 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses
-system.cpu.icache.overall_misses::total 1060138 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14001105997 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14001105997 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14001105997 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14001105997 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14001105997 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14001105997 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 12273188 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 12273188 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 12273188 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 12273188 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 12273188 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086378 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.086378 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.086378 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.086378 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.086378 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.086378 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13206.871178 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13206.871178 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13206.871178 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 4 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 295 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 15.172881 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 4 # average number of cycles each access was blocked
+system.cpu.rob.rob_reads 242385214 # The number of ROB reads
+system.cpu.rob.rob_writes 202032533 # The number of ROB writes
+system.cpu.timesIdled 1770643 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 4594378908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 60307315 # Number of Instructions Simulated
+system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated
+system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.127815 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.127815 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 550300281 # number of integer regfile reads
+system.cpu.int_regfile_writes 88460223 # number of integer regfile writes
+system.cpu.fp_regfile_reads 8330 # number of floating regfile reads
+system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
+system.cpu.misc_regfile_reads 30137587 # number of misc regfile reads
+system.cpu.misc_regfile_writes 831885 # number of misc regfile writes
+system.cpu.icache.replacements 979919 # number of replacements
+system.cpu.icache.tagsinuse 511.615669 # Cycle average of tags in use
+system.cpu.icache.total_refs 11266751 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 980431 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 11.491631 # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 511.615669 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 11266751 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 11266751 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 11266751 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 11266751 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 11266751 # number of overall hits
+system.cpu.icache.overall_hits::total 11266751 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1059755 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1059755 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1059755 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1059755 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1059755 # number of overall misses
+system.cpu.icache.overall_misses::total 1059755 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 13997065496 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 13997065496 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 13997065496 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 13997065496 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 13997065496 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 13997065496 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 12326506 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 12326506 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 12326506 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 12326506 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 12326506 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 12326506 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085974 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.085974 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.085974 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.085974 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.085974 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.085974 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.831523 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13207.831523 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 4420 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
+system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 15.136986 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 78782 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 78782 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 78782 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 78782 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 78782 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 78782 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981356 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 981356 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 981356 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 981356 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 981356 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 981356 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11396806498 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 11396806498 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11396806498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11396806498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11396806498 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11396806498 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79294 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 79294 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 79294 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 79294 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 79294 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 79294 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980461 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 980461 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 980461 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 980461 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 980461 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 980461 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11381703997 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11381703997 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11381703997 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11381703997 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11381703997 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11381703997 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079959 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.079959 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079959 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.079959 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11613.325336 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11613.325336 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079541 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.079541 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079541 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.079541 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.522926 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.522926 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 64377 # number of replacements
-system.cpu.l2cache.tagsinuse 51361.576516 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1911659 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 129770 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 14.731132 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 2498200145000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 36918.334944 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 32.795639 # Average occupied blocks per requestor
+system.cpu.l2cache.replacements 64335 # number of replacements
+system.cpu.l2cache.tagsinuse 51343.588717 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1886166 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 129730 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 14.539166 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 2498200830000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 36928.997165 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 25.134248 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 8184.403113 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 6226.042472 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.563329 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000500 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 8156.882895 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 6232.574061 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.563492 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000384 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.124884 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.095002 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.783715 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 79915 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11190 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 967706 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 386775 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 1445586 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 607265 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 607265 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 44 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits
-system.cpu.l2cache.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 112880 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 112880 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 79915 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 11190 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 967706 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 499655 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1558466 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 79915 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 11190 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 967706 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 499655 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1558466 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses
+system.cpu.l2cache.occ_percent::cpu.inst 0.124464 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.095102 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.783441 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53181 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10674 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 967006 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 387028 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1417889 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 607515 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 607515 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 7 # number of SCUpgradeReq hits
+system.cpu.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 53181 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 10674 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 967006 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 499935 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1530796 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 53181 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 10674 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 967006 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 499935 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1530796 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 12360 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 2918 # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 12329 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 10702 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 23074 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 2920 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 2920 # number of UpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
+system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133200 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133200 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 12360 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 143917 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 156325 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses
+system.cpu.l2cache.demand_misses::cpu.inst 12329 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 143902 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 156274 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 12360 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 143917 # number of overall misses
-system.cpu.l2cache.overall_misses::total 156325 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3160000 # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::cpu.inst 12329 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 143902 # number of overall misses
+system.cpu.l2cache.overall_misses::total 156274 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2844500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 702880500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 627994499 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 1334152999 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 589500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 589500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6741992998 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6741992998 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3160000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 695710500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 632225999 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1330898999 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 476500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 476500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6732832500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6732832500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2844500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 702880500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 7369987497 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8076145997 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3160000 # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 695710500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7365058499 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 8063731499 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2844500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 702880500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 7369987497 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8076145997 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 79961 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11192 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 980066 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 397492 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 1468711 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 607265 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 607265 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 246080 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 246080 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 79961 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 11192 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 980066 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 643572 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1714791 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 79961 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 11192 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 980066 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 643572 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1714791 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000575 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000179 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012611 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026962 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.015745 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985145 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985145 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.105263 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.105263 # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541287 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.541287 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000575 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000179 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012611 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.223622 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.091163 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000575 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000179 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012611 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.223622 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.091163 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68695.652174 # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_latency::cpu.inst 695710500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7365058499 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 8063731499 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53222 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10676 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 979335 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 397730 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1440963 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 607515 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 607515 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2963 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 2963 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 10 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 246107 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 246107 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53222 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 10676 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 979335 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 643837 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1687070 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53222 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 10676 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 979335 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 643837 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1687070 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000770 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000187 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012589 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026908 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.016013 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985488 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985488 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.300000 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.300000 # miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541228 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.541228 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000770 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000187 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012589 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.223507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.092630 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000770 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000187 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012589 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.223507 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.092630 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 69378.048780 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56867.354369 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58597.975086 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 57693.102659 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 202.021933 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 202.021933 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50615.563048 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50615.563048 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68695.652174 # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 56428.785790 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59075.499813 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 57679.596039 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.184932 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.184932 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50546.790541 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50546.790541 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56867.354369 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51209.985596 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51662.536363 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68695.652174 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51599.955840 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 69378.048780 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56867.354369 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51209.985596 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51662.536363 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 56428.785790 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51181.071139 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51599.955840 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 59127 # number of writebacks
-system.cpu.l2cache.writebacks::total 59127 # number of writebacks
+system.cpu.l2cache.writebacks::writebacks 59094 # number of writebacks
+system.cpu.l2cache.writebacks::total 59094 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses
+system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12347 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 23051 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2918 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 2918 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12316 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10640 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 22999 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2920 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 2920 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133200 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133200 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 12347 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 143856 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 156251 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 12316 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 143840 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 156199 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 12347 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 143856 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 156251 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2584839 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 12316 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 143840 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 156199 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2335079 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93252 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 548548146 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 492444540 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043670777 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29186917 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29186917 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5081813058 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5081813058 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2584839 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 541798119 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 497025991 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1041252441 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29202920 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29202920 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5072736540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5072736540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2335079 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93252 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 548548146 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5574257598 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6125483835 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2584839 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 541798119 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5569762531 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6113988981 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2335079 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93252 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 548548146 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5574257598 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6125483835 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541798119 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5569762531 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6113988981 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079407 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167001894776 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167006974183 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26372604056 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26372604056 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002423276 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007502683 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26890048041 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26890048041 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079407 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193374498832 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193379578239 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026808 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015695 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985145 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985145 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.105263 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.105263 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541287 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541287 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223527 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.091120 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000575 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000179 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012598 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223527 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.091120 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193892471317 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193897550724 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026752 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015961 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985488 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985488 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.300000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.300000 # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541228 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541228 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.092586 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000770 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000187 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012576 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223411 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.092586 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46626 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44427.646068 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46212.888514 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45276.594378 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.370459 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.370459 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43991.402972 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46712.969079 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45273.813688 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38151.749685 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38151.749685 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38083.607658 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38083.607658 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56192.152174 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56953.146341 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46626 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44427.646068 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38748.871079 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39202.845646 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43991.402972 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38721.930833 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39142.305527 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 643060 # number of replacements
-system.cpu.dcache.tagsinuse 511.992813 # Cycle average of tags in use
-system.cpu.dcache.total_refs 21518829 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 643572 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 33.436553 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 42289000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.992813 # Average occupied blocks per requestor
+system.cpu.dcache.replacements 643325 # number of replacements
+system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use
+system.cpu.dcache.total_refs 21505081 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 643837 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 33.401437 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13762862 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13762862 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 7262343 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 7262343 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 242888 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 242888 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247601 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247601 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 21025205 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 21025205 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 21025205 # number of overall hits
-system.cpu.dcache.overall_hits::total 21025205 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 731521 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 731521 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2960125 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2960125 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 13538 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 13538 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 3691646 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3691646 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3691646 # number of overall misses
-system.cpu.dcache.overall_misses::total 3691646 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9676520000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9676520000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 104419203240 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 104419203240 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181802500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 181802500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 271000 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 271000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 114095723240 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 114095723240 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 114095723240 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 114095723240 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 14494383 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 14494383 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10222468 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10222468 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256426 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 256426 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247620 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247620 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 24716851 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 24716851 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 24716851 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 24716851 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050469 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.050469 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289570 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.289570 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052795 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052795 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000077 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000077 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13227.945609 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13227.945609 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35275.268186 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 35275.268186 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13429.051559 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13429.051559 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14263.157895 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 14263.157895 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 30906.463740 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 30906.463740 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 30906.463740 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 28001 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 14318 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2522 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.102696 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 57.733871 # average number of cycles each access was blocked
+system.cpu.dcache.ReadReq_hits::cpu.data 13751349 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13751349 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 7259815 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 7259815 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 243177 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 243177 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247604 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247604 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 21011164 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 21011164 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 21011164 # number of overall hits
+system.cpu.dcache.overall_hits::total 21011164 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 737485 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 737485 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 2962473 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2962473 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 13509 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 13509 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 10 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 3699958 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 3699958 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 3699958 # number of overall misses
+system.cpu.dcache.overall_misses::total 3699958 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 9781666500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 9781666500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 104377974730 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 104377974730 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180159500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 180159500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 166000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 166000 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 114159641230 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 114159641230 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 114159641230 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 114159641230 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 14488834 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 14488834 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10222288 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10222288 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256686 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 256686 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247614 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247614 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 24711122 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 24711122 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 24711122 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 24711122 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050900 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.050900 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289805 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.289805 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052629 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052629 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000040 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.149728 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.149728 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.149728 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.149728 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13263.546377 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13263.546377 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35233.392753 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 35233.392753 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13336.257310 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13336.257310 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16600 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16600 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 30854.307327 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 30854.307327 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 30854.307327 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 29793 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 16864 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 2613 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.401837 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 67.187251 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 607265 # number of writebacks
-system.cpu.dcache.writebacks::total 607265 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346124 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 346124 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2711175 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2711175 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1351 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 1351 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3057299 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3057299 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3057299 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3057299 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385397 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 385397 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248950 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 248950 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12187 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 634347 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 634347 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 634347 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 634347 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4799633500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4799633500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8191877422 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8191877422 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142320500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142320500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 233000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 233000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12991510922 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12991510922 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12991510922 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12991510922 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395110500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395110500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36212514849 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36212514849 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218607625349 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 218607625349 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026589 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026589 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047526 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047526 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000077 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.025665 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025665 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.025665 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12453.738612 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12453.738612 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32905.713685 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32905.713685 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11678.058587 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11678.058587 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 12263.157895 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 12263.157895 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20480.132990 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20480.132990 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 607515 # number of writebacks
+system.cpu.dcache.writebacks::total 607515 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351842 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 351842 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713489 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2713489 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1336 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1336 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3065331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3065331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3065331 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3065331 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385643 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385643 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248984 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+gem5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void DefaultFetch<Impl>::drainSanityCheck() const [with Impl = O3CPUImpl]: Assertion `!memReq[i]' failed.
+Program aborted at cycle 2395768530500
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.401347 # Number of seconds simulated
-sim_ticks 2401347058000 # Number of ticks simulated
-final_tick 2401347058000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 247220 # Simulator instruction rate (inst/s)
-host_op_rate 317493 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9839599535 # Simulator tick rate (ticks/s)
-host_mem_usage 400552 # Number of bytes of host memory used
-host_seconds 244.05 # Real time elapsed on the host
-sim_insts 60333921 # Number of instructions simulated
-sim_ops 77484019 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 501472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 7131280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 85632 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 677504 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 1269180 # Number of bytes read from this memory
-system.physmem.bytes_read::total 124661740 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 501472 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 85632 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 764064 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3746368 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1495356 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2.data 1321004 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6762184 # Number of bytes written to this memory
-system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 14038 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 111460 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1338 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 10586 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 19845 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14512426 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 58537 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 373839 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2.data 330251 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 812491 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47814443 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 208829 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 2969700 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35660 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 282135 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 73692 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 528528 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51913254 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 208829 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35660 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 73692 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 318181 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1560111 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 622715 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2.data 550110 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2815996 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1560111 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47814443 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 208829 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3592415 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35660 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 365195 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 73692 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1078638 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54729250 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 12617453 # Total number of read requests seen
-system.physmem.writeReqs 397526 # Total number of write requests seen
-system.physmem.cpureqs 54288 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 807516992 # Total number of bytes read from memory
-system.physmem.bytesWritten 25441664 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 102873020 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 2634764 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 789108 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 788757 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 788840 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 789165 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 789011 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 788682 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 788876 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 788949 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 788591 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 787997 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 788008 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 788277 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 788205 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 788031 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 788257 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 788698 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 24832 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 24781 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 25063 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 24852 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 25063 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 25253 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 25236 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 24651 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 24325 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 24263 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 24366 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 24934 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 24846 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 25132 # Track writes on a per bank basis
-system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 749984 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2400311882000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Categorize read packet sizes
-system.physmem.readPktSize::1 0 # Categorize read packet sizes
-system.physmem.readPktSize::2 15 # Categorize read packet sizes
-system.physmem.readPktSize::3 12582912 # Categorize read packet sizes
-system.physmem.readPktSize::4 0 # Categorize read packet sizes
-system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 34526 # Categorize read packet sizes
-system.physmem.readPktSize::7 0 # Categorize read packet sizes
-system.physmem.readPktSize::8 0 # Categorize read packet sizes
-system.physmem.writePktSize::0 0 # categorize write packet sizes
-system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 1130099 # categorize write packet sizes
-system.physmem.writePktSize::3 0 # categorize write packet sizes
-system.physmem.writePktSize::4 0 # categorize write packet sizes
-system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 17411 # categorize write packet sizes
-system.physmem.writePktSize::7 0 # categorize write packet sizes
-system.physmem.writePktSize::8 0 # categorize write packet sizes
-system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 2351 # categorize neither packet sizes
-system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 815640 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 791627 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 797680 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2998199 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2260925 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2261235 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2249585 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 49266 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 49185 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 91366 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 133537 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 91353 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 6968 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 6962 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 6960 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 6958 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3037 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3074 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3115 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3262 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3282 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3304 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3335 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3369 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3384 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 17292 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 17287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 17285 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 17280 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 17275 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 17269 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 17264 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 17259 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 17259 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17254 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17235 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 14298 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 14254 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 14208 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 14055 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 14034 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 14010 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 13970 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 13934 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 13913 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 277194471582 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 353012127832 # Sum of mem lat for all requests
-system.physmem.totBusLat 63087260000 # Total cycles spent in databus access
-system.physmem.totBankLat 12730396250 # Total cycles spent in bank access
-system.physmem.avgQLat 21969.13 # Average queueing delay per request
-system.physmem.avgBankLat 1008.95 # Average bank access latency per request
-system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 27978.08 # Average memory access latency
-system.physmem.avgRdBW 336.28 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 10.59 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 42.84 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 2.71 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.15 # Average read queue length over time
-system.physmem.avgWrQLen 0.39 # Average write queue length over time
-system.physmem.readRowHits 12562851 # Number of row buffer hits during reads
-system.physmem.writeRowHits 391169 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 98.40 # Row buffer hit rate for writes
-system.physmem.avgGap 184426.87 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 63262 # number of replacements
-system.l2c.tagsinuse 50352.279574 # Cycle average of tags in use
-system.l2c.total_refs 1759649 # Total number of references to valid blocks.
-system.l2c.sampled_refs 128652 # Sample count of references to valid blocks.
-system.l2c.avg_refs 13.677588 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2374416909500 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36834.025606 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5156.727312 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3775.205663 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 795.394812 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 755.555046 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.dtb.walker 5.900240 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst 1436.095715 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data 1592.381720 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.562043 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.078685 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.057605 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.012137 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.011529 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.dtb.walker 0.000090 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.inst 0.021913 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu2.data 0.024298 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.768315 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 8915 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 3218 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 460985 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 169797 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 2555 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 1118 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 134527 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 65561 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 28959 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 4314 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst 283968 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data 137931 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1301848 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 597795 # number of Writeback hits
-system.l2c.Writeback_hits::total 597795 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu2.data 4 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 61039 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 19134 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 33458 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 113631 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 8915 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 3218 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 460985 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 230836 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 2555 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 1118 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 134527 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 84695 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 28959 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 4314 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 283968 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 171389 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1415479 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 8915 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 3218 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 460985 # number of overall hits
-system.l2c.overall_hits::cpu0.data 230836 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 2555 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 1118 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 134527 # number of overall hits
-system.l2c.overall_hits::cpu1.data 84695 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 28959 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 4314 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 283968 # number of overall hits
-system.l2c.overall_hits::cpu2.data 171389 # number of overall hits
-system.l2c.overall_hits::total 1415479 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 7422 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6360 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 1338 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 1211 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 6 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst 2765 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data 2571 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 21677 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1420 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 501 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 985 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2906 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 105862 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 9648 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 17858 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 7422 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 112222 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1338 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 10859 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 6 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 2765 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 20429 # number of demand (read+write) misses
-system.l2c.demand_misses::total 155045 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 7422 # number of overall misses
-system.l2c.overall_misses::cpu0.data 112222 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 1338 # number of overall misses
-system.l2c.overall_misses::cpu1.data 10859 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 6 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 2765 # number of overall misses
-system.l2c.overall_misses::cpu2.data 20429 # number of overall misses
-system.l2c.overall_misses::total 155045 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 74977000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 69909500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 412500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst 180415500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.data 156598499 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 482381999 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 92000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 113500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 205500 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 432219000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 946210000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 1378429000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 74977000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 502128500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 412500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 180415500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 1102808499 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 1860810999 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 74977000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 502128500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 412500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 180415500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 1102808499 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 1860810999 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 8916 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 3220 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 468407 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 176157 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 2556 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 1118 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 135865 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 66772 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 28965 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 4314 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst 286733 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data 140502 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1323525 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 597795 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 597795 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1433 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 505 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 1000 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2938 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu2.data 5 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 166901 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 28782 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 51316 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246999 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 8916 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 3220 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 468407 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 343058 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 2556 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 1118 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 135865 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 95554 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 28965 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 4314 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 286733 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 191818 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1570524 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 8916 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 3220 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 468407 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 343058 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 2556 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 1118 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 135865 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 95554 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 28965 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 4314 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 286733 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 191818 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1570524 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000621 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015845 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.036104 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000391 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.009848 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.018136 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000207 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst 0.009643 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data 0.018299 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.016378 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990928 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992079 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.985000 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.989108 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.200000 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.634280 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.335210 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.348001 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.539954 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000621 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015845 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.327123 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000391 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.009848 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.113643 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000207 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.009643 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.106502 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.098722 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000621 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015845 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.327123 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000391 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.009848 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.113643 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000207 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.009643 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.106502 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.098722 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 56036.621824 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 57728.736581 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 68750 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst 65249.728752 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.data 60909.567872 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 22253.171518 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 183.632735 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 115.228426 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 70.715760 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44798.818408 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52985.216710 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 10335.530262 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 56036.621824 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 46240.768027 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 68750 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 65249.728752 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 53982.500318 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 12001.747873 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 56036.621824 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 46240.768027 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 68750 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 65249.728752 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 53982.500318 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 12001.747873 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 58537 # number of writebacks
-system.l2c.writebacks::total 58537 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 1338 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 1211 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 6 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.inst 2765 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.data 2563 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 7884 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 501 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 985 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 1486 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 9648 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 17858 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 27506 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 1338 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 10859 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 6 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 2765 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 20421 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 35390 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 1338 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 10859 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 6 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 2765 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 20421 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 35390 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56252 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 58196898 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54789148 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 337512 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 145949840 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.data 124327253 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 383656903 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5062472 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9850985 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 14913457 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 312092166 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 723390596 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1035482762 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 58196898 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 366881314 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 337512 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 145949840 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 847717849 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 1419139665 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56252 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 58196898 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 366881314 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 337512 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 145949840 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 847717849 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 1419139665 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25146563500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26567091024 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 51713654524 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647324364 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9537940251 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 10185264615 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25793887864 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36105031275 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 61898919139 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018136 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018242 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.005957 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992079 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985000 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.505786 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.200000 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.335210 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.348001 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.111361 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.113643 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.106460 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.022534 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000391 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009848 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.113643 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000207 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009643 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.106460 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.022534 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45242.896780 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48508.487320 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 48662.722349 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.734531 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.973755 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32347.861318 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40507.928995 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 37645.705010 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43495.439462 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33785.920803 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56252 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52784.752260 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41512.063513 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 40100.018791 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 8069329 # DTB read hits
-system.cpu0.dtb.read_misses 6237 # DTB read misses
-system.cpu0.dtb.write_hits 6635324 # DTB write hits
-system.cpu0.dtb.write_misses 2059 # DTB write misses
-system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 5724 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 124 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 8075566 # DTB read accesses
-system.cpu0.dtb.write_accesses 6637383 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 14704653 # DTB hits
-system.cpu0.dtb.misses 8296 # DTB misses
-system.cpu0.dtb.accesses 14712949 # DTB accesses
-system.cpu0.itb.inst_hits 32681523 # ITB inst hits
-system.cpu0.itb.inst_misses 3486 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 709 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2595 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 32685009 # ITB inst accesses
-system.cpu0.itb.hits 32681523 # DTB hits
-system.cpu0.itb.misses 3486 # DTB misses
-system.cpu0.itb.accesses 32685009 # DTB accesses
-system.cpu0.numCycles 114009309 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 32183346 # Number of instructions committed
-system.cpu0.committedOps 42389974 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 37541413 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 5201 # Number of float alu accesses
-system.cpu0.num_func_calls 1186772 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4235639 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 37541413 # number of integer instructions
-system.cpu0.num_fp_insts 5201 # number of float instructions
-system.cpu0.num_int_register_reads 191262498 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 39620034 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3719 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1484 # number of times the floating registers were written
-system.cpu0.num_mem_refs 15366811 # number of memory refs
-system.cpu0.num_load_insts 8436504 # Number of load instructions
-system.cpu0.num_store_insts 6930307 # Number of store instructions
-system.cpu0.num_idle_cycles 13418269361.007845 # Number of idle cycles
-system.cpu0.num_busy_cycles -13304260052.007845 # Number of busy cycles
-system.cpu0.not_idle_fraction -116.694507 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 117.694507 # Percentage of idle cycles
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed
-system.cpu0.icache.replacements 892035 # number of replacements
-system.cpu0.icache.tagsinuse 511.603883 # Cycle average of tags in use
-system.cpu0.icache.total_refs 44343596 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 892547 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 49.682085 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 8110895000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 479.105953 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 18.181823 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu2.inst 14.316107 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.935754 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst 0.035511 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu2.inst 0.027961 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999226 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 32215079 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 8406427 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 3722090 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 44343596 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 32215079 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 8406427 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 3722090 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 44343596 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 32215079 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 8406427 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 3722090 # number of overall hits
-system.cpu0.icache.overall_hits::total 44343596 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 469123 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 136142 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 311123 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 916388 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 469123 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 136142 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 311123 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 916388 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 469123 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 136142 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 311123 # number of overall misses
-system.cpu0.icache.overall_misses::total 916388 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1835025000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4152863490 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 5987888490 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 1835025000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 4152863490 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 5987888490 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 1835025000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 4152863490 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 5987888490 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 32684202 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 8542569 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 4033213 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 45259984 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 32684202 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 8542569 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 4033213 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 45259984 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 32684202 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 8542569 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 4033213 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 45259984 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014353 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015937 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.077140 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.020247 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014353 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015937 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.077140 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.020247 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014353 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015937 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.077140 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.020247 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13478.757474 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13347.979706 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 6534.228395 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13478.757474 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13347.979706 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 6534.228395 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13478.757474 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13347.979706 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 6534.228395 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3311 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 199 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.638191 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23827 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 23827 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu2.inst 23827 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 23827 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu2.inst 23827 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 23827 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136142 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287296 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 423438 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 136142 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 287296 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 423438 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 136142 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 287296 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 423438 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1562741000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3387046990 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 4949787990 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1562741000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3387046990 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 4949787990 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1562741000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3387046990 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 4949787990 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009356 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.009356 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015937 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.071233 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.009356 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11689.522409 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11689.522409 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11478.757474 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11789.398356 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11689.522409 # average overall mshr miss latency
-system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 629918 # number of replacements
-system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 23229670 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 630430 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 36.847342 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 495.731477 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu1.data 9.808064 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu2.data 6.457575 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.968226 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu1.data 0.019156 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu2.data 0.012612 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 6949961 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 1913340 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4445734 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 13309035 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 5955328 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 1354459 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 2121705 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 9431492 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 130986 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34187 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73575 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 238748 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137363 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35914 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74119 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 247396 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 12905289 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 3267799 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 6567439 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 22740527 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 12905289 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 3267799 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 6567439 # number of overall hits
-system.cpu0.dcache.overall_hits::total 22740527 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 169780 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 65045 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 280934 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 515759 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 168334 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 29287 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 587324 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 784945 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6377 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1727 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3901 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 12005 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu2.data 5 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 338114 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 94332 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 868258 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1300704 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 338114 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 94332 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 868258 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1300704 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907672500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4047585000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 4955257500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 722890500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17770037899 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 18492928399 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22607500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52022500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 74630000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 77000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 77000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 1630563000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 21817622899 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 23448185899 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 1630563000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 21817622899 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 23448185899 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7119741 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 1978385 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 4726668 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 13824794 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 6123662 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 1383746 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 2709029 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 10216437 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137363 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35914 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77476 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 250753 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137363 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35914 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74124 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 13243403 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 3362131 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 7435697 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 24041231 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 13243403 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 3362131 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 7435697 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 24041231 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023846 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032878 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059436 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.037307 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027489 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021165 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.216802 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.076832 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046424 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048087 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050351 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047876 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000067 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025531 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028057 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.116769 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.054103 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025531 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028057 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.116769 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.054103 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13954.531478 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14407.601074 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 9607.699526 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24682.982211 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30255.936926 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23559.521239 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.619572 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13335.683158 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6216.576426 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15400 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 18027.303598 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17285.364457 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25128.041318 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 18027.303598 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 9913 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 3463 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 1094 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 45 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.061243 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 76.955556 # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 597795 # number of writebacks
-system.cpu0.dcache.writebacks::total 597795 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 143860 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 143860 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 535045 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 535045 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 436 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 436 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 678905 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 678905 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 678905 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 678905 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65045 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137074 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 202119 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29287 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52279 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 81566 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1727 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3465 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5192 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 5 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 94332 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 189353 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 283685 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 94332 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 189353 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 283685 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 777582500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1781362000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2558944500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 664316500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1392170991 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2056487491 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19153500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40164500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59318000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 67000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 67000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1441899000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3173532991 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 4615431991 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1441899000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3173532991 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 4615431991 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27472084500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29005064000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56477148500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280597500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13851108534 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15131706034 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28752682000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42856172534 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71608854534 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032878 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029000 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014620 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021165 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019298 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007984 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048087 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044724 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020706 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000067 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028057 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025465 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11954.531478 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12995.622802 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12660.583617 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22682.982211 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26629.640793 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25212.557818 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.619572 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11591.486291 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11424.884438 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13400 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15285.364457 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16759.877007 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16269.566565 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dtb.inst_hits 0 # ITB inst hits
-system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 2193182 # DTB read hits
-system.cpu1.dtb.read_misses 2113 # DTB read misses
-system.cpu1.dtb.write_hits 1470431 # DTB write hits
-system.cpu1.dtb.write_misses 386 # DTB write misses
-system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1737 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 73 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 2195295 # DTB read accesses
-system.cpu1.dtb.write_accesses 1470817 # DTB write accesses
-system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 3663613 # DTB hits
-system.cpu1.dtb.misses 2499 # DTB misses
-system.cpu1.dtb.accesses 3666112 # DTB accesses
-system.cpu1.itb.inst_hits 8542569 # ITB inst hits
-system.cpu1.itb.inst_misses 1142 # ITB inst misses
-system.cpu1.itb.read_hits 0 # DTB read hits
-system.cpu1.itb.read_misses 0 # DTB read misses
-system.cpu1.itb.write_hits 0 # DTB write hits
-system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 231 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 843 # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses 0 # DTB read accesses
-system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 8543711 # ITB inst accesses
-system.cpu1.itb.hits 8542569 # DTB hits
-system.cpu1.itb.misses 1142 # DTB misses
-system.cpu1.itb.accesses 8543711 # DTB accesses
-system.cpu1.numCycles 574622770 # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 8323313 # Number of instructions committed
-system.cpu1.committedOps 10568521 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 9455667 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses
-system.cpu1.num_func_calls 319891 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1162179 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 9455667 # number of integer instructions
-system.cpu1.num_fp_insts 2078 # number of float instructions
-system.cpu1.num_int_register_reads 54536858 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 10267786 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written
-system.cpu1.num_mem_refs 3838385 # number of memory refs
-system.cpu1.num_load_insts 2289184 # Number of load instructions
-system.cpu1.num_store_insts 1549201 # Number of store instructions
-system.cpu1.num_idle_cycles 539990839.742371 # Number of idle cycles
-system.cpu1.num_busy_cycles 34631930.257629 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.060269 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.939731 # Percentage of idle cycles
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 4693263 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 3812182 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 221977 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3118720 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2512857 # Number of BTB hits
-system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 80.573344 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 412180 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 21663 # Number of incorrect RAS predictions.
-system.cpu2.dtb.inst_hits 0 # ITB inst hits
-system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 10844301 # DTB read hits
-system.cpu2.dtb.read_misses 26001 # DTB read misses
-system.cpu2.dtb.write_hits 3253591 # DTB write hits
-system.cpu2.dtb.write_misses 6154 # DTB write misses
-system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 3046 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 667 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch
-system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 434 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 10870302 # DTB read accesses
-system.cpu2.dtb.write_accesses 3259745 # DTB write accesses
-system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 14097892 # DTB hits
-system.cpu2.dtb.misses 32155 # DTB misses
-system.cpu2.dtb.accesses 14130047 # DTB accesses
-system.cpu2.itb.inst_hits 4034633 # ITB inst hits
-system.cpu2.itb.inst_misses 4571 # ITB inst misses
-system.cpu2.itb.read_hits 0 # DTB read hits
-system.cpu2.itb.read_misses 0 # DTB read misses
-system.cpu2.itb.write_hits 0 # DTB write hits
-system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 499 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1620 # Number of entries that have been flushed from TLB
-system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 986 # Number of TLB faults due to permissions restrictions
-system.cpu2.itb.read_accesses 0 # DTB read accesses
-system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 4039204 # ITB inst accesses
-system.cpu2.itb.hits 4034633 # DTB hits
-system.cpu2.itb.misses 4571 # DTB misses
-system.cpu2.itb.accesses 4039204 # DTB accesses
-system.cpu2.numCycles 88320298 # number of cpu cycles simulated
-system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 9410725 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 32093241 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 4693263 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 2925037 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 6776745 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 1793565 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 51693 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.BlockedCycles 19502883 # Number of cycles fetch has spent blocked
-system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 35787 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 57273 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 283 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 4033217 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 303741 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2092 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 37067906 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.039760 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.425875 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 30296325 81.73% 81.73% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 382563 1.03% 82.76% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 507321 1.37% 84.13% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 805393 2.17% 86.31% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 652342 1.76% 88.07% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 346651 0.94% 89.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 996850 2.69% 91.69% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 239087 0.64% 92.33% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 2841374 7.67% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 37067906 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.053139 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.363373 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 10025306 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 19435128 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 6133360 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 293839 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1179201 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 610191 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 53369 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 36416807 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 180085 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 1179201 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 10595473 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 6672537 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 11193536 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 5837719 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 1588398 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 34213134 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2954 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 427229 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents 898663 # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.FullRegisterEvents 11044 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 36672264 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 156364458 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 156337893 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 26565 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 25643428 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 11028835 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 232388 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 208734 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 3368643 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 6480999 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 3820565 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 539245 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 769553 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 31495381 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 514788 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 34101978 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 55239 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7293710 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 19517466 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 157489 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 37067906 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.919987 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.574944 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 24513061 66.13% 66.13% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 3940276 10.63% 76.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 2351629 6.34% 83.10% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 1969211 5.31% 88.42% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 2763009 7.45% 95.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 888704 2.40% 98.27% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 473497 1.28% 99.55% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 133879 0.36% 99.91% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 34640 0.09% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 37067906 # Number of insts issued each cycle
-system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 16450 1.07% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 1406460 91.72% 92.80% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 110474 7.20% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.FU_type_0::No_OpClass 61347 0.18% 0.18% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 19254237 56.46% 56.64% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 25603 0.08% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 363 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.72% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 11339596 33.25% 89.97% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 3420808 10.03% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 34101978 # Type of FU issued
-system.cpu2.iq.rate 0.386117 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 1533384 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.044965 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 106886012 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 39309169 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 27255453 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 6518 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 3637 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 3015 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 35570601 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 3414 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 207005 # Number of loads that had data forwarded from stores
-system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1561439 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 1810 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 9237 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 573725 # Number of stores squashed
-system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 5369512 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 345439 # Number of times an access to memory failed due to the cache being blocked
-system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1179201 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 4914537 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 93208 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 32084127 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 61095 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 6480999 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 3820565 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 371831 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 32634 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 9237 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 106581 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 88238 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 194819 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 33130261 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 11055368 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 971717 # Number of squashed instructions skipped in execute
-system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 73958 # number of nop insts executed
-system.cpu2.iew.exec_refs 14443007 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 3675866 # Number of branches executed
-system.cpu2.iew.exec_stores 3387639 # Number of stores executed
-system.cpu2.iew.exec_rate 0.375115 # Inst execution rate
-system.cpu2.iew.wb_sent 32719575 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 27258468 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 15578435 # num instructions producing a value
-system.cpu2.iew.wb_consumers 28336805 # num instructions consuming a value
-system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.308632 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.549760 # average fanout of values written-back
-system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 7236388 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 357299 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 169355 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 35888560 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.684756 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.712853 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 27290790 76.04% 76.04% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 4165435 11.61% 87.65% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 1253109 3.49% 91.14% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 644489 1.80% 92.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 571851 1.59% 94.53% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 314297 0.88% 95.41% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 396110 1.10% 96.51% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 285595 0.80% 97.31% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 966884 2.69% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 35888560 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 19876644 # Number of instructions committed
-system.cpu2.commit.committedOps 24574906 # Number of ops (including micro ops) committed
-system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 8166400 # Number of memory references committed
-system.cpu2.commit.loads 4919560 # Number of loads committed
-system.cpu2.commit.membars 94646 # Number of memory barriers committed
-system.cpu2.commit.branches 3146883 # Number of branches committed
-system.cpu2.commit.fp_insts 2975 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 21821277 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 294032 # Number of function calls committed.
-system.cpu2.commit.bw_lim_events 966884 # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 66205278 # The number of ROB reads
-system.cpu2.rob.rob_writes 64842405 # The number of ROB writes
-system.cpu2.timesIdled 359398 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 51252392 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles 3567238209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 19827262 # Number of Instructions Simulated
-system.cpu2.committedOps 24525524 # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total 19827262 # Number of Instructions Simulated
-system.cpu2.cpi 4.454488 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 4.454488 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.224493 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.224493 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 153057849 # number of integer regfile reads
-system.cpu2.int_regfile_writes 29069811 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 22288 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 20782 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 9001591 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 241415 # number of misc regfile writes
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs nan # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981127238281 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 981127238281 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981127238281 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 981127238281 # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.kern.inst.arm 0 # number of arm instructions executed
-system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-
----------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/projects/pd/randd/dist/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=true
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
pio=system.iobus.master[24]
[system.realview.gic]
-type=Gic
+type=Pl390
clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
---------- Begin Simulation Statistics ----------
-sim_seconds 2.542409 # Number of seconds simulated
-sim_ticks 2542409356000 # Number of ticks simulated
-final_tick 2542409356000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.542296 # Number of seconds simulated
+sim_ticks 2542295570500 # Number of ticks simulated
+final_tick 2542295570500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 77322 # Simulator instruction rate (inst/s)
-host_op_rate 99492 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3259551931 # Simulator tick rate (ticks/s)
-host_mem_usage 413868 # Number of bytes of host memory used
-host_seconds 779.99 # Real time elapsed on the host
-sim_insts 60310148 # Number of instructions simulated
-sim_ops 77602492 # Number of ops (including micro ops) simulated
+host_inst_rate 70655 # Simulator instruction rate (inst/s)
+host_op_rate 90914 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2978397497 # Simulator tick rate (ticks/s)
+host_mem_usage 409668 # Number of bytes of host memory used
+host_seconds 853.58 # Real time elapsed on the host
+sim_insts 60309877 # Number of instructions simulated
+sim_ops 77602149 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 1280 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 506624 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4283408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 292928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4810268 # Number of bytes read from this memory
-system.physmem.bytes_read::total 131006892 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 506624 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 292928 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 504448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4169680 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 296128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4925148 # Number of bytes read from this memory
+system.physmem.bytes_read::total 131008300 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 504448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 296128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3787072 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 1340604 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 1675508 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 1346312 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 1669800 # Number of bytes written to this memory
system.physmem.bytes_written::total 6803184 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 20 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 7916 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 66962 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 4577 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 75167 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15293487 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 7882 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 65185 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 4627 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 76962 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15293509 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59173 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 335151 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 418877 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 336578 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 417450 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813201 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47636124 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 629 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.clcd 47638256 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 503 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 199269 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1684783 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 529 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 115217 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1892012 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51528638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 199269 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 115217 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314486 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1489560 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 527297 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 659024 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2675881 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1489560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47636124 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 629 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 198422 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1640124 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 378 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 116481 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1937284 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51531498 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 198422 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 116481 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314903 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1489627 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 529565 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 656808 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2676000 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1489627 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47638256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 199269 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 2212080 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 529 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 115217 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2551035 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 54204519 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15293487 # Total number of read requests seen
+system.physmem.bw_total::cpu0.inst 198422 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 2169689 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 116481 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 2594092 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 54207499 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15293509 # Total number of read requests seen
system.physmem.writeReqs 813201 # Total number of write requests seen
-system.physmem.cpureqs 218488 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 978783168 # Total number of bytes read from memory
+system.physmem.cpureqs 218507 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 978784576 # Total number of bytes read from memory
system.physmem.bytesWritten 52044864 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 131006892 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 131008300 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6803184 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 956241 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 955734 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 955678 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 956495 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 955436 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 955557 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 956091 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 955615 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 955522 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 955928 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 956030 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 955423 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 955313 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis
+system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 956235 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 955673 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 956489 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 955564 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 956162 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 956093 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 955524 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 955433 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 955984 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50833 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50906 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50278 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50911 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50805 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51195 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50723 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50636 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51230 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50911 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50281 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50906 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50808 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51188 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51253 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50731 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50630 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1790732 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2542408198000 # Total gap between requests
+system.physmem.numWrRetry 1856479 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2542294418500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 43 # Categorize read packet sizes
system.physmem.readPktSize::3 15138816 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154628 # Categorize read packet sizes
+system.physmem.readPktSize::6 154650 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2544760 # categorize write packet sizes
+system.physmem.writePktSize::2 2610507 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4687 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1054866 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 991514 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 961470 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3604976 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2718322 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2722144 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2700252 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60049 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 59439 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 110004 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 160498 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 109966 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 10070 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 9996 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 10911 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 8954 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1054657 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 991834 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 961504 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3604952 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2718225 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2722186 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2700242 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 60067 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 59423 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 110017 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 160496 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 109935 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 10065 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 9993 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 11014 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 8845 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2915 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3085 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 3203 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3548 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3592 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3632 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3698 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3757 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3785 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35352 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35340 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35326 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2748 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2841 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2925 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2930 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2931 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2924 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2916 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35371 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35343 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35318 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35280 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35232 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35230 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32596 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32404 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32279 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 31921 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 31858 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 31803 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 31723 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31647 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31605 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32649 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32606 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32532 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32517 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32508 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32491 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32485 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 346733530557 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 439908911807 # Sum of mem lat for all requests
-system.physmem.totBusLat 76467385000 # Total cycles spent in databus access
-system.physmem.totBankLat 16707996250 # Total cycles spent in bank access
-system.physmem.avgQLat 22671.99 # Average queueing delay per request
-system.physmem.avgBankLat 1092.49 # Average bank access latency per request
+system.physmem.totQLat 346840685210 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 440008538960 # Sum of mem lat for all requests
+system.physmem.totBusLat 76467475000 # Total cycles spent in databus access
+system.physmem.totBankLat 16700378750 # Total cycles spent in bank access
+system.physmem.avgQLat 22678.97 # Average queueing delay per request
+system.physmem.avgBankLat 1091.99 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 28764.48 # Average memory access latency
-system.physmem.avgRdBW 384.98 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 28770.96 # Average memory access latency
+system.physmem.avgRdBW 385.00 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.47 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.53 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.17 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.17 # Average read queue length over time
-system.physmem.avgWrQLen 1.11 # Average write queue length over time
-system.physmem.readRowHits 15218342 # Number of row buffer hits during reads
-system.physmem.writeRowHits 794645 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 1.14 # Average write queue length over time
+system.physmem.readRowHits 15218397 # Number of row buffer hits during reads
+system.physmem.writeRowHits 794710 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.72 # Row buffer hit rate for writes
-system.physmem.avgGap 157847.98 # Average gap between requests
+system.physmem.writeRowHitRate 97.73 # Row buffer hit rate for writes
+system.physmem.avgGap 157840.70 # Average gap between requests
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 64396 # number of replacements
-system.l2c.tagsinuse 51411.059605 # Cycle average of tags in use
-system.l2c.total_refs 1936288 # Total number of references to valid blocks.
-system.l2c.sampled_refs 129787 # Sample count of references to valid blocks.
-system.l2c.avg_refs 14.918967 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 2506346605000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 36969.089517 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.dtb.walker 15.370678 # Average occupied blocks per requestor
+system.l2c.replacements 64418 # number of replacements
+system.l2c.tagsinuse 51401.261729 # Cycle average of tags in use
+system.l2c.total_refs 1905310 # Total number of references to valid blocks.
+system.l2c.sampled_refs 129810 # Sample count of references to valid blocks.
+system.l2c.avg_refs 14.677683 # Average number of references to valid blocks.
+system.l2c.warmup_cycle 2531415043500 # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::writebacks 36947.323889 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker 9.916328 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 5186.086135 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 3274.725116 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.dtb.walker 19.219664 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.itb.walker 0.104011 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst 3007.163435 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data 2939.300701 # Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.564104 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.dtb.walker 0.000235 # Average percentage of cache occupancy
+system.l2c.occ_blocks::cpu0.inst 5145.662568 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 3278.560293 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker 13.240870 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 3059.988680 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 2946.568751 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.563771 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker 0.000151 # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst 0.079133 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.data 0.049968 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.dtb.walker 0.000293 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.itb.walker 0.000002 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst 0.045886 # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.data 0.044850 # Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.784471 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.dtb.walker 48837 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 7271 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 488824 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 211032 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 48027 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 7206 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 482673 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 176185 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1470055 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 607854 # number of Writeback hits
-system.l2c.Writeback_hits::total 607854 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
+system.l2c.occ_percent::cpu0.inst 0.078517 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.050027 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker 0.000202 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.046692 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.044961 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.784321 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker 32362 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 7566 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst 491236 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 213718 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 30461 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 6864 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 480165 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 173950 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1436322 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 608473 # number of Writeback hits
+system.l2c.Writeback_hits::total 608473 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 19 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 56342 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 56524 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 112866 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 48837 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 7271 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 488824 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 267374 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 48027 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 7206 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 482673 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 232709 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1582921 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 48837 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 7271 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 488824 # number of overall hits
-system.l2c.overall_hits::cpu0.data 267374 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 48027 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 7206 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 482673 # number of overall hits
-system.l2c.overall_hits::cpu1.data 232709 # number of overall hits
-system.l2c.overall_hits::total 1582921 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses
+system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 57779 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 55086 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 112865 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 32362 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 7566 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 491236 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 271497 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 30461 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 6864 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 480165 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 229036 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1549187 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 32362 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 7566 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 491236 # number of overall hits
+system.l2c.overall_hits::cpu0.data 271497 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 30461 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 6864 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 480165 # number of overall hits
+system.l2c.overall_hits::cpu1.data 229036 # number of overall hits
+system.l2c.overall_hits::total 1549187 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 20 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 7806 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 6093 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 4582 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 4589 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 23119 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1580 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1330 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 61797 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 71443 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 133240 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu0.inst 7773 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 6102 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 4633 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 4618 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 23163 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 1544 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 1370 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2914 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 60061 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 73152 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 133213 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 20 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 7806 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 67890 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 4582 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 76032 # number of demand (read+write) misses
-system.l2c.demand_misses::total 156359 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses
+system.l2c.demand_misses::cpu0.inst 7773 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 66163 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 4633 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 77770 # number of demand (read+write) misses
+system.l2c.demand_misses::total 156376 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 20 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 7806 # number of overall misses
-system.l2c.overall_misses::cpu0.data 67890 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 4582 # number of overall misses
-system.l2c.overall_misses::cpu1.data 76032 # number of overall misses
-system.l2c.overall_misses::total 156359 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1700500 # number of ReadReq miss cycles
+system.l2c.overall_misses::cpu0.inst 7773 # number of overall misses
+system.l2c.overall_misses::cpu0.data 66163 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 4633 # number of overall misses
+system.l2c.overall_misses::cpu1.data 77770 # number of overall misses
+system.l2c.overall_misses::total 156376 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1354500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu0.itb.walker 118000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 431133000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 345731497 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1924500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst 269379000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.data 269289000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1319343997 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 205000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 274000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 479000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 3242523998 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 3517580500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 6760104498 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.dtb.walker 1700500 # number of demand (read+write) miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 429697500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 347820500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 983000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst 271281500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data 271043000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1322298000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 251500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 204000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 455500 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 3137999000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 3639162500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 6777161500 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker 1354500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 118000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 431133000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 3588255495 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 1924500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 269379000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 3786869500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 8079448495 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.dtb.walker 1700500 # number of overall miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 429697500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 3485819500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 983000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 271281500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 3910205500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 8099459500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker 1354500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 118000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 431133000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 3588255495 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 1924500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 269379000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 3786869500 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 8079448495 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 48862 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 7273 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.inst 496630 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 217125 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 48048 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 7207 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 487255 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 180774 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1493174 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 607854 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 607854 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1597 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 1346 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 5 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 8 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 118139 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 127967 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246106 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 48862 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 7273 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 496630 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 335264 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 48048 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 7207 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 487255 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 308741 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1739280 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 48862 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 7273 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 496630 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 335264 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 48048 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 7207 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 487255 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 308741 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1739280 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000512 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000275 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.015718 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.028062 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000437 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000139 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.009404 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.025385 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.015483 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989355 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988113 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.988787 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.523087 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.558292 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.541393 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000512 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000275 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.015718 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.202497 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000437 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.000139 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.009404 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.246265 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.089899 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000512 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000275 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.015718 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.202497 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000437 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.000139 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.009404 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.246265 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.089899 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 68020 # average ReadReq miss latency
+system.l2c.overall_miss_latency::cpu0.inst 429697500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 3485819500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 983000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 271281500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 3910205500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 8099459500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 32382 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 7568 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 499009 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 219820 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 30476 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 6864 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 484798 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 178568 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1459485 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 608473 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 608473 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1563 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 1384 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2947 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 4 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 117840 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 128238 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 246078 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 32382 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 7568 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 499009 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 337660 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 30476 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 6864 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 484798 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 306806 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 1705563 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 32382 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 7568 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 499009 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 337660 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 30476 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 6864 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 484798 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 306806 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 1705563 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000618 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000264 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.015577 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.027759 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000492 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.009557 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.025861 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.015871 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.987844 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989884 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.988802 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.509683 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.570439 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.541345 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000618 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000264 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.015577 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.195946 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000492 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.009557 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.253483 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.091686 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000618 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000264 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.015577 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.195946 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000492 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.009557 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.253483 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.091686 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 67725 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 59000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55230.976172 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 56742.408830 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 91642.857143 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58790.702750 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.data 58681.412072 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 57067.520092 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 129.746835 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 206.015038 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 164.604811 # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52470.572973 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49236.181291 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 50736.299144 # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 68020 # average overall miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55280.779622 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 57001.065225 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 65533.333333 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 58554.176559 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 58692.724123 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 57086.646807 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 162.888601 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 148.905109 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 156.314345 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52246.865687 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 49747.956310 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 50874.625600 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 67725 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 55230.976172 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 52853.962218 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91642.857143 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 58790.702750 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 49806.259207 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 51672.423685 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 68020 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 55280.779622 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52685.330169 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 65533.333333 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 58554.176559 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 50279.098624 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 51794.773495 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 67725 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 59000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 55230.976172 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 52853.962218 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91642.857143 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 58790.702750 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 49806.259207 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 51672.423685 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 55280.779622 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52685.330169 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 65533.333333 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 58554.176559 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 50279.098624 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 51794.773495 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 59173 # number of writebacks
system.l2c.writebacks::total 59173 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.inst 10 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1.data 20 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
+system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst 10 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data 39 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
+system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst 10 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data 39 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 20 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.inst 7797 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu0.data 6054 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.inst 4577 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.data 4569 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 23046 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu0.data 1580 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 1330 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu0.data 61797 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 71443 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 133240 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst 7763 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data 6063 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst 4627 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data 4598 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 23088 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data 1544 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 1370 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 2914 # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data 60061 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 73152 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 133213 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker 20 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst 7797 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu0.data 67851 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 4577 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 76012 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 156286 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst 7763 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data 66124 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 4627 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 77750 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 156301 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker 20 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst 7797 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu0.data 67851 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 4577 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 76012 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 156286 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1388048 # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::cpu0.inst 7763 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data 66124 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 4627 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 77750 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 156301 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 1106788 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 93252 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 333715736 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 268789023 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1661538 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56252 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 212136240 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 211485699 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1029325788 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15908517 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13301330 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 29209847 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2471692908 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2627616827 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 5099309735 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1388048 # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 332555399 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data 270417799 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 796028 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 213310327 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data 212900467 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 1031180060 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 15532986 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13701370 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 29234356 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2388927373 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2728057055 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5116984428 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1106788 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 93252 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 333715736 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 2740481931 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1661538 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56252 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 212136240 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 2839102526 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 6128635523 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1388048 # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst 332555399 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data 2659345172 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 796028 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 213310327 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 2940957522 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 6148164488 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1106788 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 93252 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 333715736 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 2740481931 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1661538 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56252 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 212136240 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 2839102526 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 6128635523 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst 332555399 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data 2659345172 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 796028 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 213310327 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 2940957522 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 6148164488 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5050907 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84092703276 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82869988008 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 166967742191 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10187478145 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 12920441542 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 23107919687 # number of WriteReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 84173719776 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 82789281508 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 166968052191 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 10449638570 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 13171042406 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 23620680976 # number of WriteReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76254 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76254 # number of LoadLockedReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5050907 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94280181421 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95790429550 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 190075661878 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027883 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025275 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.015434 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989355 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988113 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.988787 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.523087 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.558292 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.541393 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.089857 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000512 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000275 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015700 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.202381 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000437 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000139 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009393 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.246200 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.089857 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average ReadReq mshr miss latency
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94623358346 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 95960323914 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 190588733167 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027582 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025749 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.015819 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987844 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989884 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.988802 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.509683 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.570439 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.541345 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.091642 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000618 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000264 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015557 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.195830 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000492 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009544 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.253417 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.091642 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44398.583251 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46287.086671 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.967196 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10068.681646 # average UpgradeReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44601.319314 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46302.841888 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 44663.031012 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10060.224093 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10037.748110 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39996.972474 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 36779.206178 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 38271.613142 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10032.380233 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39775.018281 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37292.993425 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 38412.050085 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55521.920000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55339.400000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42800.530460 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40389.705841 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79120.857143 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56252 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46348.315490 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37350.714703 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 39214.232388 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42838.515909 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40217.548424 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 53068.533333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46101.216123 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37825.820219 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39335.413644 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 7548901 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 6013590 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 377467 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 4898170 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 4008296 # Number of BTB hits
+system.cpu0.branchPred.lookups 7620138 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 6076880 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 380507 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4965064 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 4053585 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 81.832521 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 726547 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 38944 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 81.642150 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 731859 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 39538 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 25977003 # DTB read hits
-system.cpu0.dtb.read_misses 44168 # DTB read misses
-system.cpu0.dtb.write_hits 5905544 # DTB write hits
-system.cpu0.dtb.write_misses 10435 # DTB write misses
+system.cpu0.dtb.read_hits 26058653 # DTB read hits
+system.cpu0.dtb.read_misses 40101 # DTB read misses
+system.cpu0.dtb.write_hits 5895373 # DTB write hits
+system.cpu0.dtb.write_misses 9447 # DTB write misses
system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 8487 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1476 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 5619 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 273 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 629 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 26021171 # DTB read accesses
-system.cpu0.dtb.write_accesses 5915979 # DTB write accesses
+system.cpu0.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 26098754 # DTB read accesses
+system.cpu0.dtb.write_accesses 5904820 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31882547 # DTB hits
-system.cpu0.dtb.misses 54603 # DTB misses
-system.cpu0.dtb.accesses 31937150 # DTB accesses
-system.cpu0.itb.inst_hits 6053570 # ITB inst hits
-system.cpu0.itb.inst_misses 7437 # ITB inst misses
+system.cpu0.dtb.hits 31954026 # DTB hits
+system.cpu0.dtb.misses 49548 # DTB misses
+system.cpu0.dtb.accesses 32003574 # DTB accesses
+system.cpu0.itb.inst_hits 6112115 # ITB inst hits
+system.cpu0.itb.inst_misses 7637 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 753 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2703 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1579 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 6061007 # ITB inst accesses
-system.cpu0.itb.hits 6053570 # DTB hits
-system.cpu0.itb.misses 7437 # DTB misses
-system.cpu0.itb.accesses 6061007 # DTB accesses
-system.cpu0.numCycles 238938486 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 6119752 # ITB inst accesses
+system.cpu0.itb.hits 6112115 # DTB hits
+system.cpu0.itb.misses 7637 # DTB misses
+system.cpu0.itb.accesses 6119752 # DTB accesses
+system.cpu0.numCycles 239063312 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 15394391 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 47363199 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 7548901 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 4734843 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 10514679 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2521350 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 88217 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.BlockedCycles 49746520 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 1647 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 1973 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 54986 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 100350 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 6051440 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 388609 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3416 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 77647495 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.755624 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.112120 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 15490963 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 47835555 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 7620138 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 4785444 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 10608217 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2561094 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 89115 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.BlockedCycles 49527666 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 1654 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 1892 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 49952 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 101088 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 226 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 6110008 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 396628 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3581 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 77642580 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.762278 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.119818 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 67140338 86.47% 86.47% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 685224 0.88% 87.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 881384 1.14% 88.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1215413 1.57% 90.05% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1119001 1.44% 91.49% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 577018 0.74% 92.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 1310230 1.69% 93.92% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 395483 0.51% 94.43% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4323404 5.57% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 67041875 86.35% 86.35% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 689016 0.89% 87.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 885560 1.14% 88.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1228014 1.58% 89.96% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1141359 1.47% 91.43% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 577108 0.74% 92.17% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 1324549 1.71% 93.88% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 398041 0.51% 94.39% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4357058 5.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 77647495 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.031593 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.198223 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 16447301 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 49466389 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 9519649 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 555058 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1656976 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1018880 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 89951 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 55851060 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 301878 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1656976 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 17376198 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 19158247 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 27017971 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9071618 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3364444 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 53098048 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 14247 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 629745 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 2187800 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.FullRegisterEvents 13035 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 55196889 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 241870306 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 241822297 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 48009 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 40273759 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 14923130 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 426834 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 378971 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 6800028 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 10269000 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6780798 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1063277 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 1318043 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 49318736 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1023913 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 62924434 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 96522 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10293246 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 26052938 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 249929 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 77647495 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.810386 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.515841 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 77642580 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.031875 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.200096 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 16540886 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 49255967 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 9607571 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 552371 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1683667 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1024811 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 90579 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 56316085 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 302289 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1683667 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 17475063 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 18984775 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 27019953 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9154130 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3322955 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 53494037 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 13484 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 621738 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 2157353 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.FullRegisterEvents 548 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 55660367 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 243519467 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 243471355 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 48112 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 40417937 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 15242430 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 429833 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 381699 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 6758508 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 10355148 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 6782314 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1058612 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 1316675 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 49644359 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1043369 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 63195717 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 96260 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 10515144 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 26542188 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 266673 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 77642580 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.813931 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.519230 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 54849449 70.64% 70.64% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 7244024 9.33% 79.97% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 3688560 4.75% 84.72% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 3114192 4.01% 88.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 6252852 8.05% 96.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1400137 1.80% 98.59% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 804405 1.04% 99.62% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 228817 0.29% 99.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 65059 0.08% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 54792876 70.57% 70.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 7218069 9.30% 79.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 3694351 4.76% 84.63% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 3145323 4.05% 88.68% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 6277418 8.09% 96.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1407401 1.81% 98.57% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 809465 1.04% 99.62% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 231906 0.30% 99.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 65771 0.08% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 77647495 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 77642580 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 28907 0.65% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 5 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.65% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4221672 94.79% 95.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 203228 4.56% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 29563 0.66% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 4 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4229523 94.72% 95.38% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 206294 4.62% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 196078 0.31% 0.31% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 29762339 47.30% 47.61% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 47254 0.08% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 1214 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 26685508 42.41% 90.10% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 6232016 9.90% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 195578 0.31% 0.31% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 29951554 47.39% 47.70% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 46938 0.07% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 1212 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 26776565 42.37% 90.15% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 6223855 9.85% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 62924434 # Type of FU issued
-system.cpu0.iq.rate 0.263350 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 4453812 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.070780 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 208088796 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 60644934 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 43952872 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12311 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6553 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 67175656 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6512 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 321336 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 63195717 # Type of FU issued
+system.cpu0.iq.rate 0.264347 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 4465384 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.070660 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 208632682 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 61211746 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 44166006 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 12339 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6563 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5520 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 67458994 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6529 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 322005 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2241404 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3447 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 16174 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 877395 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2276398 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3543 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 16033 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 889328 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 17145295 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 358927 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 17163737 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 367898 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1656976 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 14313344 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 236698 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 50458165 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 105115 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 10269000 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 6780798 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 724480 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 58024 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 3552 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 16174 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 184745 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 145643 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 330388 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 61778089 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 26333265 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1146345 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1683667 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 14223209 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 234272 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 50804503 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 105344 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 10355148 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 6782314 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 742198 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 56887 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 3242 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 16033 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 187141 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 147345 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 334486 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 62025172 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 26418520 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1170545 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 115516 # number of nop insts executed
-system.cpu0.iew.exec_refs 32508411 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 5980040 # Number of branches executed
-system.cpu0.iew.exec_stores 6175146 # Number of stores executed
-system.cpu0.iew.exec_rate 0.258552 # Inst execution rate
-system.cpu0.iew.wb_sent 61260719 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 43958394 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 24186405 # num instructions producing a value
-system.cpu0.iew.wb_consumers 44536826 # num instructions consuming a value
+system.cpu0.iew.exec_nop 116775 # number of nop insts executed
+system.cpu0.iew.exec_refs 32585401 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 6028949 # Number of branches executed
+system.cpu0.iew.exec_stores 6166881 # Number of stores executed
+system.cpu0.iew.exec_rate 0.259451 # Inst execution rate
+system.cpu0.iew.wb_sent 61495183 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 44171526 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24314220 # num instructions producing a value
+system.cpu0.iew.wb_consumers 44686636 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.183974 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.543065 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.184769 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.544105 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 10181243 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 773984 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 288739 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 75990519 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.523900 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.505441 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 10365934 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 776696 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 291216 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 75958913 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.525792 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.508136 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 61812445 81.34% 81.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 6884323 9.06% 90.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2031918 2.67% 93.08% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 1127942 1.48% 94.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1041381 1.37% 95.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 554423 0.73% 96.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 699295 0.92% 97.58% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 364332 0.48% 98.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1474460 1.94% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 61730922 81.27% 81.27% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 6914068 9.10% 90.37% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2040925 2.69% 93.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 1133695 1.49% 94.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1039727 1.37% 95.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 547660 0.72% 96.64% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 699909 0.92% 97.56% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 371161 0.49% 98.05% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1480846 1.95% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 75990519 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 31157319 # Number of instructions committed
-system.cpu0.commit.committedOps 39811398 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 75958913 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 31284581 # Number of instructions committed
+system.cpu0.commit.committedOps 39938560 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 13930999 # Number of memory references committed
-system.cpu0.commit.loads 8027596 # Number of loads committed
-system.cpu0.commit.membars 211461 # Number of memory barriers committed
-system.cpu0.commit.branches 5178005 # Number of branches committed
+system.cpu0.commit.refs 13971736 # Number of memory references committed
+system.cpu0.commit.loads 8078750 # Number of loads committed
+system.cpu0.commit.membars 212403 # Number of memory barriers committed
+system.cpu0.commit.branches 5205711 # Number of branches committed
system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 35182368 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 511213 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1474460 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 35286774 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 514203 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1480846 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 123547695 # The number of ROB reads
-system.cpu0.rob.rob_writes 101683929 # The number of ROB writes
-system.cpu0.timesIdled 881879 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 161290991 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2289851507 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 31079277 # Number of Instructions Simulated
-system.cpu0.committedOps 39733356 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 31079277 # Number of Instructions Simulated
-system.cpu0.cpi 7.688032 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 7.688032 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.130072 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.130072 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 279629599 # number of integer regfile reads
-system.cpu0.int_regfile_writes 45168223 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 22746 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 19898 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 15538839 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 427973 # number of misc regfile writes
-system.cpu0.icache.replacements 984670 # number of replacements
-system.cpu0.icache.tagsinuse 511.607871 # Cycle average of tags in use
-system.cpu0.icache.total_refs 10994375 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 985182 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 11.159740 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 6536916000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 357.062519 # Average occupied blocks per requestor
-system.cpu0.icache.occ_blocks::cpu1.inst 154.545352 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.697388 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::cpu1.inst 0.301846 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.999234 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 5513374 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 5481001 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 10994375 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 5513374 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 5481001 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 10994375 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 5513374 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 5481001 # number of overall hits
-system.cpu0.icache.overall_hits::total 10994375 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 537943 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 527405 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1065348 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 537943 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 527405 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1065348 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 537943 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 527405 # number of overall misses
-system.cpu0.icache.overall_misses::total 1065348 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7287778496 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7022356993 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 14310135489 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 7287778496 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 7022356993 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 14310135489 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 7287778496 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 7022356993 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 14310135489 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 6051317 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 6008406 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 12059723 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 6051317 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 6008406 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 12059723 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 6051317 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 6008406 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 12059723 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088897 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087778 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.088339 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088897 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087778 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.088339 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088897 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087778 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.088339 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13547.492013 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13314.923053 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13432.357773 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.492013 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13314.923053 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13432.357773 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.492013 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13314.923053 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13432.357773 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 4400 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 1635 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 334 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.173653 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets 1635 # average number of cycles each access was blocked
+system.cpu0.rob.rob_reads 123805555 # The number of ROB reads
+system.cpu0.rob.rob_writes 102335061 # The number of ROB writes
+system.cpu0.timesIdled 884089 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 161420732 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 2289699870 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 31205252 # Number of Instructions Simulated
+system.cpu0.committedOps 39859231 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 31205252 # Number of Instructions Simulated
+system.cpu0.cpi 7.660996 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 7.660996 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.130531 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.130531 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 280760557 # number of integer regfile reads
+system.cpu0.int_regfile_writes 45445732 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 22770 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 15502985 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 430013 # number of misc regfile writes
+system.cpu0.icache.replacements 984427 # number of replacements
+system.cpu0.icache.tagsinuse 510.429233 # Cycle average of tags in use
+system.cpu0.icache.total_refs 11039860 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 984939 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 11.208674 # Average number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.occ_blocks::cpu0.inst 356.685952 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu1.inst 153.743281 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.696652 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::cpu1.inst 0.300280 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.996932 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 5569328 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 5470532 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 11039860 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 5569328 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 5470532 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 11039860 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 5569328 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 5470532 # number of overall hits
+system.cpu0.icache.overall_hits::total 11039860 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 540556 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 524651 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 1065207 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 540556 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 524651 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 1065207 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 540556 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 524651 # number of overall misses
+system.cpu0.icache.overall_misses::total 1065207 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7319258495 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6971682996 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 14290941491 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 7319258495 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 6971682996 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 14290941491 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 7319258495 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 6971682996 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 14290941491 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 6109884 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995183 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 12105067 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 6109884 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 5995183 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 12105067 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 6109884 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 5995183 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 12105067 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088472 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087512 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.087997 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088472 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087512 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.087997 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088472 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087512 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.087997 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13540.240965 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.229692 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13416.116765 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13416.116765 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13540.240965 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.229692 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13416.116765 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 4720 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 314 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.031847 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40608 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39535 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 80143 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 40608 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst 39535 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 80143 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 40608 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst 39535 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 80143 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 497335 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 487870 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 985205 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 497335 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 487870 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 985205 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 497335 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 487870 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 985205 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5948053496 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5711985994 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 11660039490 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5948053496 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5711985994 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 11660039490 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5948053496 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5711985994 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 11660039490 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 40959 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 39286 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 80245 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 40959 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst 39286 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 80245 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 40959 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst 39286 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 80245 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 499597 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485365 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 984962 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 499597 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 485365 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 984962 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 499597 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 485365 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 984962 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5974261995 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5687350997 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 11661612992 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5974261995 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5687350997 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 11661612992 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5974261995 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5687350997 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 11661612992 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.082186 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081198 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081694 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.082186 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081198 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.081694 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.082186 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081198 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.081694 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11959.853009 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11708.008269 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.140392 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11959.853009 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11708.008269 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.140392 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11959.853009 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11708.008269 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.140392 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081769 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080959 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11958.162269 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11717.678442 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11839.657765 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11958.162269 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11717.678442 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11839.657765 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11958.162269 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11717.678442 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11839.657765 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 643493 # number of replacements
-system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 21548288 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 644005 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 33.459815 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 43208000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 318.069743 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_blocks::cpu1.data 193.922971 # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data 0.621230 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::cpu1.data 0.378756 # Average percentage of cache occupancy
+system.cpu0.dcache.replacements 643954 # number of replacements
+system.cpu0.dcache.tagsinuse 511.992718 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 21537903 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 644466 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 33.419766 # Average number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data 318.437002 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu1.data 193.555716 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data 0.621947 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::cpu1.data 0.378039 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7070467 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 6719560 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 13790027 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 3778333 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 3485501 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 7263834 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125105 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 118624 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 243729 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127190 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120429 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 247619 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 10848800 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 10205061 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 21053861 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 10848800 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 10205061 # number of overall hits
-system.cpu0.dcache.overall_hits::total 21053861 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 426518 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 319237 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 745755 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1396624 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 1562374 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2958998 # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6770 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6794 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 13564 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 8 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1823142 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 1881611 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 3704753 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1823142 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 1881611 # number of overall misses
-system.cpu0.dcache.overall_misses::total 3704753 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6341434500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4955315500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 11296750000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 54124528351 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 59881914802 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 114006443153 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91205000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94667500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 185872500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 39000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 65000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 104000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 60465962851 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 64837230302 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 125303193153 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 60465962851 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 64837230302 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 125303193153 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 7496985 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 7038797 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 14535782 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 5174957 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 5047875 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 10222832 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 131875 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 125418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 257293 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127193 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120434 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 247627 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 12671942 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 12086672 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 24758614 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 12671942 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 12086672 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 24758614 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.056892 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045354 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.051305 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269881 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.309511 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.289450 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051336 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054171 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052718 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000024 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000042 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000032 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143872 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.155677 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.149635 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143872 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.155677 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.149635 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14867.917649 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15522.372093 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 15148.071418 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38753.829485 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38327.516204 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38528.732751 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13471.935007 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13933.985870 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13703.369213 # average LoadLockedReq miss latency
+system.cpu0.dcache.ReadReq_hits::cpu0.data 7114821 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 6667161 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 13781982 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 3771949 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 3489739 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 7261688 # number of WriteReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125842 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117705 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 243547 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127851 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119764 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 247615 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 10886770 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 10156900 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 21043670 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 10886770 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 10156900 # number of overall hits
+system.cpu0.dcache.overall_hits::total 21043670 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 435511 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 315516 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 751027 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1388695 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 1572418 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 2961113 # number of WriteReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6824 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6787 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 13611 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 4 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 1824206 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 1887934 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 3712140 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 1824206 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 1887934 # number of overall misses
+system.cpu0.dcache.overall_misses::total 3712140 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6465462500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4867480500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 11332943000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52611155364 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61827357784 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 114438513148 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92173500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 95497500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 187671000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 78000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 130000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 59076617864 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 66694838284 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 125771456148 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 59076617864 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 66694838284 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 125771456148 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 7550332 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 6982677 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 14533009 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 5160644 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 5062157 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 10222801 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132666 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124492 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 257158 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127855 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119770 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 247625 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 12710976 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 12044834 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 24755810 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 12710976 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 12044834 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 24755810 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057681 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045186 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.051677 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.269093 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310622 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.289658 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051437 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054518 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052929 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000031 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000050 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000040 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143514 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156742 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.149950 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143514 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156742 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.149950 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14845.692761 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15427.048074 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 15089.927526 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37885.320653 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39319.924972 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 38647.128005 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13507.253810 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14070.649772 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13788.186026 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33165.799949 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 34458.360576 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 33822.279961 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33165.799949 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 34458.360576 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 33822.279961 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 35965 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 14941 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 3389 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 263 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10.612275 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 56.809886 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32384.839138 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35326.890815 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 33881.118748 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32384.839138 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35326.890815 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 33881.118748 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 35462 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 15651 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 3547 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 261 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.997745 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 59.965517 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 607854 # number of writebacks
-system.cpu0.dcache.writebacks::total 607854 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 215439 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 144497 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 359936 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1276945 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1433111 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 2710056 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 667 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 710 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1377 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1492384 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data 1577608 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 3069992 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1492384 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data 1577608 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 3069992 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 211079 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 174740 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 385819 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119679 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129263 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 248942 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6103 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6084 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12187 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 330758 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 304003 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 634761 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 330758 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 304003 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 634761 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2867323500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2359031500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5226355000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4068255992 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4371447438 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8439703430 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71165500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73921500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145087000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 33000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6935579492 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6730478938 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 13666058430 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6935579492 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6730478938 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 13666058430 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91842786000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90513364000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356150000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14606778738 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18392840622 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 32999619360 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.writebacks::writebacks 608473 # number of writebacks
+system.cpu0.dcache.writebacks::total 608473 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 221772 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 142997 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 364769 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1269356 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1442834 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 2712190 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 679 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1379 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1491128 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 1585831 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 3076959 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1491128 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 1585831 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 3076959 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213739 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 172519 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 386258 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 119339 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 129584 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 248923 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6145 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6087 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12232 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 333078 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 302103 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 635181 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 333078 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 302103 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 635181 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2903093500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2321765000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5224858500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3977310493 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4483624933 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8460935426 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71679000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74936000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146615000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 44000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 110000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6880403993 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6805389933 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 13685793926 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6880403993 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6805389933 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 13685793926 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91929858500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90426612500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356471000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14888104285 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18626460302 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33514564587 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106449564738 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 108906204622 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215355769360 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028155 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024825 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026543 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023127 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025607 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046279 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048510 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047366 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000024 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.025638 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026102 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025152 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.025638 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13584.124901 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13500.237496 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13546.131735 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33993.064715 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33818.242173 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33902.288204 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11660.740619 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12150.147929 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11905.062772 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106817962785 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109053072802 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215871035587 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028309 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024707 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026578 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023125 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025599 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024350 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046319 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048895 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047566 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.025658 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026204 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025082 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.025658 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13582.422955 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13458.024913 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13526.861580 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33327.834932 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34600.143019 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33990.171362 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.605370 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12310.826351 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11986.183780 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20968.742984 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22139.514867 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21529.455070 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20657.035268 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22526.720797 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21546.289839 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 7102253 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 5695769 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 349355 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 4570648 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 3841672 # Number of BTB hits
+system.cpu1.branchPred.lookups 7047379 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5653088 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 345044 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4644809 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3819502 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 84.050927 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 676938 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 35276 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 82.231627 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 672042 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 34964 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 25380131 # DTB read hits
-system.cpu1.dtb.read_misses 40834 # DTB read misses
-system.cpu1.dtb.write_hits 5811015 # DTB write hits
-system.cpu1.dtb.write_misses 9771 # DTB write misses
+system.cpu1.dtb.read_hits 25308350 # DTB read hits
+system.cpu1.dtb.read_misses 36279 # DTB read misses
+system.cpu1.dtb.write_hits 5820677 # DTB write hits
+system.cpu1.dtb.write_misses 9386 # DTB write misses
system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1494 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 5518 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1305 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 250 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 637 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 25420965 # DTB read accesses
-system.cpu1.dtb.write_accesses 5820786 # DTB write accesses
+system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 25344629 # DTB read accesses
+system.cpu1.dtb.write_accesses 5830063 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 31191146 # DTB hits
-system.cpu1.dtb.misses 50605 # DTB misses
-system.cpu1.dtb.accesses 31241751 # DTB accesses
-system.cpu1.itb.inst_hits 6010554 # ITB inst hits
-system.cpu1.itb.inst_misses 6924 # ITB inst misses
+system.cpu1.dtb.hits 31129027 # DTB hits
+system.cpu1.dtb.misses 45665 # DTB misses
+system.cpu1.dtb.accesses 31174692 # DTB accesses
+system.cpu1.itb.inst_hits 5997294 # ITB inst hits
+system.cpu1.itb.inst_misses 6928 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 686 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2690 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 2607 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1462 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 6017478 # ITB inst accesses
-system.cpu1.itb.hits 6010554 # DTB hits
-system.cpu1.itb.misses 6924 # DTB misses
-system.cpu1.itb.accesses 6017478 # DTB accesses
-system.cpu1.numCycles 234669310 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 6004222 # ITB inst accesses
+system.cpu1.itb.hits 5997294 # DTB hits
+system.cpu1.itb.misses 6928 # DTB misses
+system.cpu1.itb.accesses 6004222 # DTB accesses
+system.cpu1.numCycles 234192897 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 15209580 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 46712783 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 7102253 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 4518610 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 10317375 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2619576 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 83943 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.BlockedCycles 47843149 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 2062 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 49108 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 95676 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 186 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 6008408 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 439180 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3193 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 75397416 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.769986 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.133362 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 15145693 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 46615728 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 7047379 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 4491544 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 10277592 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2615595 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 81100 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.BlockedCycles 47506260 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 991 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 2050 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 43629 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 94802 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 5995185 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 443145 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3161 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 74942742 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.773391 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.139188 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 65087895 86.33% 86.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 627947 0.83% 87.16% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 837408 1.11% 88.27% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 1205044 1.60% 89.87% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1066340 1.41% 91.28% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 537838 0.71% 92.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1370888 1.82% 93.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 355288 0.47% 94.29% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4308768 5.71% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 64672921 86.30% 86.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 620255 0.83% 87.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 831184 1.11% 88.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 1205105 1.61% 89.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1036791 1.38% 91.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 535666 0.71% 91.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1369144 1.83% 93.77% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 351637 0.47% 94.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4320039 5.76% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 75397416 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.030265 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.199058 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 16234163 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 47629419 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 9365333 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 455355 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1710994 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 954633 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 86850 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 54991941 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 289065 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1710994 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 17174187 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 18737860 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 25818505 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 8802452 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3151356 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 51852963 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 7784 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 495819 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 2156102 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.FullRegisterEvents 16790 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 53921236 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 237794819 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 237752758 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 42061 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 38119457 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 15801778 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 406275 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 360043 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 6312412 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 9898501 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6682455 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 887681 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 1092966 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 47793867 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 962748 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 60992947 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 83561 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10588710 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 27790687 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 254225 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 75397416 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.808953 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.518534 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 74942742 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.030092 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.199048 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 16159158 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 47296340 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 9320957 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 457304 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1706877 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 946060 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 86144 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 54858013 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 286862 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1706877 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 17095317 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 18544880 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 25731919 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 8763106 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 3098607 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 51692102 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 7152 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 482288 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 2118635 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.FullRegisterEvents 58 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 53768769 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 237295359 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 237252975 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 42384 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 37974901 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 15793867 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 403461 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 357400 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 6244351 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 9843526 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6693253 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 891235 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 1110531 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 47673025 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 943085 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 60813772 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 81704 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10584682 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 28040387 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 237278 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 74942742 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.811470 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.521589 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 53544512 71.02% 71.02% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 6720979 8.91% 79.93% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 3575565 4.74% 84.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2884458 3.83% 88.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 6227948 8.26% 96.76% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1437657 1.91% 98.67% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 736271 0.98% 99.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 210447 0.28% 99.92% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 59579 0.08% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 53203952 70.99% 70.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 6663470 8.89% 79.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 3519082 4.70% 84.58% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 2892768 3.86% 88.44% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 6218608 8.30% 96.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1439258 1.92% 98.66% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 735883 0.98% 99.64% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 209954 0.28% 99.92% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 59767 0.08% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 75397416 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 74942742 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 24253 0.55% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 3 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4149284 94.86% 95.41% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 200652 4.59% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 24319 0.56% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.56% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4142702 94.84% 95.40% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 201068 4.60% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 167588 0.27% 0.27% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 28559163 46.82% 47.10% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46488 0.08% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 897 0.00% 47.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.18% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 26112884 42.81% 89.99% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6105909 10.01% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 168088 0.28% 0.28% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 28444166 46.77% 47.05% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 46611 0.08% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 900 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 26040619 42.82% 89.95% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6113365 10.05% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 60992947 # Type of FU issued
-system.cpu1.iq.rate 0.259910 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 4374192 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.071716 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 201880877 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 59353845 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 41952881 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 10603 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 5821 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 4743 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 65193949 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 5602 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 306044 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 60813772 # Type of FU issued
+system.cpu1.iq.rate 0.259674 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 4368089 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.071827 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 201054983 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 59209073 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 41787342 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 10574 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 5911 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 4752 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 65008196 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 5577 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 302847 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2270775 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2267035 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3168 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 14837 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 853246 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 14674 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 853664 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 16957357 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 451019 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 16940133 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 457083 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1710994 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 14077639 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 237686 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 48863462 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 99358 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 9898501 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6682455 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 687943 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 54116 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 4064 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 14837 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 169399 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 135230 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 304629 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 59633634 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 25710347 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1359313 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1706877 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 13961840 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 229523 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 48721689 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 98782 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 9843526 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6693253 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 669936 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 49642 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 3791 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 14674 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 166878 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 133542 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 300420 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 59454145 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 25635874 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1359627 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 106847 # number of nop insts executed
-system.cpu1.iew.exec_refs 31763994 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 5570991 # Number of branches executed
-system.cpu1.iew.exec_stores 6053647 # Number of stores executed
-system.cpu1.iew.exec_rate 0.254118 # Inst execution rate
-system.cpu1.iew.wb_sent 59059835 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 41957624 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 22877560 # num instructions producing a value
-system.cpu1.iew.wb_consumers 41856848 # num instructions consuming a value
+system.cpu1.iew.exec_nop 105579 # number of nop insts executed
+system.cpu1.iew.exec_refs 31697240 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 5530994 # Number of branches executed
+system.cpu1.iew.exec_stores 6061366 # Number of stores executed
+system.cpu1.iew.exec_rate 0.253868 # Inst execution rate
+system.cpu1.iew.wb_sent 58875000 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 41792094 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 22753184 # num instructions producing a value
+system.cpu1.iew.wb_consumers 41716740 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.178795 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.546567 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.178452 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.545421 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 10488461 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 708523 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 263786 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 73686422 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.514905 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.496046 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 10509796 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 705807 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 260176 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 73235865 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.516331 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.496791 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 60141742 81.62% 81.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 6665026 9.05% 90.66% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 1916982 2.60% 93.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 1022287 1.39% 94.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 952512 1.29% 95.95% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 518669 0.70% 96.65% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 704589 0.96% 97.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 372223 0.51% 98.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1392392 1.89% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 59723279 81.55% 81.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 6657456 9.09% 90.64% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 1906988 2.60% 93.24% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 1010218 1.38% 94.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 959564 1.31% 95.93% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 524950 0.72% 96.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 702340 0.96% 97.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 373722 0.51% 98.12% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1377348 1.88% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 73686422 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 29303210 # Number of instructions committed
-system.cpu1.commit.committedOps 37941475 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 73235865 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 29175677 # Number of instructions committed
+system.cpu1.commit.committedOps 37813970 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 13456935 # Number of memory references committed
-system.cpu1.commit.loads 7627726 # Number of loads committed
-system.cpu1.commit.membars 192181 # Number of memory barriers committed
-system.cpu1.commit.branches 4783662 # Number of branches committed
+system.cpu1.commit.refs 13416080 # Number of memory references committed
+system.cpu1.commit.loads 7576491 # Number of loads committed
+system.cpu1.commit.membars 191234 # Number of memory barriers committed
+system.cpu1.commit.branches 4755917 # Number of branches committed
system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 33675461 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 480108 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 1392392 # number cycles where commit BW limit reached
+system.cpu1.commit.int_insts 33570741 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 477112 # Number of function calls committed.
+system.cpu1.commit.bw_lim_events 1377348 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 119835622 # The number of ROB reads
-system.cpu1.rob.rob_writes 98622587 # The number of ROB writes
-system.cpu1.timesIdled 873829 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 159271894 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2285541005 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 29230871 # Number of Instructions Simulated
-system.cpu1.committedOps 37869136 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 29230871 # Number of Instructions Simulated
-system.cpu1.cpi 8.028133 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 8.028133 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.124562 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.124562 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 270257014 # number of integer regfile reads
-system.cpu1.int_regfile_writes 43086162 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 22099 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 19636 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 14849439 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 404495 # number of misc regfile writes
+system.cpu1.rob.rob_reads 119309924 # The number of ROB reads
+system.cpu1.rob.rob_writes 98406667 # The number of ROB writes
+system.cpu1.timesIdled 873323 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 159250155 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2285809379 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 29104625 # Number of Instructions Simulated
+system.cpu1.committedOps 37742918 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 29104625 # Number of Instructions Simulated
+system.cpu1.cpi 8.046587 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 8.046587 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.124276 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.124276 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 269354983 # number of integer regfile reads
+system.cpu1.int_regfile_writes 42881539 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 22070 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 19722 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 14807942 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 402452 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1192737213912 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192737213912 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1192737213912 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1192818443837 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192818443837 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1192818443837 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 83053 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 83054 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/projects/pd/randd/dist/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/projects/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
+warn: add_child('terminal'): child 'terminal' already has parent
warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
-Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 16:30:44
-gem5 started Jan 23 2013 19:14:30
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 13 2013 11:25:23
+gem5 started Feb 13 2013 18:24:23
+gem5 executing on u200540-lin
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
-warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /projects/pd/randd/dist/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5136817990000 because m5_exit instruction encountered
+Exiting @ tick 5140860798000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.136862 # Number of seconds simulated
-sim_ticks 5136862311000 # Number of ticks simulated
-final_tick 5136862311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.140861 # Number of seconds simulated
+sim_ticks 5140860798000 # Number of ticks simulated
+final_tick 5140860798000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 202420 # Simulator instruction rate (inst/s)
-host_op_rate 400133 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2548945395 # Simulator tick rate (ticks/s)
-host_mem_usage 760276 # Number of bytes of host memory used
-host_seconds 2015.29 # Real time elapsed on the host
-sim_insts 407935752 # Number of instructions simulated
-sim_ops 806383618 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2490880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1078272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10788032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14361024 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1078272 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1078272 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9547840 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9547840 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38920 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16848 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 168563 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 224391 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149185 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149185 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 484903 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 660 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 209909 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2100121 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2795680 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 209909 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 209909 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1858691 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1858691 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1858691 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 484903 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 660 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 209909 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2100121 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4654371 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 224391 # Total number of read requests seen
-system.physmem.writeReqs 149185 # Total number of write requests seen
-system.physmem.cpureqs 388105 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14361024 # Total number of bytes read from memory
-system.physmem.bytesWritten 9547840 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14361024 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9547840 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 135 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3903 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 14157 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 13127 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 13393 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 16573 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13535 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 12962 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13580 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 16342 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13760 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 13186 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 13242 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 15501 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 13187 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12719 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 13259 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 9129 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 8570 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8702 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 11948 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8746 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 8430 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8914 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 11741 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8779 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8505 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 8628 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 10975 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8406 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 8212 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8505 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 10995 # Track writes on a per bank basis
+host_inst_rate 170494 # Simulator instruction rate (inst/s)
+host_op_rate 337025 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2148706625 # Simulator tick rate (ticks/s)
+host_mem_usage 754648 # Number of bytes of host memory used
+host_seconds 2392.54 # Real time elapsed on the host
+sim_insts 407913764 # Number of instructions simulated
+sim_ops 806343994 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2474560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1078400 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10800768 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14357184 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1078400 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1078400 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9566720 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9566720 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38665 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 16850 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 168762 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 224331 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149480 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149480 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 481351 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 598 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 209770 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2100965 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2792759 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 209770 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 209770 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1860918 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1860918 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1860918 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 481351 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 598 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 209770 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2100965 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4653677 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 224331 # Total number of read requests seen
+system.physmem.writeReqs 149480 # Total number of write requests seen
+system.physmem.cpureqs 389156 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 14357184 # Total number of bytes read from memory
+system.physmem.bytesWritten 9566720 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 14357184 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9566720 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 64 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4099 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 14350 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 13262 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 13450 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 16479 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 13640 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 13135 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 13368 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 16367 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 13625 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 12973 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 13147 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 15567 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 13297 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 12659 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 13305 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 15643 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 9342 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 8759 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 8814 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 11838 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 8747 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 8497 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 8701 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 11708 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 8726 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 8403 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 8587 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 10999 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 8504 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 8205 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8619 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 11031 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 794 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5136862258500 # Total gap between requests
+system.physmem.numWrRetry 1147 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5140860745500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 224391 # Categorize read packet sizes
+system.physmem.readPktSize::6 224331 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 149979 # categorize write packet sizes
+system.physmem.writePktSize::6 150627 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 3903 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4099 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 173046 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 19422 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 7578 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3497 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3020 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 173172 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 19537 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 7348 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3492 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2979 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2415 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 1930 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1866 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 1777 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 1691 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1133 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1016 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 933 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 874 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 828 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 817 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 915 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 867 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 384 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 221 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1913 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1865 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 1784 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 1717 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1139 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1032 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 969 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 886 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 806 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 796 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 879 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 856 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 418 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 233 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 28 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 5322 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 5660 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 6306 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 6395 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 6433 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 6455 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 6463 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 6468 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 6472 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1165 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 827 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 181 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 92 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 54 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 5364 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 5718 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 6328 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 6401 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 6443 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 6469 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 6476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 6481 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 6485 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6499 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 1136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 782 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 172 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 98 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 56 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 30 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 23 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 4730288859 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 9241012609 # Sum of mem lat for all requests
-system.physmem.totBusLat 1121280000 # Total cycles spent in databus access
-system.physmem.totBankLat 3389443750 # Total cycles spent in bank access
-system.physmem.avgQLat 21093.25 # Average queueing delay per request
-system.physmem.avgBankLat 15114.17 # Average bank access latency per request
+system.physmem.totQLat 4794174501 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 9303317001 # Sum of mem lat for all requests
+system.physmem.totBusLat 1121335000 # Total cycles spent in databus access
+system.physmem.totBankLat 3387807500 # Total cycles spent in bank access
+system.physmem.avgQLat 21377.08 # Average queueing delay per request
+system.physmem.avgBankLat 15106.13 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 41207.43 # Average memory access latency
-system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 41483.22 # Average memory access latency
+system.physmem.avgRdBW 2.79 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.79 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 12.83 # Average write queue length over time
-system.physmem.readRowHits 193267 # Number of row buffer hits during reads
-system.physmem.writeRowHits 105785 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 86.18 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 70.91 # Row buffer hit rate for writes
-system.physmem.avgGap 13750514.64 # Average gap between requests
-system.iocache.replacements 47583 # number of replacements
-system.iocache.tagsinuse 0.137403 # Cycle average of tags in use
+system.physmem.avgWrQLen 8.88 # Average write queue length over time
+system.physmem.readRowHits 193356 # Number of row buffer hits during reads
+system.physmem.writeRowHits 105797 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.22 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 70.78 # Row buffer hit rate for writes
+system.physmem.avgGap 13752566.79 # Average gap between requests
+system.iocache.replacements 47574 # number of replacements
+system.iocache.tagsinuse 0.128668 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47599 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47590 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4991910569000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.137403 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.008588 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.008588 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
+system.iocache.warmup_cycle 4991908358000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.128668 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.008042 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.008042 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 909 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
-system.iocache.overall_misses::total 47632 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144324932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 144324932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10020383160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10020383160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10164708092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10164708092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10164708092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10164708092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47629 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47629 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47629 # number of overall misses
+system.iocache.overall_misses::total 47629 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143200932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 143200932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10097082160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10097082160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10240283092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10240283092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10240283092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10240283092 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47629 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47629 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47629 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47629 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158251.021930 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 158251.021930 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 214477.379281 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 214477.379281 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 213400.824908 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 213400.824908 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 213400.824908 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 133472 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157536.778878 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 157536.778878 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 216119.053082 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 216119.053082 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 215001.009721 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 215001.009721 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 215001.009721 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 136887 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 12161 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 12650 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.975413 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.821107 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 46673 # number of writebacks
-system.iocache.writebacks::total 46673 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
+system.iocache.writebacks::writebacks 46667 # number of writebacks
+system.iocache.writebacks::total 46667 # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 909 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 909 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96878242 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 96878242 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7589579568 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 7589579568 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 7686457810 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7686457810 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 7686457810 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47629 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47629 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47629 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47629 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95911989 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 95911989 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7666293817 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 7666293817 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 7762205806 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7762205806 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 7762205806 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 106226.142544 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 106226.142544 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162448.192808 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 162448.192808 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 161371.720902 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 161371.720902 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105513.739274 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 105513.739274 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 164090.193001 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 164090.193001 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 162972.260724 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 162972.260724 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 86190273 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86190273 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1107531 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 81286866 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 79207834 # Number of BTB hits
+system.cpu.branchPred.lookups 86195570 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86195570 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1107298 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 81287324 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 79211919 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.442352 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 97.446828 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.numCycles 448143159 # number of cpu cycles simulated
+system.cpu.numCycles 448232203 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27503051 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 425930482 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86190273 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79207834 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 163575255 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4699027 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 119359 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 63002200 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36275 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 56191 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 501 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9012986 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 485449 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3601 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 257845073 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.261142 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.418049 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27444393 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 425935714 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86195570 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79211919 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 163577459 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4703661 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 120329 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 63100618 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 36734 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 50393 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 353 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9010824 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 484273 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3255 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 257888489 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.260624 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.418001 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 94696195 36.73% 36.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1566516 0.61% 37.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71918479 27.89% 65.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 936665 0.36% 65.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1597376 0.62% 66.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2419164 0.94% 67.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1071712 0.42% 67.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1371295 0.53% 68.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82267671 31.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 94737944 36.74% 36.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1567529 0.61% 37.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71915391 27.89% 65.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 936422 0.36% 65.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1600476 0.62% 66.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2419747 0.94% 67.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1072144 0.42% 67.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1374255 0.53% 68.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82264581 31.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 257845073 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192328 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.950434 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31188651 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60472166 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159373926 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3258089 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3552241 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 837743575 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 790 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3552241 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33924496 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37350938 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 11010617 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159571112 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12435669 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834099694 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 18960 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5861549 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4743149 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 8341 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 995593221 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1810589255 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1810588751 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 504 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964361742 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31231472 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 459351 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 467339 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28773559 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17056832 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10125853 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1239786 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 991765 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 827988990 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1249374 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 823075347 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 149433 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21943198 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33340930 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 196529 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 257845073 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.192131 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.383978 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 257888489 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192301 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.950257 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31158433 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60539785 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159369860 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3262201 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3558210 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 837747525 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 908 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3558210 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33896779 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37429027 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10979367 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159568616 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12456490 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834117350 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19334 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5870357 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4754276 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7741 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 995632267 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1810669462 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1810668566 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 896 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964317189 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31315071 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 459232 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 466806 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28815526 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17065121 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10125717 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1247966 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 991465 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 828007231 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1251140 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 823065161 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 148512 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 22000890 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33478625 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 198442 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 257888489 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.191554 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.384086 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71377289 27.68% 27.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15522092 6.02% 33.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10290654 3.99% 37.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7462079 2.89% 40.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75909573 29.44% 70.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3836908 1.49% 71.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72514603 28.12% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 779740 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 152135 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 71416188 27.69% 27.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15522620 6.02% 33.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10297220 3.99% 37.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7470539 2.90% 40.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75900478 29.43% 70.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3837629 1.49% 71.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72511548 28.12% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 780997 0.30% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 151270 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 257845073 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 257888489 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 361447 33.94% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.94% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 553013 51.93% 85.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 150537 14.13% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 362608 34.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 553228 51.88% 85.88% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 150521 14.12% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 311265 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795546265 96.66% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 311367 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795535215 96.66% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17838711 2.17% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9379106 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17840146 2.17% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9378433 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 823075347 # Type of FU issued
-system.cpu.iq.rate 1.836635 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1064997 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001294 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1905340193 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 851191548 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 818612199 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 185 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 823828994 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 85 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1638396 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 823065161 # Type of FU issued
+system.cpu.iq.rate 1.836247 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1066357 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001296 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1905364388 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 851269170 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 818594497 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 333 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 414 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 81 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 823820002 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 149 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1640065 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3078783 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 22684 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11490 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1711608 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3087216 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 23041 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11568 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1713876 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932396 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11890 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932419 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 12043 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3552241 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26088999 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2114690 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 829238364 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 319607 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17056832 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10125853 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 718701 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1615260 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11047 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11490 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 650165 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 594804 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1244969 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 821209157 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17428424 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1866189 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3558210 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26163339 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2115746 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 829258371 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 321958 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17065121 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10125717 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 719121 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1615790 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11387 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11568 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 649229 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 593828 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1243057 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 821192043 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17430508 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1873117 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26576192 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83198528 # Number of branches executed
-system.cpu.iew.exec_stores 9147768 # Number of stores executed
-system.cpu.iew.exec_rate 1.832471 # Inst execution rate
-system.cpu.iew.wb_sent 820748086 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 818612249 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 639805768 # num instructions producing a value
-system.cpu.iew.wb_consumers 1045573656 # num instructions consuming a value
+system.cpu.iew.exec_refs 26576754 # number of memory reference insts executed
+system.cpu.iew.exec_branches 83195358 # Number of branches executed
+system.cpu.iew.exec_stores 9146246 # Number of stores executed
+system.cpu.iew.exec_rate 1.832068 # Inst execution rate
+system.cpu.iew.wb_sent 820730031 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 818594578 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 639788924 # num instructions producing a value
+system.cpu.iew.wb_consumers 1045548924 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.826676 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611918 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.826273 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611917 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 22746956 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052843 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1113134 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 254292832 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.171083 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.853965 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 22806507 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1052696 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 1111685 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 254330279 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 3.170460 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.853927 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82512721 32.45% 32.45% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11810250 4.64% 37.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3911409 1.54% 38.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74946899 29.47% 68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2433458 0.96% 69.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1482000 0.58% 69.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 941049 0.37% 70.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70920641 27.89% 97.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5334405 2.10% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 82551524 32.46% 32.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11813015 4.64% 37.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3912372 1.54% 38.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74944552 29.47% 68.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2436279 0.96% 69.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1482727 0.58% 69.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 942941 0.37% 70.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70918770 27.88% 97.91% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5328099 2.09% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254292832 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407935752 # Number of instructions committed
-system.cpu.commit.committedOps 806383618 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 254330279 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 407913764 # Number of instructions committed
+system.cpu.commit.committedOps 806343994 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22392291 # Number of memory references committed
-system.cpu.commit.loads 13978046 # Number of loads committed
-system.cpu.commit.membars 473511 # Number of memory barriers committed
-system.cpu.commit.branches 82192705 # Number of branches committed
+system.cpu.commit.refs 22389743 # Number of memory references committed
+system.cpu.commit.loads 13977902 # Number of loads committed
+system.cpu.commit.membars 473467 # Number of memory barriers committed
+system.cpu.commit.branches 82188680 # Number of branches committed
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735323034 # Number of committed integer instructions.
+system.cpu.commit.int_insts 735286834 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5334405 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5328099 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1078010714 # The number of ROB reads
-system.cpu.rob.rob_writes 1661832245 # The number of ROB writes
-system.cpu.timesIdled 1221118 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 190298086 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9825578883 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407935752 # Number of Instructions Simulated
-system.cpu.committedOps 806383618 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407935752 # Number of Instructions Simulated
-system.cpu.cpi 1.098563 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.098563 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.910280 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.910280 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1506729750 # number of integer regfile reads
-system.cpu.int_regfile_writes 976791944 # number of integer regfile writes
-system.cpu.fp_regfile_reads 50 # number of floating regfile reads
-system.cpu.misc_regfile_reads 264623965 # number of misc regfile reads
-system.cpu.misc_regfile_writes 402412 # number of misc regfile writes
-system.cpu.icache.replacements 1049766 # number of replacements
-system.cpu.icache.tagsinuse 510.907265 # Cycle average of tags in use
-system.cpu.icache.total_refs 7899601 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1050278 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.521438 # Average number of references to valid blocks.
+system.cpu.rob.rob_reads 1078074430 # The number of ROB reads
+system.cpu.rob.rob_writes 1661878047 # The number of ROB writes
+system.cpu.timesIdled 1220922 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 190343714 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9833486813 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407913764 # Number of Instructions Simulated
+system.cpu.committedOps 806343994 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 407913764 # Number of Instructions Simulated
+system.cpu.cpi 1.098841 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.098841 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.910050 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.910050 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 1506675506 # number of integer regfile reads
+system.cpu.int_regfile_writes 976772305 # number of integer regfile writes
+system.cpu.fp_regfile_reads 81 # number of floating regfile reads
+system.cpu.misc_regfile_reads 264620330 # number of misc regfile reads
+system.cpu.misc_regfile_writes 402287 # number of misc regfile writes
+system.cpu.icache.replacements 1047202 # number of replacements
+system.cpu.icache.tagsinuse 510.392599 # Cycle average of tags in use
+system.cpu.icache.total_refs 7900027 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1047714 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 7.540251 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 56071908000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.907265 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.997866 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.997866 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 7899601 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7899601 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 7899601 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7899601 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 7899601 # number of overall hits
-system.cpu.icache.overall_hits::total 7899601 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1113380 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1113380 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1113380 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1113380 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1113380 # number of overall misses
-system.cpu.icache.overall_misses::total 1113380 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 15333448488 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 15333448488 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 15333448488 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 15333448488 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 15333448488 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 15333448488 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 9012981 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 9012981 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 9012981 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 9012981 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 9012981 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 9012981 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123531 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.123531 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.123531 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.123531 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.123531 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.123531 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13771.981253 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13771.981253 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13771.981253 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13771.981253 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13771.981253 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 13782 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 510.392599 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.996861 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.996861 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 7900027 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7900027 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 7900027 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 7900027 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 7900027 # number of overall hits
+system.cpu.icache.overall_hits::total 7900027 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1110794 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1110794 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1110794 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1110794 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1110794 # number of overall misses
+system.cpu.icache.overall_misses::total 1110794 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15299065993 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15299065993 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 15299065993 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 15299065993 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 15299065993 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 15299065993 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 9010821 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 9010821 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 9010821 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 9010821 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 9010821 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 9010821 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123273 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.123273 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.123273 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.123273 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.123273 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.123273 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13773.090234 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 13773.090234 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 13773.090234 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13773.090234 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 13773.090234 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 10781 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 279 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 45.485149 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 38.641577 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60842 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 60842 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 60842 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 60842 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 60842 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 60842 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1052538 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1052538 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1052538 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1052538 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1052538 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1052538 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12613347488 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12613347488 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12613347488 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12613347488 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12613347488 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12613347488 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116780 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.116780 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116780 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.116780 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.745469 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11983.745469 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.745469 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11983.745469 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 60632 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 60632 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 60632 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 60632 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 60632 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 60632 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1050162 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1050162 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1050162 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1050162 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1050162 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1050162 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12588415993 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 12588415993 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12588415993 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12588415993 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12588415993 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 12588415993 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116545 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.116545 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116545 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.116545 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11987.118171 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11987.118171 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11987.118171 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11987.118171 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.replacements 9783 # number of replacements
-system.cpu.itb_walker_cache.tagsinuse 6.014217 # Cycle average of tags in use
-system.cpu.itb_walker_cache.total_refs 28141 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.sampled_refs 9798 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.avg_refs 2.872117 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.warmup_cycle 5106728958500 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.014217 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375889 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.occ_percent::total 0.375889 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 28140 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 28140 # number of ReadReq hits
+system.cpu.itb_walker_cache.replacements 9719 # number of replacements
+system.cpu.itb_walker_cache.tagsinuse 6.023103 # Cycle average of tags in use
+system.cpu.itb_walker_cache.total_refs 25822 # Total number of references to valid blocks.
+system.cpu.itb_walker_cache.sampled_refs 9733 # Sample count of references to valid blocks.
+system.cpu.itb_walker_cache.avg_refs 2.653036 # Average number of references to valid blocks.
+system.cpu.itb_walker_cache.warmup_cycle 5104044206500 # Cycle when the warmup percentage was hit.
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.023103 # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376444 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total 0.376444 # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25827 # number of ReadReq hits
+system.cpu.itb_walker_cache.ReadReq_hits::total 25827 # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 28142 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 28142 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 28142 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 28142 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10689 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 10689 # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10689 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 10689 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10689 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 10689 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 118046500 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 118046500 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 118046500 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total 118046500 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 118046500 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total 118046500 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 38829 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 38829 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25829 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::total 25829 # number of demand (read+write) hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25829 # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::total 25829 # number of overall hits
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10616 # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::total 10616 # number of ReadReq misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10616 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::total 10616 # number of demand (read+write) misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10616 # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::total 10616 # number of overall misses
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 119043500 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total 119043500 # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 119043500 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total 119043500 # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 119043500 # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total 119043500 # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 36443 # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::total 36443 # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 38831 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 38831 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 38831 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 38831 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.275284 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.275284 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.275270 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.275270 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.275270 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.275270 # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11043.736552 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11043.736552 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11043.736552 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11043.736552 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11043.736552 # average overall miss latency
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 36445 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::total 36445 # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36445 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::total 36445 # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.291304 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.291304 # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.291288 # miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_miss_rate::total 0.291288 # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.291288 # miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_miss_rate::total 0.291288 # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11213.592690 # average ReadReq miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11213.592690 # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11213.592690 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11213.592690 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11213.592690 # average overall miss latency
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 1993 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 1993 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10689 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10689 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10689 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 10689 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10689 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 10689 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 96668500 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 96668500 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 96668500 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 96668500 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 96668500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 96668500 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.275284 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.275284 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.275270 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.275270 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.275270 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9043.736552 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9043.736552 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9043.736552 # average overall mshr miss latency
+system.cpu.itb_walker_cache.writebacks::writebacks 2031 # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total 2031 # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10616 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10616 # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10616 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total 10616 # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10616 # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total 10616 # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97811500 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 97811500 # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 97811500 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 97811500 # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 97811500 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 97811500 # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.291304 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.291304 # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.291288 # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.291288 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.291288 # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9213.592690 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9213.592690 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9213.592690 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.replacements 108113 # number of replacements
-system.cpu.dtb_walker_cache.tagsinuse 13.301181 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.total_refs 134692 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.sampled_refs 108129 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.avg_refs 1.245660 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.warmup_cycle 5100502305500 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.301181 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.831324 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.occ_percent::total 0.831324 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 134692 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 134692 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 134692 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 134692 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 134692 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 134692 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 109183 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 109183 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 109183 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 109183 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 109183 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 109183 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1366356000 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1366356000 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1366356000 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 1366356000 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1366356000 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 1366356000 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 243875 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 243875 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 243875 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 243875 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 243875 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 243875 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.447701 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.447701 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.447701 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.447701 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.447701 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.447701 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12514.365790 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12514.365790 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12514.365790 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12514.365790 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12514.365790 # average overall miss latency
+system.cpu.dtb_walker_cache.replacements 109067 # number of replacements
+system.cpu.dtb_walker_cache.tagsinuse 12.961436 # Cycle average of tags in use
+system.cpu.dtb_walker_cache.total_refs 135080 # Total number of references to valid blocks.
+system.cpu.dtb_walker_cache.sampled_refs 109080 # Sample count of references to valid blocks.
+system.cpu.dtb_walker_cache.avg_refs 1.238357 # Average number of references to valid blocks.
+system.cpu.dtb_walker_cache.warmup_cycle 5099784110000 # Cycle when the warmup percentage was hit.
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.961436 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.810090 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total 0.810090 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135158 # number of ReadReq hits
+system.cpu.dtb_walker_cache.ReadReq_hits::total 135158 # number of ReadReq hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135158 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::total 135158 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135158 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::total 135158 # number of overall hits
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110111 # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::total 110111 # number of ReadReq misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110111 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::total 110111 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110111 # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::total 110111 # number of overall misses
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1384932000 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1384932000 # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1384932000 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total 1384932000 # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1384932000 # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total 1384932000 # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 245269 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::total 245269 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 245269 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::total 245269 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 245269 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::total 245269 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.448940 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.448940 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.448940 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::total 0.448940 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.448940 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::total 0.448940 # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12577.598968 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12577.598968 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12577.598968 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12577.598968 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12577.598968 # average overall miss latency
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 35577 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 35577 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 109183 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 109183 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 109183 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 109183 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 109183 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 109183 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1147990000 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1147990000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1147990000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1147990000 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.447701 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.447701 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.447701 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.447701 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10514.365790 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10514.365790 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10514.365790 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.writebacks::writebacks 36570 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total 36570 # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110111 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110111 # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110111 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total 110111 # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110111 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total 110111 # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1164710000 # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1164710000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1164710000 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1164710000 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.448940 # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.448940 # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.448940 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.448940 # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10577.598968 # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10577.598968 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10577.598968 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1659590 # number of replacements
-system.cpu.dcache.tagsinuse 511.997640 # Cycle average of tags in use
-system.cpu.dcache.total_refs 19085008 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1660102 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 11.496286 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 1659765 # number of replacements
+system.cpu.dcache.tagsinuse 511.990842 # Cycle average of tags in use
+system.cpu.dcache.total_refs 19082473 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1660277 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 11.493548 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 27985000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.997640 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 10993134 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 10993134 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8086930 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8086930 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 19080064 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 19080064 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 19080064 # number of overall hits
-system.cpu.dcache.overall_hits::total 19080064 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2235074 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2235074 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 318068 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 318068 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2553142 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2553142 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2553142 # number of overall misses
-system.cpu.dcache.overall_misses::total 2553142 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 32122708000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 32122708000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 9628285992 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 9628285992 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 41750993992 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 41750993992 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 41750993992 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 41750993992 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 13228208 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13228208 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8404998 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8404998 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21633206 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21633206 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21633206 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21633206 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168963 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.168963 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037843 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.118020 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.118020 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.118020 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.118020 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14372.100432 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14372.100432 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30271.155828 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30271.155828 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16352.789618 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16352.789618 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16352.789618 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16352.789618 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 398716 # number of cycles access was blocked
+system.cpu.dcache.occ_blocks::cpu.data 511.990842 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999982 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999982 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 10992813 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 10992813 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8084535 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8084535 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 19077348 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 19077348 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 19077348 # number of overall hits
+system.cpu.dcache.overall_hits::total 19077348 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2235315 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2235315 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 318075 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 318075 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2553390 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2553390 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2553390 # number of overall misses
+system.cpu.dcache.overall_misses::total 2553390 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 32075751500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 32075751500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 9669659497 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 9669659497 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 41745410997 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 41745410997 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 41745410997 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 41745410997 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 13228128 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13228128 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 8402610 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8402610 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 21630738 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 21630738 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 21630738 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 21630738 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.168982 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.168982 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037854 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.037854 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.118045 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.118045 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.118045 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.118045 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14349.544248 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14349.544248 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30400.564323 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30400.564323 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16349.014838 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16349.014838 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16349.014838 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 385443 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 42426 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 42285 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.397916 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.115360 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1560986 # number of writebacks
-system.cpu.dcache.writebacks::total 1560986 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863566 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 863566 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 25004 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 25004 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 888570 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 888570 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 888570 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 888570 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371508 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1371508 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293064 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 293064 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1664572 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1664572 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1664572 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1664572 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17458468000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17458468000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8785727992 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8785727992 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26244195992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 26244195992 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26244195992 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 26244195992 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97297948500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97297948500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2473076000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2473076000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99771024500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 99771024500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103681 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103681 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034868 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034868 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076945 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.076945 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076945 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.076945 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12729.395673 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12729.395673 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29978.871482 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29978.871482 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15766.332722 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15766.332722 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15766.332722 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15766.332722 # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks 1561573 # number of writebacks
+system.cpu.dcache.writebacks::total 1561573 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 863477 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 863477 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24970 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 24970 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 888447 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 888447 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 888447 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 888447 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371838 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1371838 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 293105 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 293105 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1664943 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1664943 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1664943 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1664943 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17433703000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17433703000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8829680997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8829680997 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26263383997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 26263383997 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26263383997 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 26263383997 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97296997000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97296997000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2470922500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2470922500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99767919500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 99767919500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103706 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103706 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034883 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034883 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.076971 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076971 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.076971 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12708.281153 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12708.281153 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30124.634506 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30124.634506 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15774.344225 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 15774.344225 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 113184 # number of replacements
-system.cpu.l2cache.tagsinuse 64838.652063 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3931021 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 177284 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 22.173580 # Average number of references to valid blocks.
+system.cpu.l2cache.replacements 113143 # number of replacements
+system.cpu.l2cache.tagsinuse 64828.008913 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 3933194 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 177289 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 22.185212 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 50168.170279 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.493195 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.133179 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 3227.427363 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 11429.428047 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.765506 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000206 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::writebacks 50000.769302 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.dtb.walker 10.826981 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.134900 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 3307.164355 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 11509.113375 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.762951 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000165 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.049247 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.174399 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.989359 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 101466 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8114 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 1033385 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1333616 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2476581 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1598556 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1598556 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 335 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 335 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 156370 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 156370 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 101466 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 8114 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 1033385 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1489986 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2632951 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 101466 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 8114 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 1033385 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1489986 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2632951 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 53 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 16850 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 36691 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 53601 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 3625 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 3625 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 132809 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 132809 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 53 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst 16850 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 169500 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 186410 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.dtb.walker 53 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst 16850 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 169500 # number of overall misses
-system.cpu.l2cache.overall_misses::total 186410 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 4666500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 459000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1174285000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2521513999 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 3700924499 # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17158500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 17158500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6838563000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 6838563000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 4666500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 459000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 1174285000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 9360076999 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 10539487499 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 4666500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 459000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 1174285000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 9360076999 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 10539487499 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 101519 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8121 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 1050235 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 1370307 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 2530182 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1598556 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1598556 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3960 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 3960 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 289179 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 289179 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.dtb.walker 101519 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.itb.walker 8121 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst 1050235 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1659486 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 2819361 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.dtb.walker 101519 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.itb.walker 8121 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 1050235 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1659486 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 2819361 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000522 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000862 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016044 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026776 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.021185 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.915404 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.915404 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.459262 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.459262 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000522 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000862 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016044 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.102140 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.066118 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000522 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000862 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016044 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.102140 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.066118 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 88047.169811 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 65571.428571 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69690.504451 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68722.956556 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 69045.810694 # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4733.379310 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4733.379310 # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51491.713664 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51491.713664 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 88047.169811 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 65571.428571 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69690.504451 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55221.693209 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 56539.281686 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 88047.169811 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 65571.428571 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69690.504451 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55221.693209 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 56539.281686 # average overall miss latency
+system.cpu.l2cache.occ_percent::cpu.inst 0.050463 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.175615 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.989197 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 102962 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8277 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst 1030819 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1333964 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2476022 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1600174 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1600174 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 327 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 327 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 156003 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 156003 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.dtb.walker 102962 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.itb.walker 8277 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst 1030819 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1489967 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2632025 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.dtb.walker 102962 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.itb.walker 8277 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst 1030819 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1489967 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2632025 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst 16851 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 36698 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 53603 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 3825 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 3825 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 133009 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 133009 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst 16851 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 169707 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 186612 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst 16851 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 169707 # number of overall misses
+system.cpu.l2cache.overall_misses::total 186612 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5800000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 389500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1177383500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2492698000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 3676271000 # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16893999 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total 16893999 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6881289000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6881289000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5800000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 389500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 1177383500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 9373987000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 10557560000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5800000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 389500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 1177383500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 9373987000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 10557560000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103010 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8283 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 1047670 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1370662 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 2529625 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1600174 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1600174 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4152 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 4152 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 289012 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 289012 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103010 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.itb.walker 8283 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst 1047670 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1659674 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2818637 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103010 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.itb.walker 8283 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 1047670 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1659674 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2818637 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000466 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000724 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016084 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026774 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.021190 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.921243 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.921243 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.460220 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.460220 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000466 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000724 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016084 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.102253 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.066206 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000466 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000724 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016084 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.102253 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.066206 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 120833.333333 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 64916.666667 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69870.245089 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67924.628045 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 68583.306904 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 4416.731765 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 4416.731765 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51735.514138 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51735.514138 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 120833.333333 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69870.245089 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55236.301390 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 56574.925514 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 120833.333333 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 64916.666667 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69870.245089 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55236.301390 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 56574.925514 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 102512 # number of writebacks
-system.cpu.l2cache.writebacks::total 102512 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
+system.cpu.l2cache.writebacks::writebacks 102813 # number of writebacks
+system.cpu.l2cache.writebacks::total 102813 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 53 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16848 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36690 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 53598 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3625 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 3625 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 132809 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 132809 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 53 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 16848 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 169499 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 186407 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 53 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 16848 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 169499 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 186407 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4003602 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 370512 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964285581 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2065462567 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3034122262 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 37079107 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 37079107 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200762570 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200762570 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4003602 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 370512 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964285581 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7266225137 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 8234884832 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4003602 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 370512 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964285581 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7266225137 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 8234884832 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89188560000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89188560000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2310705000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2310705000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91499265000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91499265000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026775 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021183 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.915404 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.915404 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459262 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459262 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.066117 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000522 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000862 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016042 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102139 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.066117 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57234.424323 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56294.973208 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56608.870891 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10228.719172 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10228.719172 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39159.714854 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39159.714854 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75539.660377 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52930.285714 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57234.424323 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42868.837793 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44176.907691 # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_hits::total 2 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16850 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 36697 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 53601 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3825 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 3825 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133009 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 133009 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 16850 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 169706 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 186610 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 16850 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 169706 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 186610 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5203838 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 314260 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 967803547 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2036732357 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3010054002 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39193303 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39193303 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5240927353 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5240927353 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5203838 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 314260 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 967803547 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277659710 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 8250981355 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5203838 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 314260 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 967803547 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277659710 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 8250981355 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89187688500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89187688500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308713500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308713500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91496402000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91496402000 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026773 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021189 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.921243 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.921243 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.460220 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.460220 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102253 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.066206 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000466 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000724 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016083 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102253 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.066206 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57436.412285 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55501.331362 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56156.676219 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10246.615163 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10246.615163 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39402.802464 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39402.802464 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 108413.291667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52376.666667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57436.412285 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42883.926968 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44215.108274 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/projects/pd/randd/dist/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
-Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:52:06
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 13 2013 11:20:14
+gem5 started Feb 13 2013 14:16:35
+gem5 executing on u200540-lin
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 387279743500 because target called exit()
+Exiting @ tick 387315507500 because target called exit()
sim_ticks 387315507500 # Number of ticks simulated
final_tick 387315507500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 205717 # Simulator instruction rate (inst/s)
-host_op_rate 206366 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56864239 # Simulator tick rate (ticks/s)
-host_mem_usage 235456 # Number of bytes of host memory used
-host_seconds 6811.23 # Real time elapsed on the host
+host_inst_rate 183094 # Simulator instruction rate (inst/s)
+host_op_rate 183671 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 50610731 # Simulator tick rate (ticks/s)
+host_mem_usage 233664 # Number of bytes of host memory used
+host_seconds 7652.83 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 76544 # Number of bytes read from this memory
system.cpu.rename.fp_rename_lookups 34121307 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1244770439 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 111594753 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2643942 # count of serializing insts renamed
+system.cpu.rename.serializingInsts 2643851 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 2663506 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 271777312 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 436941235 # Number of loads inserted to the mem dependence unit.
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
master=system.physmem.port
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:51:04
-gem5 executing on u200540
+gem5 compiled Feb 13 2013 11:38:19
+gem5 started Feb 13 2013 19:20:32
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 206006891000 because target called exit()
+Exiting @ tick 199938942500 because target called exit()
---------- Begin Simulation Statistics ----------
-sim_seconds 0.199960 # Number of seconds simulated
-sim_ticks 199959919500 # Number of ticks simulated
-final_tick 199959919500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.199939 # Number of seconds simulated
+sim_ticks 199938942500 # Number of ticks simulated
+final_tick 199938942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 164124 # Simulator instruction rate (inst/s)
-host_op_rate 185039 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 64955915 # Simulator tick rate (ticks/s)
-host_mem_usage 268876 # Number of bytes of host memory used
-host_seconds 3078.39 # Real time elapsed on the host
+host_inst_rate 131447 # Simulator instruction rate (inst/s)
+host_op_rate 148199 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 52017940 # Simulator tick rate (ticks/s)
+host_mem_usage 267932 # Number of bytes of host memory used
+host_seconds 3843.65 # Real time elapsed on the host
sim_insts 505237723 # Number of instructions simulated
sim_ops 569624283 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 216768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9260800 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9477568 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 216768 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 216768 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6246592 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6246592 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3387 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 144700 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 148087 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97603 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97603 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1084057 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 46313281 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 47397339 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1084057 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1084057 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 31239220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 31239220 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 31239220 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1084057 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 46313281 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 78636559 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 148088 # Total number of read requests seen
-system.physmem.writeReqs 97603 # Total number of write requests seen
-system.physmem.cpureqs 247534 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 9477568 # Total number of bytes read from memory
-system.physmem.bytesWritten 6246592 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 9477568 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6246592 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 77 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 6 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 9156 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 9186 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 9613 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 9851 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 9528 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 9506 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 9385 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 9094 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 9054 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 9284 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 8856 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 9051 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 9215 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 9026 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 9005 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 9201 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 5949 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 5987 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 6274 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 6476 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 6181 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 6228 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 6222 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 6039 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 5973 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 6195 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 5906 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 6101 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 5980 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 5943 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 6048 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 6101 # Track writes on a per bank basis
+system.physmem.bytes_read::cpu.inst 216128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9265536 # Number of bytes read from this memory
+system.physmem.bytes_read::total 9481664 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 216128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 216128 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6247680 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6247680 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3377 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144774 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 148151 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 97620 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 97620 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1080970 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 46341828 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 47422798 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1080970 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1080970 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 31247940 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 31247940 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 31247940 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1080970 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 46341828 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 78670737 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 148152 # Total number of read requests seen
+system.physmem.writeReqs 97620 # Total number of write requests seen
+system.physmem.cpureqs 247838 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 9481664 # Total number of bytes read from memory
+system.physmem.bytesWritten 6247680 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 9481664 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6247680 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 60 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 8 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 9164 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 9182 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 9626 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 9864 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 9514 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 9522 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 9403 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 9088 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 9047 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 9254 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 8851 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 9078 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 9226 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 9035 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 9022 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 9216 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 5948 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 5982 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 6294 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 6479 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 6169 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 6226 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 6230 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 6028 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 5969 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 6184 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 5907 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 6110 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 5994 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 5940 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 6061 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 6099 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1837 # Number of times wr buffer was full causing retry
-system.physmem.totGap 199959894000 # Total gap between requests
+system.physmem.numWrRetry 2058 # Number of times wr buffer was full causing retry
+system.physmem.totGap 199938916500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 148088 # Categorize read packet sizes
+system.physmem.readPktSize::6 148152 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 99440 # categorize write packet sizes
+system.physmem.writePktSize::6 99678 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 6 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 8 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 138077 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 9290 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 558 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 77 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 138002 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 9423 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 574 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4198 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4220 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4225 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4229 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4230 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 4231 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4207 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4224 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4229 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4230 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4232 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 4234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 4235 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 4234 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 46 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 1699469983 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 4970281233 # Sum of mem lat for all requests
-system.physmem.totBusLat 740055000 # Total cycles spent in databus access
-system.physmem.totBankLat 2530756250 # Total cycles spent in bank access
-system.physmem.avgQLat 11482.05 # Average queueing delay per request
-system.physmem.avgBankLat 17098.43 # Average bank access latency per request
+system.physmem.totQLat 1714592809 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 4984530309 # Sum of mem lat for all requests
+system.physmem.totBusLat 740460000 # Total cycles spent in databus access
+system.physmem.totBankLat 2529477500 # Total cycles spent in bank access
+system.physmem.avgQLat 11577.89 # Average queueing delay per request
+system.physmem.avgBankLat 17080.45 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 33580.49 # Average memory access latency
-system.physmem.avgRdBW 47.40 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 31.24 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 47.40 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 31.24 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 33658.34 # Average memory access latency
+system.physmem.avgRdBW 47.42 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 31.25 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 47.42 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 31.25 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.61 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
-system.physmem.avgWrQLen 8.80 # Average write queue length over time
-system.physmem.readRowHits 125322 # Number of row buffer hits during reads
-system.physmem.writeRowHits 52822 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 8.61 # Average write queue length over time
+system.physmem.readRowHits 125391 # Number of row buffer hits during reads
+system.physmem.writeRowHits 52781 # Number of row buffer hits during writes
system.physmem.readRowHitRate 84.67 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 54.12 # Row buffer hit rate for writes
-system.physmem.avgGap 813867.39 # Average gap between requests
-system.cpu.branchPred.lookups 182791909 # Number of BP lookups
-system.cpu.branchPred.condPredicted 143104920 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7263448 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 93100856 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 87211306 # Number of BTB hits
+system.physmem.writeRowHitRate 54.07 # Row buffer hit rate for writes
+system.physmem.avgGap 813513.81 # Average gap between requests
+system.cpu.branchPred.lookups 182822724 # Number of BP lookups
+system.cpu.branchPred.condPredicted 143137315 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 7265727 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 92608245 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 87223668 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 93.674011 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12676660 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 116192 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 94.185640 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 12678241 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 116328 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 548 # Number of system calls
-system.cpu.numCycles 399919840 # number of cpu cycles simulated
+system.cpu.numCycles 399877886 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 119359242 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 761526244 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 182791909 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 99887966 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 170136962 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 35675847 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 75471629 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 650 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 114518172 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2437097 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 392580882 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.175648 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.990337 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 119357295 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 761661117 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 182822724 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 99901909 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 170153225 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 35685967 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 75404786 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 115 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 599 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 52 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 114514980 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2439435 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 392535349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.176247 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.990585 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 222456572 56.67% 56.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 14184957 3.61% 60.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 22893267 5.83% 66.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 22743461 5.79% 71.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 20901253 5.32% 77.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 11599327 2.95% 80.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 13055185 3.33% 83.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 11991563 3.05% 86.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 52755297 13.44% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 222394759 56.66% 56.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 14182729 3.61% 60.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 22889831 5.83% 66.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 22740730 5.79% 71.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 20911778 5.33% 77.22% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 11592313 2.95% 80.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 13064597 3.33% 83.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11995709 3.06% 86.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 52762903 13.44% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 392580882 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.457071 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.904197 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 129017942 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 70989640 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 158833179 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6202041 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 27538080 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 26128135 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 77010 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 825507648 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 295471 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 27538080 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 135602175 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 9653631 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 46459749 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 158272352 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15054895 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 800579867 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 1059 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 3045560 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 8808243 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 238 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 954266949 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 3500439750 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3500438390 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1360 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 392535349 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.457196 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.904734 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 129007067 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 70936891 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 158856890 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 6189241 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 27545260 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 26123752 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 76713 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 825615035 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 296627 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 27545260 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 135587162 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 9629406 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 46470672 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 158288564 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 15014285 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 800671144 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 1118 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 3045263 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 8770685 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 294 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 954443131 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 3500799039 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3500797754 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1285 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 288014658 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2292979 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2292975 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 41576680 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 170252258 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 73485876 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 28570132 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15813364 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 755065776 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3775319 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 665331498 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 1369025 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 187382058 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 479835806 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 797687 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 392580882 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.694763 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.735550 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 288190840 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2292928 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2292926 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 41484095 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 170257556 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 73477240 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 28515126 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 15993211 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 755098791 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 3775279 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 665315698 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 1373206 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 187413888 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 480112879 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 797647 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 392535349 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.694919 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.735704 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 137175345 34.94% 34.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 69848009 17.79% 52.73% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 71421264 18.19% 70.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 53409606 13.60% 84.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 31213744 7.95% 92.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 16052398 4.09% 96.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 8748856 2.23% 98.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 2891239 0.74% 99.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 1820421 0.46% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 137185022 34.95% 34.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 69772643 17.77% 52.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 71446692 18.20% 70.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 53384649 13.60% 84.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 31224067 7.95% 92.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 16072234 4.09% 96.57% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 8725351 2.22% 98.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 2911348 0.74% 99.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 1813343 0.46% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 392580882 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 392535349 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 477908 5.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 6514153 68.18% 73.18% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2562402 26.82% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 479006 5.03% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.03% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 6520016 68.50% 73.53% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 2519109 26.47% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 447790588 67.30% 67.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 383397 0.06% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 447796113 67.31% 67.31% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 383215 0.06% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 96 0.00% 67.36% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 153366793 23.05% 90.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 63790621 9.59% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 153384929 23.05% 90.42% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 63751348 9.58% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 665331498 # Type of FU issued
-system.cpu.iq.rate 1.663662 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 9554463 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014360 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1734167139 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 947029128 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 646060992 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 227 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 304 # Number of floating instruction queue writes
+system.cpu.iq.FU_type_0::total 665315698 # Type of FU issued
+system.cpu.iq.rate 1.663797 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 9518131 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014306 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1734057867 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 947094766 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 646039746 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 286 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 674885846 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 115 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 8559648 # Number of loads that had data forwarded from stores
+system.cpu.iq.int_alu_accesses 674833720 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 8567051 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 44222703 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 41636 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 810061 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 16625399 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 44228001 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 42018 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 810750 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 16616763 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19536 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4374 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19550 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 4420 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 27538080 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5027706 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 374233 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 760399793 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1113000 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 170252258 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 73485876 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 2286777 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 218846 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 12338 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 810061 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 4335774 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4000856 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8336630 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 655910156 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 150087379 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9421342 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 27545260 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 5028428 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 374189 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 760433630 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1111503 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 170257556 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 73477240 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 2286737 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 218401 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 11600 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 810750 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 4335810 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4004416 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8340226 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 655896543 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 150102164 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9419155 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1558698 # number of nop insts executed
-system.cpu.iew.exec_refs 212584480 # number of memory reference insts executed
-system.cpu.iew.exec_branches 138500041 # Number of branches executed
-system.cpu.iew.exec_stores 62497101 # Number of stores executed
-system.cpu.iew.exec_rate 1.640104 # Inst execution rate
-system.cpu.iew.wb_sent 651032473 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 646061008 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 374768785 # num instructions producing a value
-system.cpu.iew.wb_consumers 646479955 # num instructions consuming a value
+system.cpu.iew.exec_nop 1559560 # number of nop insts executed
+system.cpu.iew.exec_refs 212562970 # number of memory reference insts executed
+system.cpu.iew.exec_branches 138503180 # Number of branches executed
+system.cpu.iew.exec_stores 62460806 # Number of stores executed
+system.cpu.iew.exec_rate 1.640242 # Inst execution rate
+system.cpu.iew.wb_sent 651014538 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 646039762 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 374764030 # num instructions producing a value
+system.cpu.iew.wb_consumers 646464296 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.615476 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.579707 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.615593 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.579713 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 189458167 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 189492243 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 7189194 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 365042802 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.564113 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.233409 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 7191710 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 364990089 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.564339 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.233727 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 157342257 43.10% 43.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 98505195 26.98% 70.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 33835922 9.27% 79.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 18767828 5.14% 84.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 16196095 4.44% 88.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7449740 2.04% 90.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 6969572 1.91% 92.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 3172412 0.87% 93.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22803781 6.25% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 157311546 43.10% 43.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 98505266 26.99% 70.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 33800198 9.26% 79.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 18792030 5.15% 84.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 16182785 4.43% 88.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 7427698 2.04% 90.97% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 6983737 1.91% 92.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 3180269 0.87% 93.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22806560 6.25% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 365042802 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 364990089 # Number of insts commited each cycle
system.cpu.commit.committedInsts 506581607 # Number of instructions committed
system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 470727693 # Number of committed integer instructions.
system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 22803781 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 22806560 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1102658217 # The number of ROB reads
-system.cpu.rob.rob_writes 1548511592 # The number of ROB writes
-system.cpu.timesIdled 308911 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 7338958 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 1102636801 # The number of ROB reads
+system.cpu.rob.rob_writes 1548586887 # The number of ROB writes
+system.cpu.timesIdled 308520 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 7342537 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 505237723 # Number of Instructions Simulated
system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated
-system.cpu.cpi 0.791548 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.791548 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.263347 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.263347 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 3058721385 # number of integer regfile reads
-system.cpu.int_regfile_writes 752002162 # number of integer regfile writes
+system.cpu.cpi 0.791465 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.791465 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.263480 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.263480 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 3058659121 # number of integer regfile reads
+system.cpu.int_regfile_writes 752040834 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 210835812 # number of misc regfile reads
+system.cpu.misc_regfile_reads 210809556 # number of misc regfile reads
system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.icache.replacements 15017 # number of replacements
-system.cpu.icache.tagsinuse 1100.275071 # Cycle average of tags in use
-system.cpu.icache.total_refs 114497128 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 16875 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 6785.014993 # Average number of references to valid blocks.
+system.cpu.icache.replacements 15027 # number of replacements
+system.cpu.icache.tagsinuse 1100.543961 # Cycle average of tags in use
+system.cpu.icache.total_refs 114493839 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 16883 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 6781.605106 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 1100.275071 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.537244 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.537244 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 114497128 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 114497128 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 114497128 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 114497128 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 114497128 # number of overall hits
-system.cpu.icache.overall_hits::total 114497128 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 21044 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 21044 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 21044 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 21044 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 21044 # number of overall misses
-system.cpu.icache.overall_misses::total 21044 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 498168000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 498168000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 498168000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 498168000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 498168000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 498168000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 114518172 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 114518172 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 114518172 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 114518172 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 114518172 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 114518172 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23672.685801 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 23672.685801 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 23672.685801 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23672.685801 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 23672.685801 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 381 # number of cycles access was blocked
+system.cpu.icache.occ_blocks::cpu.inst 1100.543961 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.537375 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.537375 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 114493839 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 114493839 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 114493839 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 114493839 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 114493839 # number of overall hits
+system.cpu.icache.overall_hits::total 114493839 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 21140 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 21140 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 21140 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 21140 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 21140 # number of overall misses
+system.cpu.icache.overall_misses::total 21140 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 516063000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 516063000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 516063000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 516063000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 516063000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 516063000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 114514979 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 114514979 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 114514979 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 114514979 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 114514979 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 114514979 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000185 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.000185 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000185 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.000185 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000185 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.000185 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24411.684011 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 24411.684011 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24411.684011 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 24411.684011 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24411.684011 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 24411.684011 # average overall miss latency
+system.cpu.icache.blocked_cycles::no_mshrs 1240 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 38.100000 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_mshrs 95.384615 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4078 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 4078 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 4078 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 4078 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 4078 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 4078 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16966 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 16966 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 16966 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 16966 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 16966 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 16966 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 370390500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 370390500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 370390500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 370390500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 370390500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 370390500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4173 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 4173 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 4173 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 4173 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 4173 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 4173 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16967 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 16967 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 16967 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 16967 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 16967 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 16967 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375239500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 375239500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375239500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 375239500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375239500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 375239500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21831.339149 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21831.339149 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21831.339149 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 21831.339149 # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22115.842518 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22115.842518 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22115.842518 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 22115.842518 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22115.842518 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 22115.842518 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 115340 # number of replacements
-system.cpu.l2cache.tagsinuse 27103.357438 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1781605 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 146589 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 12.153743 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 100678479000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 23035.141201 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst 363.560333 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 3704.655904 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks 0.702977 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst 0.011095 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.113057 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.827129 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 13475 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 804570 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 818045 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1111113 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1111113 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 86 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 86 # number of UpgradeReq hits
+system.cpu.l2cache.replacements 115403 # number of replacements
+system.cpu.l2cache.tagsinuse 27101.914214 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1781316 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 146660 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 12.145888 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 100667210000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 23032.375893 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 362.137104 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 3707.401217 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.702892 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.011052 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.113141 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.827085 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 13493 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 804348 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 817841 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 1110901 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 1110901 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 76 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 76 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 247517 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 247517 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 13475 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1052087 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 1065562 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 13475 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1052087 # number of overall hits
-system.cpu.l2cache.overall_hits::total 1065562 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 3393 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 43422 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 46815 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 101299 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 101299 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 3393 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 144721 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 148114 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 3393 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 144721 # number of overall misses
-system.cpu.l2cache.overall_misses::total 148114 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 218124500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2897532500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 3115657000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5229658000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5229658000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 218124500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 8127190500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 8345315000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 218124500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 8127190500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 8345315000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 16868 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 847992 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 864860 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks 1111113 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total 1111113 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data 92 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 348816 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 348816 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 16868 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 1196808 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 1213676 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 16868 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 1196808 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 1213676 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201150 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051206 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.054130 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.065217 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.065217 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290408 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 0.290408 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201150 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.120922 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.122038 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201150 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.120922 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.122038 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 64286.619511 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66729.595597 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 66552.536580 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51625.958795 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51625.958795 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 64286.619511 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56157.644709 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 56343.863511 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 64286.619511 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56157.644709 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 56343.863511 # average overall miss latency
+system.cpu.l2cache.demand_hits::cpu.inst 13493 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1051865 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1065358 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 13493 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1051865 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1065358 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3382 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 43483 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 46865 # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 101314 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 101314 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3382 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 144797 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 148179 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3382 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 144797 # number of overall misses
+system.cpu.l2cache.overall_misses::total 148179 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 222786000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2922283500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 3145069500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5216808500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5216808500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 222786000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8139092000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 8361878000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 222786000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 8139092000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 8361878000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 16875 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 847831 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 864706 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1110901 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1110901 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 84 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 348831 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 348831 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 16875 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1196662 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1213537 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 16875 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1196662 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1213537 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200415 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051287 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.054198 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.095238 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.095238 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290439 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.290439 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200415 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.121001 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.122105 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200415 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.121001 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.122105 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65874.039030 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67205.195134 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 67109.132615 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51491.486863 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51491.486863 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65874.039030 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56210.363474 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 56430.924760 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65874.039030 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56210.363474 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 56430.924760 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks 97603 # number of writebacks
-system.cpu.l2cache.writebacks::total 97603 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3388 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43401 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 46789 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101299 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 101299 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 3388 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 144700 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 148088 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 3388 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 144700 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 148088 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175595014 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2357208396 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2532803410 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 60006 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 60006 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3964657000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3964657000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175595014 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6321865396 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 6497460410 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175595014 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6321865396 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 6497460410 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051181 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054100 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.065217 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.065217 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290408 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290408 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.122016 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200854 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120905 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.122016 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 51828.516529 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54312.306076 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54132.454423 # average ReadReq mshr miss latency
+system.cpu.l2cache.writebacks::writebacks 97620 # number of writebacks
+system.cpu.l2cache.writebacks::total 97620 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 23 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 23 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 27 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3378 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43460 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 46838 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101314 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 101314 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3378 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 144774 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 148152 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3378 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 144774 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 148152 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 180238509 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2380789420 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2561027929 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 80008 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 80008 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3951783175 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3951783175 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 180238509 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6332572595 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6512811104 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 180238509 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6332572595 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6512811104 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051260 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054166 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.095238 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.095238 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290439 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290439 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120982 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.122083 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200178 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120982 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.122083 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53356.574600 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54781.164749 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54678.421986 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39138.165234 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39138.165234 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 51828.516529 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43689.463690 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43875.671290 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39005.302081 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39005.302081 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53356.574600 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43741.090216 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 43960.331983 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53356.574600 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43741.090216 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 43960.331983 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1192712 # number of replacements
-system.cpu.dcache.tagsinuse 4058.214665 # Cycle average of tags in use
-system.cpu.dcache.total_refs 190183804 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1196808 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 158.909202 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 1192566 # number of replacements
+system.cpu.dcache.tagsinuse 4058.210701 # Cycle average of tags in use
+system.cpu.dcache.total_refs 190188522 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1196662 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 158.932532 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 4133508000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4058.214665 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.990775 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.990775 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 136214217 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 136214217 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 50991947 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 50991947 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488812 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1488812 # number of LoadLockedReq hits
+system.cpu.dcache.occ_blocks::cpu.data 4058.210701 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.990774 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.990774 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 136218658 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 136218658 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 50992230 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 50992230 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488832 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1488832 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 187206164 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 187206164 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 187206164 # number of overall hits
-system.cpu.dcache.overall_hits::total 187206164 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1696297 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1696297 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3247359 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3247359 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 187210888 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 187210888 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 187210888 # number of overall hits
+system.cpu.dcache.overall_hits::total 187210888 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1698471 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1698471 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3247076 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3247076 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 4943656 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4943656 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4943656 # number of overall misses
-system.cpu.dcache.overall_misses::total 4943656 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 26545297500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 26545297500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57237294950 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57237294950 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 659000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 659000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 83782592450 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 83782592450 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 83782592450 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 83782592450 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 137910514 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 137910514 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data 4945547 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4945547 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4945547 # number of overall misses
+system.cpu.dcache.overall_misses::total 4945547 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 26682171000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 26682171000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57031810448 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57031810448 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 615500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 615500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 83713981448 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 83713981448 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 83713981448 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 83713981448 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 137917129 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 137917129 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488853 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488853 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488873 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1488873 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 192149820 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 192149820 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 192149820 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 192149820 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012300 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.012300 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059871 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.059871 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 192156435 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 192156435 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 192156435 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 192156435 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012315 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012315 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059866 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.059866 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000028 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000028 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025728 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025728 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025728 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025728 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15648.968017 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15648.968017 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17625.798364 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 17625.798364 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16073.170732 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16073.170732 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 16947.496438 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16947.496438 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 16947.496438 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 18139 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 17902 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1666 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 610 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.887755 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 29.347541 # average number of cycles each access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025737 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025737 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025737 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025737 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15709.524037 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 15709.524037 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17564.051611 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 17564.051611 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15012.195122 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15012.195122 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16927.143034 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 16927.143034 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16927.143034 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 16927.143034 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 18054 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 15751 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 1648 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 601 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.955097 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 26.207987 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1111113 # number of writebacks
-system.cpu.dcache.writebacks::total 1111113 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 847762 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 847762 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898994 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 2898994 # number of WriteReq MSHR hits
+system.cpu.dcache.writebacks::writebacks 1110901 # number of writebacks
+system.cpu.dcache.writebacks::total 1110901 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 850108 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 850108 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2898693 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2898693 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3746756 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3746756 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3746756 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3746756 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848535 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 848535 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348365 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 348365 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1196900 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1196900 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1196900 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1196900 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11831456500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 11831456500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8103165495 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8103165495 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19934621995 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 19934621995 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19934621995 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 19934621995 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006153 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006153 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data 3748801 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3748801 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3748801 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3748801 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848363 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 848363 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348383 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 348383 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1196746 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1196746 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1196746 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1196746 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11853365500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 11853365500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8090404996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8090404996 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19943770496 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 19943770496 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19943770496 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 19943770496 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006229 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006229 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006229 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13943.392435 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13943.392435 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23260.561466 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23260.561466 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16655.210957 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16655.210957 # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006228 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006228 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006228 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13972.044396 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13972.044396 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23222.731867 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23222.731867 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.998668 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.998668 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.998668 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.998668 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff