+2018-09-06 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ PR target/86731
+ * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Update logic
+ around folding of vec_sl to handle out of range shift values.
+
2018-09-06 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (fix_trunc<mode>_fisttp_i387_1): Remove.
case ALTIVEC_BUILTIN_VSLH:
case ALTIVEC_BUILTIN_VSLW:
case P8V_BUILTIN_VSLD:
- arg0 = gimple_call_arg (stmt, 0);
- if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
- && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
- return false;
- arg1 = gimple_call_arg (stmt, 1);
- lhs = gimple_call_lhs (stmt);
- g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
- gimple_set_location (g, gimple_location (stmt));
- gsi_replace (gsi, g, true);
- return true;
+ {
+ location_t loc;
+ gimple_seq stmts = NULL;
+ arg0 = gimple_call_arg (stmt, 0);
+ tree arg0_type = TREE_TYPE (arg0);
+ if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
+ && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
+ return false;
+ arg1 = gimple_call_arg (stmt, 1);
+ tree arg1_type = TREE_TYPE (arg1);
+ tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
+ tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
+ loc = gimple_location (stmt);
+ lhs = gimple_call_lhs (stmt);
+ /* Force arg1 into the range valid matching the arg0 type. */
+ /* Build a vector consisting of the max valid bit-size values. */
+ int n_elts = VECTOR_CST_NELTS (arg1);
+ int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
+ * BITS_PER_UNIT;
+ tree element_size = build_int_cst (unsigned_element_type,
+ tree_size_in_bits / n_elts);
+ tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
+ for (int i = 0; i < n_elts; i++)
+ elts.safe_push (element_size);
+ tree modulo_tree = elts.build ();
+ /* Modulo the provided shift value against that vector. */
+ tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
+ unsigned_arg1_type, arg1);
+ tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
+ unsigned_arg1_type, unsigned_arg1,
+ modulo_tree);
+ gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+ /* And finally, do the shift. */
+ g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
/* Flavors of vector shift right. */
case ALTIVEC_BUILTIN_VSRB:
case ALTIVEC_BUILTIN_VSRH:
+2018-09-06 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ PR target/86731
+ * gcc.target/powerpc/pr86731.c: New test.
+ * gcc.target/powerpc/pr86731-longlong.c: New test.
+ * gcc.target/powerpc/pr86731-fwrapv.c: New test.
+ * gcc.target/powerpc/pr86731-fwrapv-longlong.c: New test.
+ * gcc.target/powerpc/pr86731-nogimplefold.c: New test.
+ * gcc.target/powerpc/pr86731-nogimplefold-longlong.c: New test.
+
2018-09-06 Ilya Leoshkevich <iii@linux.ibm.com>
PR target/80080
--- /dev/null
+/* PR86731. Verify that the rs6000 gimple-folding code handles the
+ left shift operation properly. This is a testcase variation that
+ explicitly specifies -fwrapv, which is a condition for the
+ gimple folding of the vec_sl() intrinsic. */
+
+/* specify -mpower8-vector, which provides vec_sl(long long,...) support. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-maltivec -O3 -fwrapv -mpower8-vector " } */
+
+#include <altivec.h>
+
+vector unsigned long long splatu4(void)
+{
+ vector unsigned long long mzero = {-1,-1};
+ return (vector unsigned long long) vec_sl(mzero, mzero);
+}
+
+vector signed long long splats4(void)
+{
+ vector unsigned long long mzero = {-1,-1};
+ return (vector signed long long) vec_sl(mzero, mzero);
+}
+
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
+
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxv\M|\mlxvd2x\M} 2 } } */
+
--- /dev/null
+/* PR86731. Verify that the rs6000 gimple-folding code handles the
+ left shift operation properly. This is a testcase variation that
+ explicitly specifies -fwrapv, which is a condition for the
+ gimple folding of the vec_sl() intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-maltivec -O3 -fwrapv " } */
+
+#include <altivec.h>
+/* original test as reported. */
+vector unsigned int splat(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector unsigned int) vec_sl(mzero, mzero);
+}
+
+/* more testcase variations. */
+vector unsigned char splatu1(void)
+{
+ vector unsigned char mzero = vec_splat_u8(-1);
+ return (vector unsigned char) vec_sl(mzero, mzero);
+}
+
+vector unsigned short splatu2(void)
+{
+ vector unsigned short mzero = vec_splat_u16(-1);
+ return (vector unsigned short) vec_sl(mzero, mzero);
+}
+
+vector unsigned int splatu3(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector unsigned int) vec_sl(mzero, mzero);
+}
+
+vector signed char splats1(void)
+{
+ vector unsigned char mzero = vec_splat_u8(-1);
+ return (vector signed char) vec_sl(mzero, mzero);
+}
+
+vector signed short splats2(void)
+{
+ vector unsigned short mzero = vec_splat_u16(-1);
+ return (vector signed short) vec_sl(mzero, mzero);
+}
+
+vector signed int splats3(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector signed int) vec_sl(mzero, mzero);
+}
+
+/* Codegen will consist of splat and shift instructions.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
+
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 0 } } */
+
--- /dev/null
+/* PR86731. Verify that the rs6000 gimple-folding code handles the
+ left shift properly. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-maltivec -O3 -mpower8-vector " } */
+
+#include <altivec.h>
+
+vector unsigned long long splatu4(void)
+{
+ vector unsigned long long mzero = {-1,-1};
+ return (vector unsigned long long) vec_sl(mzero, mzero);
+}
+vector signed long long splats4(void)
+{
+ vector unsigned long long mzero = {-1,-1};
+ return (vector signed long long) vec_sl(mzero, mzero);
+}
+
+/* Codegen will consist of splat and shift instructions for most types.
+ Noted variations: if gimple folding is disabled, or if -fwrapv is not
+ specified, the long long tests will generate a vspltisw+vsld pair,
+ versus generating a single lvx. */
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 } } */
+
--- /dev/null
+/* PR86731. Verify that the rs6000 gimple-folding code handles the
+ left shift operation properly. This is a testcase variation that
+ explicitly disables gimple folding. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-maltivec -O3 -fwrapv -mno-fold-gimple -mpower8-vector " } */
+/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
+
+
+#include <altivec.h>
+
+vector unsigned long long splatu4(void)
+{
+ vector unsigned long long mzero = {-1,-1};
+ return (vector unsigned long long) vec_sl(mzero, mzero);
+}
+
+vector signed long long splats4(void)
+{
+ vector unsigned long long mzero = {-1,-1};
+ return (vector signed long long) vec_sl(mzero, mzero);
+}
+
+/* Codegen will consist of splat and shift instructions for most types.
+ Noted variations: if gimple folding is disabled, or if -fwrapv is not specified, the
+ long long tests will generate a vspltisw+vsld pair, versus generating a lvx. */
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 } } */
+
--- /dev/null
+/* PR86731. Verify that the rs6000 gimple-folding code handles the
+ left shift operation properly. This is a testcase variation that
+ explicitly disables gimple folding. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-maltivec -O3 -fwrapv -mno-fold-gimple" } */
+/* { dg-prune-output "gimple folding of rs6000 builtins has been disabled." } */
+
+
+#include <altivec.h>
+/* original test as reported. */
+vector unsigned int splat(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector unsigned int) vec_sl(mzero, mzero);
+}
+
+/* more testcase variations. */
+vector unsigned char splatu1(void)
+{
+ vector unsigned char mzero = vec_splat_u8(-1);
+ return (vector unsigned char) vec_sl(mzero, mzero);
+}
+
+vector unsigned short splatu2(void)
+{
+ vector unsigned short mzero = vec_splat_u16(-1);
+ return (vector unsigned short) vec_sl(mzero, mzero);
+}
+
+vector unsigned int splatu3(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector unsigned int) vec_sl(mzero, mzero);
+}
+
+vector signed char splats1(void)
+{
+ vector unsigned char mzero = vec_splat_u8(-1);
+ return (vector signed char) vec_sl(mzero, mzero);
+}
+
+vector signed short splats2(void)
+{
+ vector unsigned short mzero = vec_splat_u16(-1);
+ return (vector signed short) vec_sl(mzero, mzero);
+}
+
+vector signed int splats3(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector signed int) vec_sl(mzero, mzero);
+}
+
+/* Codegen will consist of splat and shift instructions for most types.
+ Noted variations: if gimple folding is disabled, or if -fwrapv is not specified, the
+ long long tests will generate a vspltisw+vsld pair, versus generating a lvx. */
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 } } */
+
--- /dev/null
+/* PR86731. Verify that the rs6000 gimple-folding code handles the
+ left shift properly. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-maltivec -O3" } */
+
+#include <altivec.h>
+/* The original test as reported. */
+vector unsigned int splat(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector unsigned int) vec_sl(mzero, mzero);
+}
+
+/* more testcase variations. */
+vector unsigned char splatu1(void)
+{
+ vector unsigned char mzero = vec_splat_u8(-1);
+ return (vector unsigned char) vec_sl(mzero, mzero);
+}
+
+vector unsigned short splatu2(void)
+{
+ vector unsigned short mzero = vec_splat_u16(-1);
+ return (vector unsigned short) vec_sl(mzero, mzero);
+}
+
+vector unsigned int splatu3(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector unsigned int) vec_sl(mzero, mzero);
+}
+
+vector signed char splats1(void)
+{
+ vector unsigned char mzero = vec_splat_u8(-1);
+ return (vector signed char) vec_sl(mzero, mzero);
+}
+
+vector signed short splats2(void)
+{
+ vector unsigned short mzero = vec_splat_u16(-1);
+ return (vector signed short) vec_sl(mzero, mzero);
+}
+
+vector signed int splats3(void)
+{
+ vector unsigned int mzero = vec_splat_u32(-1);
+ return (vector signed int) vec_sl(mzero, mzero);
+}
+
+/* Codegen will consist of splat and shift instructions for most types.
+ Noted variations: if gimple folding is disabled, or if -fwrapv is not
+ specified, the long long tests will generate a vspltisw+vsld pair,
+ versus generating a single lvx. */
+/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 } } */
+/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 } } */
+/* { dg-final { scan-assembler-times {\mlvx\M} 0 } } */
+
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