i965: Combine offset/texture_offset fields.

texture_offset was only used by some texturing operations, and offset
was only used by spill/unspill and some URB operations. These fields are
never used at the same time.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index 5fdbf4639841cf5ca3e2795c9100a3c446a4a22c..b1c433e45c7ddae53d13cc0cd8f9dfe87287b0fd 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -157,7 +157,7 @@ instructions_match(fs_inst *a, fs_inst *b)
           a->conditional_mod == b->conditional_mod &&
           a->dst.type == b->dst.type &&
           a->sources == b->sources &&
-          (a->is_tex() ? (a->texture_offset == b->texture_offset &&
+          (a->is_tex() ? (a->offset == b->offset &&
                           a->mlen == b->mlen &&
                           a->regs_written == b->regs_written &&
                           a->base_mrf == b->base_mrf &&

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 0622b0740c92750722ced0782b969521e408bd4c..3b9bfe48df321a2fe4fb8c62a461fcc4c6104cff 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -556,7 +556,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
     * Otherwise, we can use an implied move from g0 to the first message reg.
     */
    if (inst->header_present) {
-      if (brw->gen < 6 && !inst->texture_offset) {
+      if (brw->gen < 6 && !inst->offset) {
          /* Set up an implied move from g0 to the MRF. */
          src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
       } else {
@@ -575,10 +575,10 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src
          /* Explicitly set up the message header by copying g0 to the MRF. */
          brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
 
-         if (inst->texture_offset) {
+         if (inst->offset) {
             /* Set the offset bits in DWord 2. */
             brw_MOV(p, get_element_ud(header_reg, 2),
-                       brw_imm_ud(inst->texture_offset));
+                       brw_imm_ud(inst->offset));
          }
 
          brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 4e1badda21f9e741fa86e20626bc735e27abe5a0..21334a25599dc08d5e56aaaaee17df9a3d2712a7 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1918,10 +1918,10 @@ fs_visitor::emit_texture(ir_texture_opcode op,
       inst->shadow_compare = true;
 
    if (offset_value.file == IMM)
-      inst->texture_offset = offset_value.fixed_hw_reg.dw1.ud;
+      inst->offset = offset_value.fixed_hw_reg.dw1.ud;
 
    if (op == ir_tg4) {
-      inst->texture_offset |=
+      inst->offset |=
          gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
 
       if (brw->gen == 6)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 94db98702b9f32e4282f425e0eda806f1e1b61ca..32460e233b9f680b8ce396f74c76f827ad0fe823 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -112,8 +112,7 @@ struct backend_instruction {
    const char *annotation;
    /** @} */
 
-   uint32_t texture_offset; /**< Texture offset bitfield */
-   uint32_t offset; /**< spill/unspill offset */
+   uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
    uint8_t mlen; /**< SEND message length */
    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
    uint8_t target; /**< MRT target. */

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index e52256738121d41531f351e0281c68589592ac1a..0776a91745619240c436c2ea4cbc9c0e26c9b3d8 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -319,7 +319,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
     * use an implied move from g0 to the first message register.
     */
    if (inst->header_present) {
-      if (brw->gen < 6 && !inst->texture_offset) {
+      if (brw->gen < 6 && !inst->offset) {
          /* Set up an implied move from g0 to the MRF. */
          src = brw_vec8_grf(0, 0);
       } else {
@@ -333,10 +333,10 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 
          brw_set_default_access_mode(p, BRW_ALIGN_1);
 
-         if (inst->texture_offset) {
+         if (inst->offset) {
             /* Set the texel offset bits in DWord 2. */
             brw_MOV(p, get_element_ud(header, 2),
-                    brw_imm_ud(inst->texture_offset));
+                    brw_imm_ud(inst->offset));
          }
 
          brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index af7ca0c2ead31075af6d957ff5709fab6dbc34bc..7d4bf5501ffaa81a8ecc24a29513935c2f59539e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -46,7 +46,6 @@ vec4_instruction::vec4_instruction(vec4_visitor *v,
    this->no_dd_check = false;
    this->writes_accumulator = false;
    this->conditional_mod = BRW_CONDITIONAL_NONE;
-   this->texture_offset = 0;
    this->target = 0;
    this->shadow_compare = false;
    this->ir = v->base_ir;
@@ -2468,14 +2467,14 @@ vec4_visitor::visit(ir_texture *ir)
    vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, opcode);
 
    if (ir->offset != NULL && !has_nonconstant_offset) {
-      inst->texture_offset =
+      inst->offset =
          brw_texture_offset(ctx, ir->offset->as_constant()->value.i,
                             ir->offset->type->vector_elements);
    }
 
    /* Stuff the channel select bits in the top of the texture offset */
    if (ir->op == ir_tg4)
-      inst->texture_offset |= gather_channel(ir, sampler) << 16;
+      inst->offset |= gather_channel(ir, sampler) << 16;
 
    /* The message header is necessary for:
     * - Gen4 (always)
@@ -2484,7 +2483,7 @@ vec4_visitor::visit(ir_texture *ir)
     * - Sampler indices too large to fit in a 4-bit value.
     */
    inst->header_present =
-      brw->gen < 5 || inst->texture_offset != 0 || ir->op == ir_tg4 ||
+      brw->gen < 5 || inst->offset != 0 || ir->op == ir_tg4 ||
       is_high_sampler(brw, sampler_reg);
    inst->base_mrf = 2;
    inst->mlen = inst->header_present + 1; /* always at least one */