struct ir3_kernel *ir3_kernel = to_ir3_kernel(kernel);
struct ir3_shader_variant *v = ir3_kernel->v;
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t base = const_state->offsets.immediate;
int size = const_state->immediates_count;
/* to calculate the byte offset (yes, uggg) we need (up to) three
* const values to know the bytes per pixel, and y and z stride:
*/
- struct ir3_const_state *const_state = &ctx->so->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
unsigned cb = regid(const_state->offsets.image_dims, 0) +
const_state->image_dims.off[index];
{
/* first four vec4 sysval's reserved for UBOs: */
/* NOTE: dp is in scalar, but there can be >4 dp components: */
- struct ir3_const_state *const_state = &ctx->so->shader->const_state;
+ struct ir3_const_state *const_state = ir3_const_state(ctx->so);
unsigned n = const_state->offsets.driver_param;
unsigned r = regid(n + dp / 4, dp % 4);
return create_uniform(ctx->block, r);
{
struct ir3_block *b = ctx->block;
struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
- struct ir3_const_state *const_state = &ctx->so->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
unsigned ubo = regid(const_state->offsets.ubo, 0);
const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
struct ir3_instruction **dst)
{
/* SSBO size stored as a const starting at ssbo_sizes: */
- struct ir3_const_state *const_state = &ctx->so->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
unsigned blk_idx = nir_src_as_uint(intr->src[0]);
unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
const_state->ssbo_size.off[blk_idx];
* bytes-per-pixel should have been emitted in 2nd slot of
* image_dims. See ir3_shader::emit_image_dims().
*/
- struct ir3_const_state *const_state = &ctx->so->shader->const_state;
+ const struct ir3_const_state *const_state =
+ ir3_const_state(ctx->so);
unsigned cb = regid(const_state->offsets.image_dims, 0) +
const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
struct ir3_instruction *aux = create_uniform(b, cb + 1);
dst = NULL;
}
- const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
- const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
+ const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
+ const unsigned primitive_param = const_state->offsets.primitive_param * 4;
+ const unsigned primitive_map = const_state->offsets.primitive_map * 4;
switch (intr->intrinsic) {
case nir_intrinsic_load_uniform:
* stripped out in the backend.
*/
for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
- struct ir3_const_state *const_state = &ctx->so->shader->const_state;
+ const struct ir3_const_state *const_state =
+ ir3_const_state(ctx->so);
unsigned stride = strmout->stride[i];
struct ir3_instruction *base, *off;
}
/* Reallocate for 4 more elements whenever it's necessary */
- struct ir3_const_state *const_state = &ctx->so->shader->const_state;
+ struct ir3_const_state *const_state = ir3_const_state(ctx->so);
if (const_state->immediate_idx == const_state->immediates_size * 4) {
const_state->immediates_size += 4;
const_state->immediates = realloc (const_state->immediates,
static void add_const(unsigned reg, unsigned c0, unsigned c1, unsigned c2, unsigned c3)
{
- struct ir3_const_state *const_state = &variant->shader->const_state;
+ struct ir3_const_state *const_state = ir3_const_state(variant);
assert((reg & 0x7) == 0);
int idx = reg >> (1 + 2); /* low bit is half vs full, next two bits are swiz */
if (const_state->immediate_idx == const_state->immediates_size * 4) {
fprintf(out, "\n");
}
- struct ir3_const_state *const_state = &so->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(so);
for (i = 0; i < const_state->immediates_count; i++) {
fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
struct ir3_shader_key key_mask;
};
+static inline struct ir3_const_state *
+ir3_const_state(const struct ir3_shader_variant *v)
+{
+ return &v->shader->const_state;
+}
+
void * ir3_shader_assemble(struct ir3_shader_variant *v);
struct ir3_shader_variant * ir3_shader_get_variant(struct ir3_shader *shader,
struct ir3_shader_key *key, bool binning_pass, bool *created);
/* emit immediates */
- const struct ir3_const_state *const_state = &xs->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(xs);
uint32_t base = const_state->offsets.immediate;
int size = const_state->immediates_count;
tu6_emit_link_map(struct tu_cs *cs,
const struct ir3_shader_variant *producer,
const struct ir3_shader_variant *consumer) {
- const struct ir3_const_state *const_state = &consumer->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(consumer);
uint32_t base = const_state->offsets.primitive_map;
uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
num_loc = ir3_link_geometry_stages(producer, consumer, patch_locs);
0,
0,
};
- uint32_t vs_base = vs->shader->const_state.offsets.primitive_param;
+ uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param;
tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0,
ARRAY_SIZE(params), params);
- uint32_t gs_base = gs->shader->const_state.offsets.primitive_param;
+ uint32_t gs_base = ir3_const_state(gs)->offsets.primitive_param;
tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0,
ARRAY_SIZE(params), params);
}
struct ir3_shader_variant *v)
{
link->ubo_state = v->shader->ubo_state;
- link->const_state = v->shader->const_state;
+ link->const_state = *ir3_const_state(v);
link->constlen = v->constlen;
link->push_consts = shader->push_consts;
}
emit_tess_bos(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_shader_variant *s)
{
struct fd_context *ctx = emit->ctx;
- const unsigned regid = s->shader->const_state.offsets.primitive_param * 4 + 4;
+ const struct ir3_const_state *const_state = ir3_const_state(s);
+ const unsigned regid = const_state->offsets.primitive_param * 4 + 4;
uint32_t dwords = 16;
OUT_PKT7(ring, fd6_stage2opcode(s->type), 3);
emit_stage_tess_consts(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
uint32_t *params, int num_params)
{
- const unsigned regid = v->shader->const_state.offsets.primitive_param;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
+ const unsigned regid = const_state->offsets.primitive_param;
int size = MIN2(1 + regid, v->constlen) - regid;
if (size > 0)
fd6_emit_const(ring, v->type, regid * 4, 0, num_params, params, NULL);
ir3_emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
{
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.ubo;
if (v->constlen > offset) {
uint32_t params = const_state->num_ubos;
ir3_emit_ssbo_sizes(struct fd_screen *screen, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring, struct fd_shaderbuf_stateobj *sb)
{
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.ssbo_sizes;
if (v->constlen > offset) {
uint32_t sizes[align(const_state->ssbo_size.count, 4)];
ir3_emit_image_dims(struct fd_screen *screen, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring, struct fd_shaderimg_stateobj *si)
{
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.image_dims;
if (v->constlen > offset) {
uint32_t dims[align(const_state->image_dims.count, 4)];
ir3_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v,
struct fd_ringbuffer *ring)
{
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t base = const_state->offsets.immediate;
int size = const_state->immediates_count;
const struct ir3_shader_variant *producer,
const struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
{
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t base = const_state->offsets.primitive_map;
uint32_t patch_locs[MAX_VARYING] = { }, num_loc;
struct fd_ringbuffer *ring)
{
/* streamout addresses after driver-params: */
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.tfbo;
if (v->constlen > offset) {
struct fd_streamout_stateobj *so = &ctx->streamout;
static inline bool
ir3_needs_vs_driver_params(const struct ir3_shader_variant *v)
{
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.driver_param;
return v->constlen > offset;
{
debug_assert(ir3_needs_vs_driver_params(v));
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.driver_param;
uint32_t vertex_params[IR3_DP_VS_COUNT] = {
[IR3_DP_VTXID_BASE] = info->index_size ?
emit_common_consts(v, ring, ctx, PIPE_SHADER_COMPUTE);
/* emit compute-shader driver-params: */
- const struct ir3_const_state *const_state = &v->shader->const_state;
+ const struct ir3_const_state *const_state = ir3_const_state(v);
uint32_t offset = const_state->offsets.driver_param;
if (v->constlen > offset) {
ring_wfi(ctx->batch, ring);