platforms: add default_clk_freq/default_clk_name (to use it on simple designs to...

diff --git a/mibuild/platforms/apf27.py b/mibuild/platforms/apf27.py
index 048b857b15140794124a8500dfc95b4b12c3fc82..3490c1c4c58036e53b7d863cbd6f5732d683066a 100644 (file)
--- a/mibuild/platforms/apf27.py
+++ b/mibuild/platforms/apf27.py
@@ -142,6 +142,8 @@ _connectors = [
 ]
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk0"
+       default_clk_period = 10
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
                        lambda p: SimpleCRG(p, "clk0", None), _connectors)

diff --git a/mibuild/platforms/apf51.py b/mibuild/platforms/apf51.py
index e15eb27a8510b6b2542a1a749085cd7583c8f39c..2f7f92d601d63d3966c00f78659e4c7bcfddfd62 100644 (file)
--- a/mibuild/platforms/apf51.py
+++ b/mibuild/platforms/apf51.py
@@ -169,6 +169,8 @@ _connectors = [
 ]
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk3"
+       default_clk_period = 10.526
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios,
                        lambda p: SimpleCRG(p, "clk3", None), _connectors)

diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py
index d0c990469d697a0e46059e2868b6d3c9899c45f1..4cab4b9cc93477f19dfeec64c1ae0f09ddfcf8e0 100644 (file)
--- a/mibuild/platforms/de0nano.py
+++ b/mibuild/platforms/de0nano.py
@@ -92,6 +92,8 @@ _io = [
 ]
 
 class Platform(AlteraQuartusPlatform):
+       default_clk_name = "clk50"
+       default_clk_period = 20
        def __init__(self):
                AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io,
                        lambda p: SimpleCRG(p, "clk50", None))

diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index 1deab34a998339f54d3cc002ad44e51b91b71c92..528a187de83f16c96d0c8885feb2614de70d0af7 100644 (file)
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -348,6 +348,8 @@ def Platform(*args, toolchain="vivado", **kwargs):
                raise ValueError
 
        class RealPlatform(xilinx_platform):
+               default_clk_name = "clk156"
+               default_clk_period = 6.4
                bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
 
                def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):

diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py
index a46d6319d6534f83fbaf85ef5c99b7a58061bbf6..8dbf01e86fa889bc4fc7e24768a28540490e9d31 100644 (file)
--- a/mibuild/platforms/lx9_microboard.py
+++ b/mibuild/platforms/lx9_microboard.py
@@ -103,6 +103,8 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk_y3"
+       default_clk_period = 10
        bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
        ise_commands = """
 promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit

diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py
index 37b12cf0c53018b4026e734c05ce5a31b35917fc..cc1b619f58871ad33bf11de749bf0c6847400da0 100644 (file)
--- a/mibuild/platforms/m1.py
+++ b/mibuild/platforms/m1.py
@@ -119,6 +119,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk50"
+       default_clk_period = 20
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
                        lambda p: SimpleCRG(p, "clk50", None))

diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py
index d09f546ae57116a968b8a119e832e615157a510d..df9eac850685baf44799d70359e5d36f44cdfb79 100644 (file)
--- a/mibuild/platforms/mixxeo.py
+++ b/mibuild/platforms/mixxeo.py
@@ -155,6 +155,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk50"
+       default_clk_period = 20
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
                        lambda p: SimpleCRG(p, "clk50", None))

diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py
index f8236800ee9bc1064c4ba9993a0fca65c306099a..3b24ac21db3ad6d8ea7431f3a24578021396940a 100644 (file)
--- a/mibuild/platforms/ml605.py
+++ b/mibuild/platforms/ml605.py
@@ -52,6 +52,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk200"
+       default_clk_period = 5
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
                        lambda p: CRG_DS(p, "clk200", "user_btn"))

diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py
index 823155521d01c92ae145533c2be1cc495a20d887..0ccd8dd11cd3de45110fd3f28b533491292c2a02 100644 (file)
--- a/mibuild/platforms/papilio_pro.py
+++ b/mibuild/platforms/papilio_pro.py
@@ -50,6 +50,8 @@ _connectors = [
 ]
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk32"
+       default_clk_period = 31.25
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
                        lambda p: SimpleCRG(p, "clk32", None), _connectors)

diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py
index f1af075ef5ba5a639efdc84cc9e87c201aef636d..9446305bf5c62a616f1203304a52ddf0362b05d8 100644 (file)
--- a/mibuild/platforms/rhino.py
+++ b/mibuild/platforms/rhino.py
@@ -134,6 +134,8 @@ _io = [
 ]
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk100"
+       default_clk_period = 10
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
                        lambda p: CRG_DS(p, "clk100", "gpio"))

diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py
index 1fb30080b76fd4ae2d3f47712213114749aaafd9..8c826c4fbcc75db5c3b093bc15233ef144bc5c0f 100644 (file)
--- a/mibuild/platforms/usrp_b100.py
+++ b/mibuild/platforms/usrp_b100.py
@@ -114,6 +114,8 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk64"
+       default_clk_period = 15.625
        bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,

diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py
index 2a3e91c6c5ce4a251ccdb128b7706080549b03b0..5604a1f9d73a158517c378affb9cf311526f3990 100644 (file)
--- a/mibuild/platforms/zedboard.py
+++ b/mibuild/platforms/zedboard.py
@@ -138,6 +138,8 @@ _io = [
 
 
 class Platform(XilinxISEPlatform):
+       default_clk_name = "clk100"
+       default_clk_period = 10
        def __init__(self):
                XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io,
                        lambda p: SimpleCRG(p, "clk100", None))

diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py
index 970b1e7d57662c69faf6a49324e7e8c82b337d46..8513f96cfa9ad6d4d558c0e7ca12dd6198e5f748 100644 (file)
--- a/mibuild/platforms/ztex_115d.py
+++ b/mibuild/platforms/ztex_115d.py
@@ -83,6 +83,8 @@ _io = [
 
 class Platform(XilinxISEPlatform):
        def __init__(self):
+               default_clk_name = "clk_if"
+               default_clk_period = 20
                XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
                                lambda p: SimpleCRG(p, "clk_if", "rst"))
                self.add_platform_command("""