rename svp64 bit-reversed LD instructions to not conflict with v3.0B

diff --git a/openpower/isa/svfixedload.mdwn b/openpower/isa/svfixedload.mdwn
index 6272f900ec70e94576442c3dab8d34ec97c2866e..5ff9d2c5bdd825f529dde969b3300ca60935064f 100644 (file)
--- a/openpower/isa/svfixedload.mdwn
+++ b/openpower/isa/svfixedload.mdwn
@@ -6,7 +6,7 @@
 
 SVD-Form
 
-* lbz RT,SVD(RA),RC
+* lbzbr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -23,7 +23,7 @@ Special Registers Altered:
 
 SVD-Form
 
-* lbzu RT,SVD(RA),RC
+* lbzubr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -40,7 +40,7 @@ Special Registers Altered:
 
 SVD-Form
 
-* lhz RT,SVD(RA),RC
+* lhzbr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -57,7 +57,7 @@ Special Registers Altered:
 
 SVD-Form
 
-* lhzu RT,SVD(RA),RC
+* lhzubr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -74,7 +74,7 @@ Special Registers Altered:
 
 SVD-Form
 
-* lha RT,SVD(RA),RC
+* lhabr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -91,7 +91,7 @@ Special Registers Altered:
 
 SVD-Form
 
-* lhau RT,SVD(RA),RC
+* lhaubr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -108,7 +108,7 @@ Special Registers Altered:
 
 SVD-Form
 
-* lwz RT,SVD(RA),RC
+* lwzbr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -125,7 +125,7 @@ Special Registers Altered:
 
 SVD-Form
 
-* lwzu RT,SVD(RA),RC
+* lwzubr RT,SVD(RA),RC
 
 Pseudo-code:
 
@@ -142,7 +142,7 @@ Special Registers Altered:
 
 SVDS-Form
 
-* lwa RT,SVDS(RA),RC
+* lwabr RT,SVDS(RA),RC
 
 Pseudo-code:
 
@@ -159,7 +159,7 @@ Special Registers Altered:
 
 SVDS-Form
 
-* ld RT,SVDS(RA),RC
+* ldbr RT,SVDS(RA),RC
 
 Pseudo-code:
 
@@ -176,7 +176,7 @@ Special Registers Altered:
 
 SVDS-Form
 
-* ldu RT,SVDS(RA),RC
+* ldubr RT,SVDS(RA),RC
 
 Pseudo-code:
 

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 3ed5273791299015947137386e1884ec665eb8a3..fc04757e7bf3a7f9f457567f9a7835a5d7f393c2 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -246,12 +246,18 @@ _insns = [
     "hrfid", "icbi", "icbt", "isel", "isync",
     "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
+    "lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
+    "ldbr", "ldubr",    # load double SVP64 bit-reversed
     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
+    "lhabr", "lhaubr",  # load half SVP64 bit-reversed
+    "lhzbr", "lhzubr",  # more load half SVP64 bit-reversed
     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
+    "lwabr",           # load word SVP64 bit-reversed
+    "lwzbr", "lwzubr", # more load word SVP64 bit-reversed
     "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add
     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",