nope. failfirst needs to always save the result, but truncate VL *after*.

https://bugs.libre-soc.org/show_bug.cgi?id=936

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 078a2f0b6271536b4d39646768a646c0e2189d3e..6971aa21f4f0b8a83febede68a6406c1169ab622 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1926,14 +1926,13 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
     def do_outregs_nia(self, asmop, ins_name, info, outs,
                        carry_en, rc_en, ffirst_hit):
         ffirst_hit, vli = ffirst_hit
-        if not ffirst_hit or vli:
-            # write out any regs for this instruction
-            for name, output in outs.items():
-                yield from self.check_write(info, name, output, carry_en)
+        # write out any regs for this instruction
+        for name, output in outs.items():
+            yield from self.check_write(info, name, output, carry_en)
         # restore the CR value on non-VLI failfirst (from sv.cmp and others
         # which write directly to CR in the pseudocode (gah, what a mess)
-        if ffirst_hit and not vli:
-            self.cr.value = self.cr_backup
+        #if ffirst_hit and not vli:
+        #    self.cr.value = self.cr_backup
 
         if ffirst_hit:
             self.svp64_reset_loop()

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
index 73fed6e52948c4a25b93f818b075f93ed5567006..af5fb4702feea7043246038267bc3d30c2e2158b 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py
@@ -57,10 +57,10 @@ class DecoderTestCase(FHDLTestCase):
             expected_vl = 0
             for i in range(4):
                 result = expected[i] - gprs[8]
+                expected[i] = result
                 if result <= 0:
                     break
                 # only write out if successful
-                expected[i] = result
                 expected_vl += 1
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
@@ -101,10 +101,9 @@ class DecoderTestCase(FHDLTestCase):
             expected = deepcopy(vec)
             for i in range(4):
                 result = expected[i] - gprs[8]
+                expected[i] = result
                 if result == 0:
                     break
-                # only write out if successful
-                expected[i] = result
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 
@@ -144,10 +143,9 @@ class DecoderTestCase(FHDLTestCase):
             expected = deepcopy(vec)
             for i in range(4):
                 result = expected[i] - gprs[8]
+                expected[i] = result
                 if result == 0:
                     break
-                # only write out if successful
-                expected[i] = result
             for i, v in enumerate(res):
                 self.assertEqual(v, expected[i])
 

diff --git a/src/openpower/decoder/isa/test_caller_svp64_inssort.py b/src/openpower/decoder/isa/test_caller_svp64_inssort.py
index 9b0490fc469adfbb08512931b9c90e698816a7b7..1fe0b6b516eae156aea563a887578f67447e05cd 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_inssort.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_inssort.py
@@ -84,7 +84,7 @@ class DecoderTestCase(FHDLTestCase):
 
         gprs = [0] * 64
         vec = [1, 2, 3]
-        crs_expected = [8, 0, 0] # LT EQ GT
+        crs_expected = [8, 2, 0] # LT EQ GT
 
         res = []
         # store GPRs
@@ -122,7 +122,7 @@ class DecoderTestCase(FHDLTestCase):
 
         gprs = [0] * 64
         vec = [1, 2, 3]
-        crs_expected = [8, 2, 0] # LT EQ GT
+        crs_expected = [8, 2, 4] # LT EQ GT
 
         res = []
         # store GPRs