(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 9e55f39a95b62456a78c0e16d26a937cf46454ad..2fe7fa73c647d2f1150ba249f3c9802444fc5c93 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -208,11 +208,18 @@ foundation to take a leap forward in performance and performance/watt,
 The most obvious question before that is: why would you want to?
 As explained in the "SIMD Considered Harmful" article, Cray-style
 Vector ISAs break the link between data element batches and the
-underylying architectural back-end parallel processing capability.
+underlying architectural back-end parallel processing capability.
 Packed SIMD explicitly smashes that width right in the face of the
 programmer and expects them to like it.  As the article immediately
 demonstrates, an arbitrary-sized data set has to contend with
-power-of-two setup and teardown that can add literally an order
-of magnitude size in the number of hand-written lines of assembler
+an insane power-of-two Packed SIMD cascade at both setup and teardown
+that can add literally an order
+of magnitude increase in the number of hand-written lines of assembler
 compared to a well-designed Cray-style Vector ISA with a `setvl`
 instruction.
+
+Assuming then that variable-length Vectors are obviously desirable,
+it becomes a matter of how, not if.  Both Cray and NEC SX Aurora
+went the way of adding explicit Vector opcodes, a style which RVV
+copied and modernised. In the case of RVV this introduced 192 new
+instructions on top of an existing 95+ for base RV64GC.