(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 75a532aa8ebdd88e640f25d8d438dc677fa9ada8..cd6215fa741911b0baa65ff49330cc72181b4a7f 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -536,8 +536,15 @@ and apply deterministic nested loop schedules to more than just registers
 
 OpenCAPI is a deterministic high-performance, high-bandwidth, low-latency
 cache-coherent Memory-access Protocol that is integrated into IBM's Supercomputing-class POWER9 and POWER10 processors. POWER10 *only*
-has OpenCAPI interfaces, and requires an OpenCAPI-to-DDR4/5 Bridge PHY
+has OpenCAPI Memory interfaces, and requires an OpenCAPI-to-DDR4/5 Bridge PHY
 to connect to standard DIMMs.
 
+Extra-V appears to be a remarkable research project that, by leveraging
+OpenCAPI, assuming that the map of edges in any given arbitrary data graph
+could be kept by the main CPU in-memory, could distribute and delegate
+a limited-capability deterministic node-walking schedule actually right down into the memory itself (on the other side of that L1-4 cache barrier),
+where, thanks to the OpenCAPI Standard, many of the nightmare problems
+of other more explicit parallel processing paradigms disappear.
+
 **Snitch**