+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * archures.c (bfd_architecture): New machine
+ bfd_mach_mips_gs464e.
+ * bfd-in2.h (bfd_architecture): Likewise.
+ * cpu-mips.c (enum I_xxx): Likewise.
+ (arch_info_struct): Likewise.
+ * elfxx-mips.c (_bfd_elf_mips_mach): Handle
+ E_MIPS_MACH_GS464E.
+ (mips_set_isa_flags): Likewise.
+ (mips_mach_extensions): Map bfd_mach_mips_gs464e to
+ bfd_mach_mips_gs464 extension.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* archures.c (bfd_architecture): Rename
.#define bfd_mach_mips_loongson_2e 3001
.#define bfd_mach_mips_loongson_2f 3002
.#define bfd_mach_mips_gs464 3003
+.#define bfd_mach_mips_gs464e 3004
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01. *}
.#define bfd_mach_mips_octeon 6501
.#define bfd_mach_mips_octeonp 6601
#define bfd_mach_mips_loongson_2e 3001
#define bfd_mach_mips_loongson_2f 3002
#define bfd_mach_mips_gs464 3003
+#define bfd_mach_mips_gs464e 3004
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01. */
#define bfd_mach_mips_octeon 6501
#define bfd_mach_mips_octeonp 6601
I_loongson_2e,
I_loongson_2f,
I_gs464,
+ I_gs464e,
I_mipsocteon,
I_mipsocteonp,
I_mipsocteon2,
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
N (64, 64, bfd_mach_mips_gs464, "mips:gs464", FALSE, NN(I_gs464)),
+ N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e", FALSE, NN(I_gs464e)),
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
case E_MIPS_MACH_GS464:
return bfd_mach_mips_gs464;
+ case E_MIPS_MACH_GS464E:
+ return bfd_mach_mips_gs464e;
+
case E_MIPS_MACH_OCTEON3:
return bfd_mach_mips_octeon3;
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464;
break;
+ case bfd_mach_mips_gs464e:
+ val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464E;
+ break;
+
case bfd_mach_mips_octeon:
case bfd_mach_mips_octeonp:
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
{ bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
+ { bfd_mach_mips_gs464e, bfd_mach_mips_gs464 },
{ bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
/* MIPS64 extensions. */
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
+ * readelf.c (get_machine_flags): Handle gs464e.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* NEWS: Mention Loongson 3A1000 proccessor support.
-*- text -*-
+* The MIPS port now supports the Loongson 3A2000/3A3000 processor which
+ implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE,
+ Loongson-ext ASE and Loongson-ext2 ASE instructions. Add -march=gs464e
+ option for Loongson 3A2000/3A3000 processor.
+
* The MIPS port now supports the Loongson 3A1000 processor, aka Loongson3a,
which implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE
and Loongson-ext ASE instructions. Add -march=gs464 option for Loongson
case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
+ case E_MIPS_MACH_GS464E: strcat (buf, ", gs464e"); break;
case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
E_MIPS_MACH_LS2E = 0x00A00000,
E_MIPS_MACH_LS2F = 0x00A10000,
E_MIPS_MACH_GS464 = 0x00A20000,
+ E_MIPS_MACH_GS464E = 0x00A30000,
};
// MIPS architecture
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
+ (mips_cpu_info_table): Add gs464e descriptors.
+ * doc/as.texi (march table): Add gs464e.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
|| (ISA) == ISA_MIPS64R5 \
|| (ISA) == ISA_MIPS64R6 \
|| (CPU) == CPU_R5900) \
- && (CPU) != CPU_GS464)
+ && ((CPU) != CPU_GS464 \
+ || (CPU) != CPU_GS464E))
/* Return true if ISA supports move to/from high part of a 64-bit
floating-point register. */
ISA_MIPS64R2, CPU_GS464 },
{ "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
ISA_MIPS64R2, CPU_GS464 },
+ { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+ | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E },
/* Cavium Networks Octeon CPU core */
{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
loongson2e,
loongson2f,
gs464,
+gs464e,
octeon,
octeon+,
octeon2,
mach_mips_loongson_2e = 3001,
mach_mips_loongson_2f = 3002,
mach_mips_gs464 = 3003,
+ mach_mips_gs464e = 3004,
mach_mips_sb1 = 12310201, // octal 'SB', 01
mach_mips_octeon = 6501,
mach_mips_octeonp = 6601,
this->add_extension(mach_mips_octeon2, mach_mips_octeonp);
this->add_extension(mach_mips_octeonp, mach_mips_octeon);
this->add_extension(mach_mips_octeon, mach_mipsisa64r2);
+ this->add_extension(mach_mips_gs464e, mach_mips_gs464);
this->add_extension(mach_mips_gs464, mach_mipsisa64r2);
// MIPS64 extensions.
case elfcpp::E_MIPS_MACH_GS464:
return mach_mips_gs464;
+ case elfcpp::E_MIPS_MACH_GS464E:
+ return mach_mips_gs464e;
+
case elfcpp::E_MIPS_MACH_OCTEON3:
return mach_mips_octeon3;
return "mips:loongson_2f";
case elfcpp::E_MIPS_MACH_GS464:
return "mips:gs464";
+ case elfcpp::E_MIPS_MACH_GS464E:
+ return "mips:gs464e";
case elfcpp::E_MIPS_MACH_OCTEON:
return "mips:octeon";
case elfcpp::E_MIPS_MACH_OCTEON2:
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+
+ * elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
+ * opcode/mips.h (CPU_XXX): New CPU_GS464E.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
#define E_MIPS_MACH_LS2E 0x00A00000
#define E_MIPS_MACH_LS2F 0x00A10000
#define E_MIPS_MACH_GS464 0x00A20000
+#define E_MIPS_MACH_GS464E 0x00A30000
\f
/* Processor specific section indices. These sections do not actually
exist. Symbols with a st_shndx field corresponding to one of these
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
#define CPU_GS464 3003
+#define CPU_GS464E 3004
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
+ gs464e and gs464.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
{ mips32r2 interaptiv-mr2 } \
MIPS32r5 "Imagination interAptiv MR2" \
{ "DSP ASE" "Enhanced VA Scheme" "MT ASE" }
+
+good_combination { "-march=gs464 -32" "-march=gs464e -32" } \
+ { gs464e o32 } \
+ MIPS64r2 "None" \
+ { "Loongson MMI ASE" "Loongson CAM ASE" "Loongson EXT ASE" "Loongson EXT2 ASE" }
+2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
+
+ * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
+
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
mips_hwr_names_numeric },
+ { "g464e", 1, bfd_mach_mips_gs464e, CPU_GS464E,
+ ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT
+ | ASE_LOONGSON_EXT2, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
+ mips_hwr_names_numeric },
+
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0,
mips_cp1_names_mips3264, mips_hwr_names_numeric },