move ffadds to not conflict with fptrans -- makes space for min/max/fmod/remainder ops

diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv
index cdb66e40781d29a953511371e1e5ff33eed24577..2e7d13cc72b5b1b7df205653d373e6122f307128 100644 (file)
--- a/openpower/isatables/minor_59.csv
+++ b/openpower/isatables/minor_59.csv
@@ -18,7 +18,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 -----00101,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
 -----00110,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmsubs,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
 -----00111,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffnmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
-1000001100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,X,,1,2-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
+1111100000,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,ffadds,X,,1,2-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
 -----11011,FPU,OP_FP_MADD,FRA,FRB,FRC,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fdmadds,A,,1,3-in 2-out: implicit FRS. unofficial until submitted and approved/renumbered by the opf isa wg
 1001001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fatan2s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 1000001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fatan2pis,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 157093c6338ba55a93a7a76b96532122fd8ab0c0..8cd7db702ba5be574173e704162f643317fefa05 100644 (file)
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -1037,7 +1037,7 @@ class PowerDecodeSubset(Elaboratable):
                 '-----00101',  # ffmadds
                 '-----00110',  # ffnmsubs
                 '-----00111',  # ffnmadds
-                '1000001100',  # ffadds
+                '1111100000',  # ffadds
                 '-----11011',  # fdmadds
             ))
 

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 7b146fb4ca2a4170abb69f7d4bfcddfe96abc0fa..7a7dad01ffcdaa64fbdbc15d7fa74eb112db74ab 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1391,7 +1391,7 @@ class SVP64Asm:
             opcode |= int(v30b_newfields[0]) << (32-11)  # FRT
             opcode |= int(v30b_newfields[1]) << (32-16)  # FRA
             opcode |= int(v30b_newfields[2]) << (32-21)  # FRB
-            opcode |= 0b1000001100 << (32-31)   # bits 21-30
+            opcode |= 0b1111100000 << (32-31)   # bits 21-30
             if rc:
                 opcode |= 1  # Rc, bit 31.
             yield ".long 0x%x" % opcode