#include "arch/x86/generated/decoder.hh"
#include "arch/x86/isa_traits.hh"
+#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/Faults.hh"
modeStr = "write";
else
modeStr = "read";
- panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
+
+ // print information about what we are panic'ing on
+ if (!inst) {
+ panic("Tried to %s unmapped address %#x.\n", modeStr, addr);
+ } else {
+ panic("Tried to %s unmapped address %#x.\nPC: %#x, Instr: %s",
+ modeStr, addr, tc->pcState().pc(),
+ inst->disassemble(tc->pcState().pc(), debugSymbolTable));
+ }
}
}
SimpleThread* thread = t_info.thread;
Addr instAddr = thread->instAddr();
+ Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
// set up memory request for instruction fetch
- DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
+ DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
- Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
- req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(),
- instAddr);
+ req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
+ instMasterId(), instAddr);
}