No point logging constant bit

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index aa10aa55e6c685edf693f73d2d0cc7ad6e76d518..6718e4f2cd192f68ce6bd7df194d3f33be785616 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -110,7 +110,7 @@ struct XAigerWriter
                }
 
                if (bit == State::Sx || bit == State::Sz) {
-                       log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit));
+                       log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
                        a = aig_map.at(State::S0);
                }