uint32_t stencil_uniforms[3];
};
+#define perf_debug(...) do { \
+ if (unlikely(vc4_debug & VC4_DEBUG_PERF)) \
+ fprintf(stderr, __VA_ARGS__); \
+} while (0)
+
static inline struct vc4_context *
vc4_context(struct pipe_context *pcontext)
{
* IN THE SOFTWARE.
*/
+#include "util/u_prim.h"
#include "util/u_format.h"
#include "util/u_pack_color.h"
#include "indices/u_primconvert.h"
util_primconvert_save_index_buffer(vc4->primconvert, &vc4->indexbuf);
util_primconvert_save_rasterizer_state(vc4->primconvert, &vc4->rasterizer->base);
util_primconvert_draw_vbo(vc4->primconvert, info);
+ perf_debug("Fallback conversion for %d %s vertices\n",
+ info->count, u_prim_name(info->mode));
return;
}
/* We can't flag new buffers for clearing once we've queued draws. We
* could avoid this by using the 3d engine to clear.
*/
- if (vc4->draw_call_queued)
+ if (vc4->draw_call_queued) {
+ perf_debug("Flushing rendering to process new clear.");
vc4_flush(pctx);
+ }
if (buffers & PIPE_CLEAR_COLOR0) {
vc4->clear_color[0] = vc4->clear_color[1] =
if (shadow->writes == orig->writes)
return;
+ perf_debug("Updating shadow texture due to %s\n",
+ view->u.tex.first_level ? "base level" : "raster layout");
+
for (int i = 0; i <= shadow->base.b.last_level; i++) {
unsigned width = u_minify(shadow->base.b.width0, i);
unsigned height = u_minify(shadow->base.b.height0, i);
if (shadow->writes == orig->writes)
return;
+ perf_debug("Fallback conversion for %d uint indices\n", count);
+
struct pipe_transfer *src_transfer;
uint32_t *src = pipe_buffer_map_range(pctx, &orig->base.b,
ib->offset,