Revert "fhdl/verilog: do not use initial begin in _printinit (not accepted by all...

This breaks simulations, and we will try to use the "reg name = value" syntax instead.

This reverts commit e946f6e4538277308e374cd1f0b1b9a31f66dc5a.

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 7f97fa0ddc72d26afe7a90504a676493e1c0759c..de36556fafff08c7186a5975ccfc0d6756a20734 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -279,19 +279,11 @@ def _printinit(f, ios, ns):
                - ios \
                - list_targets(f) \
                - list_special_ios(f, False, True, True)
-       wires = (_list_comb_wires(f) | list_special_ios(f, True, False, False)) \
-               - ios \
-               - list_targets(f) \
-               - list_special_ios(f, False, True, True)
        if signals:
+               r += "initial begin\n"
                for s in sorted(signals, key=lambda x: x.huid):
-                       if s in wires:
-                               r += "assign" + ns.get_name(s) + " = " + _printexpr(ns, s.reset)[0] + ";\n"
-               r += "always @(*) begin\n"
-               for s in sorted(signals, key=lambda x: x.huid):
-                       if s not in wires:
-                               r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
-               r += "end\n"
+                       r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
+               r += "end\n\n"
        return r
 
 def convert(f, ios=None, name="top",