Arc assembler: Convert nps400 from a machine type to an extension.

gas	* config/tc-arc.c (check_cpu_feature, md_parse_option):
	Add nps400 option and feature. Add check for nps400
	feature. Refactor existing checks to check subclass before
	feature enablement.
	(md_show_usage): Document flags for NPS-400 and add some other
	undocumented flags.
	(cpu_type): Remove nps400 CPU type entry
	(check_zol): Remove bfd_mach_arc_nps400 case.
	(md_show_usage): Add help on -mcpu=nps400.
	(cpu_types): Add entry for nps400 as arc700 plus nps400 extension
	set.
	* doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
	-fpuda flags.  Document -mcpu=nps400.
	* testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
	expected flags to match ARC700 instead of NPS400.
	* testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
	* testsuite/gas/arc/nps-400-2.d: Likewise.
	* testsuite/gas/arc/nps-400-3.d: Likewise.
	* testsuite/gas/arc/nps-400-4.d: Likewise.
	* testsuite/gas/arc/nps-400-5.d: Likewise.
	* testsuite/gas/arc/nps-400-6.d: Likewise.
	* testsuite/gas/arc/nps-400-7.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
	avoid clash with cbba instruction.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
	-mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.

binutils* readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
	case.

ld	* testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
	* testsuite/ld-arc/nps-1b.d: Likewise.

include	* opcode/arc.h: Add nps400 extension and instruction
	subclass.
	Remove ARC_OPCODE_NPS400
	* elf/arc.h: Remove E_ARC_MACH_NPS400

opcodes	* arc-dis.c (arc_insn_length): Add comment on instruction length.
	Use same method for determining	instruction length on ARC700 and
	NPS-400.
	(arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
	* arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
	with the NPS400 subclass.
	* arc-opc.c: Likewise.

bfd	* archures.c: Remove bfd_mach_arc_nps400.
	* bfd-in2.h: Likewise.
	* cpu-arc.c (arch_info_struct): Likewise.
	* elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
	Likewise.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 85d2cea2eef905d99d51717fde73b9349f55d90e..2b87660cfc23b10817541599cb200cb7dc1fa82f 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,11 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+       * archures.c: Remove bfd_mach_arc_nps400.
+       * bfd-in2.h: Likewise.
+       * cpu-arc.c (arch_info_struct): Likewise.
+       * elf32-arc.c (arc_elf_object_p, arc_elf_final_write_processing):
+       Likewise.
+
 2016-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/18250

diff --git a/bfd/archures.c b/bfd/archures.c
index a00c71265324c39169d33e2e17c1490f82a08f93..96c91099ac203ec7c5f26b3aa0ff597b3b9d2522 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -375,7 +375,6 @@ DESCRIPTION
 .#define bfd_mach_arc_arc601    4
 .#define bfd_mach_arc_arc700    3
 .#define bfd_mach_arc_arcv2     5
-.#define bfd_mach_arc_nps400    6
 . bfd_arch_m32c,     {* Renesas M16C/M32C.  *}
 .#define bfd_mach_m16c        0x75
 .#define bfd_mach_m32c        0x78

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index af950a01badbec8161c0b2f5172173040636a6fc..ebed9664bb28f553d5cc0f719819d00ea53dabd9 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -2186,7 +2186,6 @@ enum bfd_architecture
 #define bfd_mach_arc_arc601    4
 #define bfd_mach_arc_arc700    3
 #define bfd_mach_arc_arcv2     5
-#define bfd_mach_arc_nps400    6
  bfd_arch_m32c,     /* Renesas M16C/M32C.  */
 #define bfd_mach_m16c        0x75
 #define bfd_mach_m32c        0x78

diff --git a/bfd/cpu-arc.c b/bfd/cpu-arc.c
index 472af8d96cc4453ce55759ecc9c04c9fa2e8b633..07a052b8a5072678cdf2f8560b5650ec40d42ade 100644 (file)
--- a/bfd/cpu-arc.c
+++ b/bfd/cpu-arc.c
@@ -47,9 +47,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   ARC (bfd_mach_arc_arc601, "ARC601", FALSE, &arch_info_struct[3]),
   ARC (bfd_mach_arc_arc700, "ARC700", FALSE, &arch_info_struct[4]),
   ARC (bfd_mach_arc_arc700, "A7",     FALSE, &arch_info_struct[5]),
-  ARC (bfd_mach_arc_nps400, "NPS400", FALSE, &arch_info_struct[6]),
-  ARC (bfd_mach_arc_arcv2,  "ARCv2",  FALSE, &arch_info_struct[7]),
-  ARC (bfd_mach_arc_arcv2,  "EM",     FALSE, &arch_info_struct[8]),
+  ARC (bfd_mach_arc_arcv2,  "ARCv2",  FALSE, &arch_info_struct[6]),
+  ARC (bfd_mach_arc_arcv2,  "EM",     FALSE, &arch_info_struct[7]),
   ARC (bfd_mach_arc_arcv2,  "HS",     FALSE, NULL),
 };
 

diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index 82bfe02615300dbd8e4085b28435c31bd1a81fd3..0161832ca73f0e89d76d6630047a10000adac563 100644 (file)
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -621,9 +621,6 @@ arc_elf_object_p (bfd * abfd)
          case E_ARC_MACH_ARC700:
            mach = bfd_mach_arc_arc700;
            break;
-         case E_ARC_MACH_NPS400:
-           mach = bfd_mach_arc_nps400;
-           break;
          case EF_ARC_CPU_ARCV2HS:
          case EF_ARC_CPU_ARCV2EM:
            mach = bfd_mach_arc_arcv2;
@@ -673,9 +670,6 @@ arc_elf_final_write_processing (bfd * abfd,
     case bfd_mach_arc_arc700:
       emf = EM_ARC_COMPACT;
       break;
-    case bfd_mach_arc_nps400:
-      emf = EM_ARC_COMPACT;
-      break;
     case bfd_mach_arc_arcv2:
       emf = EM_ARC_COMPACT2;
       break;

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 5f52ed967895e457425d64f17ea24931fc645362..1574ba4e820242f030b0ed9264675071845faa36 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+       * readelf.c (decode_ARC_machine_flags): Remove E_ARC_MACH_NPS400
+       case.
+
 2016-06-15  Nick Clifton  <nickc@redhat.com>
 
        * readelf.c (is_24bit_abs_reloc): Add support for R_FT32_20

diff --git a/binutils/readelf.c b/binutils/readelf.c
index ac278a4da3844a6963e8e7f41f457d2e0c461cec..81459182b32adc814a228a9a97a10f41ac138e0a 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2381,9 +2381,6 @@ decode_ARC_machine_flags (unsigned e_flags, unsigned e_machine, char buf[])
     case E_ARC_MACH_ARC700:
       strcat (buf, ", ARC700");
       break;
-    case E_ARC_MACH_NPS400:
-      strcat (buf, ", NPS400");
-      break;
 
       /* The only times we should end up here are (a) A corrupt ELF, (b) A
          new ELF with new architecture being read by an old version of

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3f1af8a8449f639f65d0c16be5dd50c3e2538845..4672d15229e35cf30965ede98d0cacad6b9d6cb1 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,35 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+       * config/tc-arc.c (check_cpu_feature, md_parse_option):
+       Add nps400 option and feature. Add check for nps400
+       feature. Refactor existing checks to check subclass before
+       feature enablement.
+       (md_show_usage): Document flags for NPS-400 and add some other
+       undocumented flags.
+       (cpu_type): Remove nps400 CPU type entry
+       (check_zol): Remove bfd_mach_arc_nps400 case.
+       (md_show_usage): Add help on -mcpu=nps400.
+       (cpu_types): Add entry for nps400 as arc700 plus nps400 extension
+       set.
+       * doc/c-arc.texi: Document the -mnps400, -mspfp, -mdpfp, and
+       -fpuda flags.  Document -mcpu=nps400.
+       * testsuite/gas/arc/nps-400-0.d: Use -mcpu=arc700 -mnps400. Change
+       expected flags to match ARC700 instead of NPS400.
+       * testsuite/gas/arc/nps-400-1.d: Use -mcpu=arc700 -mnps400.
+       * testsuite/gas/arc/nps-400-2.d: Likewise.
+       * testsuite/gas/arc/nps-400-3.d: Likewise.
+       * testsuite/gas/arc/nps-400-4.d: Likewise.
+       * testsuite/gas/arc/nps-400-5.d: Likewise.
+       * testsuite/gas/arc/nps-400-6.d: Likewise.
+       * testsuite/gas/arc/nps-400-7.d: Likewise.
+       * testsuite/gas/arc/textinsn2op01.s: Change opcode of myinsn to
+       avoid clash with cbba instruction.
+       * testsuite/gas/arc/textinsn2op01.d: Likewise.
+       * testsuite/gas/arc/textinsn3op.d: Likewise.
+       * testsuite/gas/arc/textinsn3op.s: Likewise.
+       * testsuite/gas/arc/nps-400-0.d: Test using NPS-400 using
+       -mcpu=nps400 as an alternative to -mcpu=arc700 -mnps400 flags.
+
 2016-06-20  Maciej W. Rozycki  <macro@imgtec.com>
 
        * testsuite/gas/mips/r6-64-n32.d: Change the `name' tag.

diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 966b18d2ac7fe721d5847d81b0c3170f0e78c446..34d58a1c1eeda9cca586fa6dd068924a53504126 100644 (file)
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -100,6 +100,7 @@ enum arc_rlx_types
 #define is_fpuda_p(op)          (((sc) == DPA))
 #define is_br_jmp_insn_p(op)    (((op)->insn_class == BRANCH || (op)->insn_class == JUMP))
 #define is_kernel_insn_p(op)    (((op)->insn_class == KERNEL))
+#define is_nps400_p(op)         (((sc) == NPS400))
 
 /* Generic assembler global variables which must be defined by all
    targets.  */
@@ -179,6 +180,7 @@ enum options
   OPTION_MCPU,
   OPTION_CD,
   OPTION_RELAX,
+  OPTION_NPS400,
 
   /* The following options are deprecated and provided here only for
      compatibility reasons.  */
@@ -221,6 +223,7 @@ struct option md_longopts[] =
   { "mHS",             no_argument,       NULL, OPTION_ARCHS },
   { "mcode-density",   no_argument,       NULL, OPTION_CD },
   { "mrelax",           no_argument,       NULL, OPTION_RELAX },
+  { "mnps400",          no_argument,       NULL, OPTION_NPS400 },
 
   /* The following options are deprecated and provided here only for
      compatibility reasons.  */
@@ -425,8 +428,8 @@ static const struct cpu_type
     E_ARC_MACH_ARC600,  0x00},
   { "arc700", ARC_OPCODE_ARC700,  bfd_mach_arc_arc700,
     E_ARC_MACH_ARC700,  0x00},
-  { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
-    E_ARC_MACH_NPS400,  0x00},
+  { "nps400", ARC_OPCODE_ARC700 , bfd_mach_arc_arc700,
+    E_ARC_MACH_ARC700,  ARC_NPS400},
   { "arcem",  ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
     EF_ARC_CPU_ARCV2EM, 0x00},
   { "archs",  ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
@@ -1529,20 +1532,19 @@ allocate_tok (expressionS *tok, int ntok, int cidx)
 static bfd_boolean
 check_cpu_feature (insn_subclass_t sc)
 {
-  if (!(arc_features & ARC_CD)
-      && is_code_density_p (sc))
+  if (is_code_density_p (sc) && !(arc_features & ARC_CD))
     return FALSE;
 
-  if (!(arc_features & ARC_SPFP)
-      && is_spfp_p (sc))
+  if (is_spfp_p (sc) && !(arc_features & ARC_SPFP))
     return FALSE;
 
-  if (!(arc_features & ARC_DPFP)
-      && is_dpfp_p (sc))
+  if (is_dpfp_p (sc) && !(arc_features & ARC_DPFP))
     return FALSE;
 
-  if (!(arc_features & ARC_FPUDA)
-      && is_fpuda_p (sc))
+  if (is_fpuda_p (sc) && !(arc_features & ARC_FPUDA))
+    return FALSE;
+
+  if (is_nps400_p (sc) && !(arc_features & ARC_NPS400))
     return FALSE;
 
   return TRUE;
@@ -3341,6 +3343,9 @@ md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
       relaxation_state = 1;
       break;
 
+    case OPTION_NPS400:
+      arc_features |= ARC_NPS400;
+
     case OPTION_USER_MODE:
     case OPTION_LD_EXT_MASK:
     case OPTION_SWAP:
@@ -3396,6 +3401,18 @@ md_show_usage (FILE *stream)
   fprintf (stream, _("ARC-specific assembler options:\n"));
 
   fprintf (stream, "  -mcpu=<cpu name>\t  assemble for CPU <cpu name>\n");
+  fprintf (stream, "  -mcpu=nps400\t\t  same as -mcpu=arc700 -mnps400\n");
+  fprintf (stream, "  -mA6/-mARC600/-mARC601  same as -mcpu=arc600\n");
+  fprintf (stream, "  -mA7/-mARC700\t\t  same as -mcpu=arc700\n");
+  fprintf (stream, "  -mEM\t\t\t  same as -mcpu=arcem\n");
+  fprintf (stream, "  -mHS\t\t\t  same as -mcpu=archs\n");
+
+  fprintf (stream, "  -mnps400\t\t  enable NPS-400 extended instructions\n");
+  fprintf (stream, "  -mspfp\t\t  enable single-precision floating point instructions\n");
+  fprintf (stream, "  -mdpfp\t\t  enable double-precision floating point instructions\n");
+  fprintf (stream, "  -mfpuda\t\t  enable double-precision assist floating "
+                   "point\n\t\t\t  instructions for ARC EM\n");
+
   fprintf (stream,
           "  -mcode-density\t  enable code density option for ARC EM\n");
 
@@ -3404,8 +3421,36 @@ md_show_usage (FILE *stream)
   fprintf (stream, _("\
   -EL                     assemble code for a little-endian cpu\n"));
   fprintf (stream, _("\
-  -mrelax                  Enable relaxation\n"));
-
+  -mrelax                 enable relaxation\n"));
+
+  fprintf (stream, _("The following ARC-specific assembler options are "
+                     "deprecated and are accepted\nfor compatibility only:\n"));
+
+  fprintf (stream, _("  -mEA\n"
+                     "  -mbarrel-shifter\n"
+                     "  -mbarrel_shifter\n"
+                     "  -mcrc\n"
+                     "  -mdsp-packa\n"
+                     "  -mdsp_packa\n"
+                     "  -mdvbf\n"
+                     "  -mld-extension-reg-mask\n"
+                     "  -mlock\n"
+                     "  -mmac-24\n"
+                     "  -mmac-d16\n"
+                     "  -mmac_24\n"
+                     "  -mmac_d16\n"
+                     "  -mmin-max\n"
+                     "  -mmin_max\n"
+                     "  -mmul64\n"
+                     "  -mno-mpy\n"
+                     "  -mnorm\n"
+                     "  -mrtsc\n"
+                     "  -msimd\n"
+                     "  -mswap\n"
+                     "  -mswape\n"
+                     "  -mtelephony\n"
+                    "  -muser-mode-only\n"
+                     "  -mxy\n"));
 }
 
 /* Find the proper relocation for the given opcode.  */
@@ -4070,7 +4115,6 @@ check_zol (symbolS *s)
 end of the ZOL label @%s"), S_GET_NAME (s));
 
       /* Fall through.  */
-    case bfd_mach_arc_nps400:
     case bfd_mach_arc_arc700:
       if (arc_last_insns[0].has_delay_slot)
        as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 1cd60ede65a68f2081284dfc0fecfc690cea6ca4..6d2c325798d585115f3e80aade9416838888f36c 100644 (file)
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -2680,7 +2680,7 @@ do include file processing with the @code{.include} directive
 (@pxref{Include,,@code{.include}}).  You can use the @sc{gnu} C compiler driver
 to get other ``CPP'' style preprocessing by giving the input file a
 @samp{.S} suffix.  @xref{Overall Options, ,Options Controlling the Kind of
-Output, gcc.info, Using GNU CC}.
+Output, gcc.info, Using GNU CC} .
 
 Excess whitespace, comments, and character constants
 cannot be used in the portions of the input text that are not

diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index 4852c3d602314150c670b594446dcb345a0e90d0..64522dbeb839fb29506c8c161b0cba360e9b9142 100644 (file)
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -56,9 +56,6 @@ Assemble for ARC 601.  Alias: @code{-mARC601}.
 @cindex @code{mARC700} command line option, ARC
 Assemble for ARC 700.  Aliases: @code{-mA7}, @code{-mARC700}.
 
-@item nps400
-Assemble for NPS400.
-
 @item arcem
 @cindex @code{mEM} command line option, ARC
 Assemble for ARC EM.  Aliases: @code{-mEM}
@@ -67,6 +64,10 @@ Assemble for ARC EM.  Aliases: @code{-mEM}
 @cindex @code{mHS} command line option, ARC
 Assemble for ARC HS.  Aliases: @code{-mHS}, @code{-mav2hs}.
 
+@item nps400
+@cindex @code{mnps400} command line option, ARC
+Assemble for ARC 700 with NPS-400 extended instructions.
+
 @end table
 
 Note: the @code{.cpu} directive (@pxref{ARC Directives}) can
@@ -94,6 +95,23 @@ Enable support for assembly-time relaxation.  The assembler will
 replace a longer version of an instruction with a shorter one,
 whenever it is possible.
 
+@cindex @code{-mnps400} command line option, ARC
+@item -mnps400
+Enable support for NPS-400 extended instructions.
+
+@cindex @code{-mspfp} command line option, ARC
+@item -mspfp
+Enable support for single-precision floating point instructions.
+
+@cindex @code{-mdpfp} command line option, ARC
+@item -mdpfp
+Enable support for double-precision floating point instructions.
+
+@cindex @code{-mfpuda} command line option, ARC
+@item -mfpuda
+Enable support for double-precision assist floating point instructions.
+Only valid for ARC EM processors.
+
 @end table
 
 @node ARC Syntax

diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d
index a34a4d5662fb86446ec7e7e2632c6c985ef9c0eb..e5920c8a976648f8eb2c5c8be48b4133aa48b5d9 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-0.d
+++ b/gas/testsuite/gas/arc/nps400-0.d
@@ -11,5 +11,5 @@
   Machine:                           ARCompact
   Version:                           0x1
 #...
-  Flags:                             0x307, NPS400, v3 no-legacy-syscalls ABI
-#...
\ No newline at end of file
+  Flags:                             0x303, ARC700, v3 no-legacy-syscalls ABI
+#...

diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d
index 7272cfdbcfc3f396623f533bc677ddbb01010841..707b982f81a7bd8861c413356451115035b61ce3 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-1.d
+++ b/gas/testsuite/gas/arc/nps400-1.d
@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

diff --git a/gas/testsuite/gas/arc/nps400-2.d b/gas/testsuite/gas/arc/nps400-2.d
index 966907e9da2bb39cb51db8d21e57d4b838c60f7d..8327a05af6726878f2e6c7b1f093976054bc301c 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-2.d
+++ b/gas/testsuite/gas/arc/nps400-2.d
@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

diff --git a/gas/testsuite/gas/arc/nps400-3.d b/gas/testsuite/gas/arc/nps400-3.d
index ea525545e5ca64a5b8ae2da2c835d4763cb3523f..5d6ac8aa1eda86036b2e17953e487c2f6701204f 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-3.d
+++ b/gas/testsuite/gas/arc/nps400-3.d
@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

diff --git a/gas/testsuite/gas/arc/nps400-4.d b/gas/testsuite/gas/arc/nps400-4.d
index 2caab8cda77470753355b558563e55b67191d523..99205c694c6660d78a6acf3404c0f81d68c4d0f1 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-4.d
+++ b/gas/testsuite/gas/arc/nps400-4.d
@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

diff --git a/gas/testsuite/gas/arc/nps400-5.d b/gas/testsuite/gas/arc/nps400-5.d
index 214e38e62b2b14ce8d0441f526cbf24fedc541b9..7e8cc0ec382f5d04f4bfde914982c7781d1ca373 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-5.d
+++ b/gas/testsuite/gas/arc/nps400-5.d
@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

diff --git a/gas/testsuite/gas/arc/nps400-6.d b/gas/testsuite/gas/arc/nps400-6.d
index 2edc2b5c90d4c74d213f0c15415f669fce38c157..972689b299b3106222a58cd76d9494678aef9888 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-6.d
+++ b/gas/testsuite/gas/arc/nps400-6.d
@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

diff --git a/gas/testsuite/gas/arc/nps400-7.d b/gas/testsuite/gas/arc/nps400-7.d
index 8e47d19fb4721cc2e8b3ff929db4903bfaf3a9cd..317753dcd99ef5c492558408fb31bce756c50f2e 100644 (file)
--- a/gas/testsuite/gas/arc/nps400-7.d
+++ b/gas/testsuite/gas/arc/nps400-7.d
@@ -1,4 +1,4 @@
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #objdump: -dr
 
 .*: +file format .*arc.*

diff --git a/gas/testsuite/gas/arc/textinsn2op01.d b/gas/testsuite/gas/arc/textinsn2op01.d
index ea14df761c6f42024b60bbef0aeeedb42f962d18..caa4cc07edd8f4548249a4d94bb618cdcac3947f 100644 (file)
--- a/gas/testsuite/gas/arc/textinsn2op01.d
+++ b/gas/testsuite/gas/arc/textinsn2op01.d
@@ -6,22 +6,22 @@
 Disassembly of section .text:
 
 [0-9a-f]+ <.text>:
-   0:  382d 007e               myinsn  r0,r1
-   4:  3b2d 373e               myinsn  fp,sp
-   8:  386d 003e               myinsn  r0,0
-   c:  392d 0fbe ffff ffff     myinsn  r1,0xffffffff
-  14:  3eed 7080 0000 0000     myinsn  0,r2
-  1c:  3c2d 0fbe 0000 00ff     myinsn  r4,0xff
-  24:  3e2d 0fbe ffff ff00     myinsn  r6,0xffffff00
-  2c:  382d 1fbe 0000 0100     myinsn  r8,0x100
-  34:  392d 1fbe ffff feff     myinsn  r9,0xfffffeff
-  3c:  3b2d 1fbe 4242 4242     myinsn  r11,0x42424242
-  44:  382d 0fbe 0000 0000     myinsn  r0,0
+   0:  3830 007e               myinsn  r0,r1
+   4:  3b30 373e               myinsn  fp,sp
+   8:  3870 003e               myinsn  r0,0
+   c:  3930 0fbe ffff ffff     myinsn  r1,0xffffffff
+  14:  3ef0 7080 0000 0000     myinsn  0,r2
+  1c:  3c30 0fbe 0000 00ff     myinsn  r4,0xff
+  24:  3e30 0fbe ffff ff00     myinsn  r6,0xffffff00
+  2c:  3830 1fbe 0000 0100     myinsn  r8,0x100
+  34:  3930 1fbe ffff feff     myinsn  r9,0xfffffeff
+  3c:  3b30 1fbe 4242 4242     myinsn  r11,0x42424242
+  44:  3830 0fbe 0000 0000     myinsn  r0,0
                        48: R_ARC_32_ME foo
-  4c:  382d 807e               myinsn.f        r0,r1
-  50:  3a6d 807e               myinsn.f        r2,0x1
-  54:  3eed f100 0000 0000     myinsn.f        0,r4
-  5c:  3d2d 8fbe 0000 0200     myinsn.f        r5,0x200
-  64:  3eed f102 0000 0000     myinsn.ne.f     0,r4
-  6c:  3eed ff85 dead beef     myinsn.c.f      0xdeadbeef,0xdeadbeef
-  74:  3eed f0a6 dead beef     myinsn.nc.f     0xdeadbeef,0x2
+  4c:  3830 807e               myinsn.f        r0,r1
+  50:  3a70 807e               myinsn.f        r2,0x1
+  54:  3ef0 f100 0000 0000     myinsn.f        0,r4
+  5c:  3d30 8fbe 0000 0200     myinsn.f        r5,0x200
+  64:  3ef0 f102 0000 0000     myinsn.ne.f     0,r4
+  6c:  3ef0 ff85 dead beef     myinsn.c.f      0xdeadbeef,0xdeadbeef
+  74:  3ef0 f0a6 dead beef     myinsn.nc.f     0xdeadbeef,0x2

diff --git a/gas/testsuite/gas/arc/textinsn2op01.s b/gas/testsuite/gas/arc/textinsn2op01.s
index dbd5b24009f6b8cd11accbc2146611339709c4dd..38a069017c68f34ccd9f4563a7fdcbd7333a0c09 100644 (file)
--- a/gas/testsuite/gas/arc/textinsn2op01.s
+++ b/gas/testsuite/gas/arc/textinsn2op01.s
@@ -1,5 +1,5 @@
 # Insn 2op .extInstruction test
-       .extInstruction myinsn, 0x07, 0x2d, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
+       .extInstruction myinsn, 0x07, 0x30, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
 
         myinsn r0,r1
         myinsn fp,sp

diff --git a/gas/testsuite/gas/arc/textinsn3op.d b/gas/testsuite/gas/arc/textinsn3op.d
index abf69ff388c994aac0f5a42720356775be8e1774..2615885a8ee4512cbd2644e7d90435f4050b5d1a 100644 (file)
--- a/gas/testsuite/gas/arc/textinsn3op.d
+++ b/gas/testsuite/gas/arc/textinsn3op.d
@@ -6,58 +6,58 @@
 Disassembly of section .text:
 
 [0-9a-f]+ <.text>:
-   0:  392d 0080               myinsn  r0,r1,r2
-   4:  3b2d 371a               myinsn  gp,fp,sp
-   8:  3e2d 37dd               myinsn  ilink,r30,blink
-   c:  396d 0000               myinsn  r0,r1,0
-  10:  3e2d 7080 0000 0000     myinsn  r0,0,r2
-  18:  392d 00be               myinsn  0,r1,r2
-  1c:  392d 0f80 ffff ffff     myinsn  r0,r1,0xffffffff
-  24:  3e2d 7080 ffff ffff     myinsn  r0,0xffffffff,r2
-  2c:  392d 0f80 0000 00ff     myinsn  r0,r1,0xff
-  34:  3e2d 7080 0000 00ff     myinsn  r0,0xff,r2
-  3c:  392d 0f80 ffff ff00     myinsn  r0,r1,0xffffff00
-  44:  3e2d 7080 ffff ff00     myinsn  r0,0xffffff00,r2
-  4c:  392d 0f80 0000 0100     myinsn  r0,r1,0x100
-  54:  3e2d 7080 ffff feff     myinsn  r0,0xfffffeff,r2
-  5c:  3e2d 7f80 0000 0100     myinsn  r0,0x100,0x100
-  64:  392d 0f80 0000 0000     myinsn  r0,r1,0
+   0:  3930 0080               myinsn  r0,r1,r2
+   4:  3b30 371a               myinsn  gp,fp,sp
+   8:  3e30 37dd               myinsn  ilink,r30,blink
+   c:  3970 0000               myinsn  r0,r1,0
+  10:  3e30 7080 0000 0000     myinsn  r0,0,r2
+  18:  3930 00be               myinsn  0,r1,r2
+  1c:  3930 0f80 ffff ffff     myinsn  r0,r1,0xffffffff
+  24:  3e30 7080 ffff ffff     myinsn  r0,0xffffffff,r2
+  2c:  3930 0f80 0000 00ff     myinsn  r0,r1,0xff
+  34:  3e30 7080 0000 00ff     myinsn  r0,0xff,r2
+  3c:  3930 0f80 ffff ff00     myinsn  r0,r1,0xffffff00
+  44:  3e30 7080 ffff ff00     myinsn  r0,0xffffff00,r2
+  4c:  3930 0f80 0000 0100     myinsn  r0,r1,0x100
+  54:  3e30 7080 ffff feff     myinsn  r0,0xfffffeff,r2
+  5c:  3e30 7f80 0000 0100     myinsn  r0,0x100,0x100
+  64:  3930 0f80 0000 0000     myinsn  r0,r1,0
                        68: R_ARC_32_ME foo
-  6c:  38ed 0080               myinsn  r0,r0,r2
-  70:  3bed 0140               myinsn  r3,r3,r5
-  74:  3eed 0201               myinsn.eq       r6,r6,r8
-  78:  39ed 12c1               myinsn.eq       r9,r9,r11
-  7c:  3ced 1382               myinsn.ne       r12,r12,r14
-  80:  3fed 1442               myinsn.ne       r15,r15,r17
-  84:  3aed 2503               myinsn.p        r18,r18,r20
-  88:  3ded 25c3               myinsn.p        r21,r21,r23
-  8c:  38ed 3684               myinsn.n        r24,r24,gp
-  90:  3bed 3744               myinsn.n        fp,fp,ilink
-  94:  3eed 37c5               myinsn.c        r30,r30,blink
-  98:  3bed 00c5               myinsn.c        r3,r3,r3
-  9c:  3bed 0205               myinsn.c        r3,r3,r8
-  a0:  3bed 0106               myinsn.nc       r3,r3,r4
-  a4:  3ced 0106               myinsn.nc       r4,r4,r4
-  a8:  3ced 01c6               myinsn.nc       r4,r4,r7
-  ac:  3ced 0147               myinsn.v        r4,r4,r5
-  b0:  3ded 0147               myinsn.v        r5,r5,r5
-  b4:  3ded 0148               myinsn.nv       r5,r5,r5
-  b8:  3ded 0148               myinsn.nv       r5,r5,r5
-  bc:  3eed 0009               myinsn.gt       r6,r6,r0
-  c0:  38ed 002a               myinsn.ge       r0,r0,0
-  c4:  39ed 006b               myinsn.lt       r1,r1,0x1
-  c8:  3bed 00ed               myinsn.hi       r3,r3,0x3
-  cc:  3ced 012e               myinsn.ls       r4,r4,0x4
-  d0:  3ded 016f               myinsn.pnz      r5,r5,0x5
-  d4:  392d 8080               myinsn.f        r0,r1,r2
-  d8:  396d 8040               myinsn.f        r0,r1,0x1
-  dc:  3e2d f080 0000 0001     myinsn.f        r0,0x1,r2
-  e4:  392d 80be               myinsn.f        0,r1,r2
-  e8:  392d 8f80 0000 0200     myinsn.f        r0,r1,0x200
-  f0:  3e2d f080 0000 0200     myinsn.f        r0,0x200,r2
-  f8:  39ed 8081               myinsn.eq.f     r1,r1,r2
-  fc:  38ed 8022               myinsn.ne.f     r0,r0,0
- 100:  3aed 808b               myinsn.lt.f     r2,r2,r2
- 104:  3eed f0a9 0000 0001     myinsn.gt.f     0,0x1,0x2
- 10c:  3eed ff8c 0000 0200     myinsn.le.f     0,0x200,0x200
- 114:  3eed f0aa 0000 0200     myinsn.ge.f     0,0x200,0x2
+  6c:  38f0 0080               myinsn  r0,r0,r2
+  70:  3bf0 0140               myinsn  r3,r3,r5
+  74:  3ef0 0201               myinsn.eq       r6,r6,r8
+  78:  39f0 12c1               myinsn.eq       r9,r9,r11
+  7c:  3cf0 1382               myinsn.ne       r12,r12,r14
+  80:  3ff0 1442               myinsn.ne       r15,r15,r17
+  84:  3af0 2503               myinsn.p        r18,r18,r20
+  88:  3df0 25c3               myinsn.p        r21,r21,r23
+  8c:  38f0 3684               myinsn.n        r24,r24,gp
+  90:  3bf0 3744               myinsn.n        fp,fp,ilink
+  94:  3ef0 37c5               myinsn.c        r30,r30,blink
+  98:  3bf0 00c5               myinsn.c        r3,r3,r3
+  9c:  3bf0 0205               myinsn.c        r3,r3,r8
+  a0:  3bf0 0106               myinsn.nc       r3,r3,r4
+  a4:  3cf0 0106               myinsn.nc       r4,r4,r4
+  a8:  3cf0 01c6               myinsn.nc       r4,r4,r7
+  ac:  3cf0 0147               myinsn.v        r4,r4,r5
+  b0:  3df0 0147               myinsn.v        r5,r5,r5
+  b4:  3df0 0148               myinsn.nv       r5,r5,r5
+  b8:  3df0 0148               myinsn.nv       r5,r5,r5
+  bc:  3ef0 0009               myinsn.gt       r6,r6,r0
+  c0:  38f0 002a               myinsn.ge       r0,r0,0
+  c4:  39f0 006b               myinsn.lt       r1,r1,0x1
+  c8:  3bf0 00ed               myinsn.hi       r3,r3,0x3
+  cc:  3cf0 012e               myinsn.ls       r4,r4,0x4
+  d0:  3df0 016f               myinsn.pnz      r5,r5,0x5
+  d4:  3930 8080               myinsn.f        r0,r1,r2
+  d8:  3970 8040               myinsn.f        r0,r1,0x1
+  dc:  3e30 f080 0000 0001     myinsn.f        r0,0x1,r2
+  e4:  3930 80be               myinsn.f        0,r1,r2
+  e8:  3930 8f80 0000 0200     myinsn.f        r0,r1,0x200
+  f0:  3e30 f080 0000 0200     myinsn.f        r0,0x200,r2
+  f8:  39f0 8081               myinsn.eq.f     r1,r1,r2
+  fc:  38f0 8022               myinsn.ne.f     r0,r0,0
+ 100:  3af0 808b               myinsn.lt.f     r2,r2,r2
+ 104:  3ef0 f0a9 0000 0001     myinsn.gt.f     0,0x1,0x2
+ 10c:  3ef0 ff8c 0000 0200     myinsn.le.f     0,0x200,0x200
+ 114:  3ef0 f0aa 0000 0200     myinsn.ge.f     0,0x200,0x2

diff --git a/gas/testsuite/gas/arc/textinsn3op.s b/gas/testsuite/gas/arc/textinsn3op.s
index a07aa9dd2011664de4edc045d0a98c55d8606828..d2fbc3c705c2e119ef7766577163408e93677c5e 100644 (file)
--- a/gas/testsuite/gas/arc/textinsn3op.s
+++ b/gas/testsuite/gas/arc/textinsn3op.s
@@ -1,5 +1,5 @@
 # Insn 3op .extInstruction test
-       .extInstruction myinsn, 0x07, 0x2d, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_3OP
+       .extInstruction myinsn, 0x07, 0x30, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_3OP
 
        myinsn r0,r1,r2
        myinsn r26,fp,sp

diff --git a/include/ChangeLog b/include/ChangeLog
index cb9dacc042d9392c1fa4e8aed57abe2bd5b61785..a9f380fda958c0274671d5f9db7ceebafbbcc74a 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,10 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+       * opcode/arc.h: Add nps400 extension and instruction
+       subclass.
+       Remove ARC_OPCODE_NPS400
+       * elf/arc.h: Remove E_ARC_MACH_NPS400
+
 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
        * opcode/sparc.h (enum sparc_opcode_arch_val): Add

diff --git a/include/elf/arc.h b/include/elf/arc.h
index 2aed25d02cbbb7f4d53779e0717d0093170f441b..47381f3608580bbea623c41732bb69cba3236b2d 100644 (file)
--- a/include/elf/arc.h
+++ b/include/elf/arc.h
@@ -48,7 +48,6 @@ END_RELOC_NUMBERS (R_ARC_max)
 #define E_ARC_MACH_ARC600      0x00000002
 #define E_ARC_MACH_ARC601      0x00000004
 #define E_ARC_MACH_ARC700      0x00000003
-#define E_ARC_MACH_NPS400      0x00000007
 #define EF_ARC_CPU_ARCV2EM      0x00000005
 #define EF_ARC_CPU_ARCV2HS      0x00000006
 

diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index adbae742754b5cbb3aaf520d0e268844202e5dc5..f8f1955b979d560d09baddba1a17ff1aa3d03cab 100644 (file)
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -70,6 +70,7 @@ typedef enum
     MPY7E,
     MPY8E,
     MPY9E,
+    NPS400,
     QUARKSE,
     SHFT1,
     SHFT2,
@@ -172,7 +173,6 @@ extern const struct arc_opcode arc_opcodes[];
 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
-#define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */
 
 /* CPU combi.  */
 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700      \
@@ -186,6 +186,7 @@ extern const struct arc_opcode arc_opcodes[];
 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 #define ARC_MPY      0x0004
 #define ARC_MULT     0x0004
+#define ARC_NPS400   0x0008
 
 /* Floating point support.  */
 #define ARC_DPFP     0x0010

diff --git a/ld/ChangeLog b/ld/ChangeLog
index ca87628eb866e082b54fca178b8488259edc6e58..f1c1fe7d1f2d61a4af4d92ccefbdfb02a8702137 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,8 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+       * testsuite/ld-arc/nps-1a.d: Use -mcpu=arc700 -mnps400.
+       * testsuite/ld-arc/nps-1b.d: Likewise.
+
 2016-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR ld/20267

diff --git a/ld/testsuite/ld-arc/nps-1a.d b/ld/testsuite/ld-arc/nps-1a.d
index 120c71cc443327a0d9671cf82b5d77e9db09f8da..4eae02472a37a1ee4d7756cfbc30a75a0c4f85f4 100644 (file)
--- a/ld/testsuite/ld-arc/nps-1a.d
+++ b/ld/testsuite/ld-arc/nps-1a.d
@@ -1,5 +1,5 @@
 #source: nps-1.s
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #ld: -defsym=foo=0x57f03000
 #objdump: -d
 

diff --git a/ld/testsuite/ld-arc/nps-1b.d b/ld/testsuite/ld-arc/nps-1b.d
index 56c29ae230ea36c1108a8ee6bd345ef31e8c7f1c..a4848b8b7d848c7595a480f7f3e0c43239631443 100644 (file)
--- a/ld/testsuite/ld-arc/nps-1b.d
+++ b/ld/testsuite/ld-arc/nps-1b.d
@@ -1,4 +1,4 @@
 #source: nps-1.s
-#as: -mcpu=nps400
+#as: -mcpu=arc700 -mnps400
 #ld: -defsym=foo=0x56f03000
 #error_output: nps-1b.err

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 39fa888db8c824343a1f73e832c7a1fa4fc21779..f3db0b2e609e95e1ce07b013ca445dec35cfd08c 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2016-06-21  Graham Markall  <graham.markall@embecosm.com>
+
+       * arc-dis.c (arc_insn_length): Add comment on instruction length.
+       Use same method for determining instruction length on ARC700 and
+       NPS-400.
+       (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
+       * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
+       with the NPS400 subclass.
+       * arc-opc.c: Likewise.
+
 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
        * sparc-opc.c (rdasr): New macro.

diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 26dbd738646b2b9bca81c1877edb73b1020bf9e5..1d1dcd81c1bfb9e71aa7179200018c9c91b3fbf6 100644 (file)
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -557,7 +557,12 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
 
   switch (info->mach)
     {
-    case bfd_mach_arc_nps400:
+    case bfd_mach_arc_arc700:
+      /* The nps400 extension set requires this special casing of the
+        instruction length calculation.  Right now this is not causing any
+        problems as none of the known extensions overlap in opcode space,
+        but, if they ever do then we might need to start carrying
+        information around in the elf about which extensions are in use.  */
       if (major_opcode == 0xb)
         {
           bfd_byte minor_opcode = lsb & 0x1f;
@@ -565,7 +570,6 @@ arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
           if (minor_opcode < 4)
             return 2;
         }
-    case bfd_mach_arc_arc700:
     case bfd_mach_arc_arc600:
       return (major_opcode > 0xb) ? 2 : 4;
       break;
@@ -719,10 +723,6 @@ print_insn_arc (bfd_vma memaddr,
 
   switch (info->mach)
     {
-    case bfd_mach_arc_nps400:
-      isa_mask = ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400;
-      break;
-
     case bfd_mach_arc_arc700:
       isa_mask = ARC_OPCODE_ARC700;
       break;

diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index b8ec0af4de550c58a430777868d14a6a17ca87fe..580659a815d5f868544661d59d65e44bb50829b7 100644 (file)
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -1,38 +1,38 @@
 /****                  Bit Manipulation Instructions                  ****/
 
 /* movl<.cl> */
-{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
-{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
+{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
+{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
 
 /* movl<.cl> */
-{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
-{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
+{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
+{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
 
 /* movb<.f><.cl> */
-{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
-{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
+{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
 
 /* movbi<.f><.cl> */
-{ "movbi", 0x480f0000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B  }, { C_NPS_F }},
-{ "movbi", 0x480f8000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B  }, { C_NPS_F, C_NPS_CL }},
+{ "movbi", 0x480f0000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_R_SRC1, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B  }, { C_NPS_F }},
+{ "movbi", 0x480f8000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST, NPS_BITOP_UIMM8, NPS_BITOP_DST_POS, NPS_BITOP_SIZE_2B  }, { C_NPS_F, C_NPS_CL }},
 
 /* decode1<.f> */
-{ "decode1", 0x48038040, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "decode1", 0x48038040, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
 
 /* decode1.cl<.f> */
-{ "decode1", 0x48038060, 0xf80803e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS_SZ }, { C_NPS_CL, C_NPS_F }},
+{ "decode1", 0x48038060, 0xf80803e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS_SZ }, { C_NPS_CL, C_NPS_F }},
 
 /* fbset<.f> */
-{ "fbset", 0x48038000, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "fbset", 0x48038000, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
 
 /* fbclr<.f> */
-{ "fbclr", 0x48030000, 0xf80f83e0, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "fbclr", 0x48030000, 0xf80f83e0, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
 
 /* encode0<.f> */
-{ "encode0", 0x48040000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "encode0", 0x48040000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
 
 /* encode1<.f> */
-{ "encode1", 0x48048000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "encode1", 0x48048000, 0xf80f8000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
 
 /* mrgb - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
 /* mrgb.cl - 48 bit instruction, see arc_long_opcodes in arc-opc.c.  */
@@ -50,108 +50,108 @@
 /* mov4b.cl - 64 bit instruction, see arc_long_opcodes in arc-opc.c.  */
 
 /* rflt a,b,c   00111bbb00101110FBBBCCCCCCAAAAAA */
-{ "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { 0 }},
+{ "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }},
 
 /* rflt a,limm,c   0011111000101110F111CCCCCCAAAAAA */
-{ "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { 0 }},
+{ "rflt", 0x3e2e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { 0 }},
 
 /* rflt a,b,u6   00111bbb01101110FBBBuuuuuuAAAAAA */
-{ "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
+{ "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }},
 
 /* rflt 0,b,c   00111bbb00101110FBBBCCCCCC111110 */
-{ "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { 0 }},
+{ "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }},
 
 /* rflt 0,limm,c   0011111000101110F111CCCCCC111110 */
-{ "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { 0 }},
+{ "rflt", 0x3e2e703e, 0xfffff03f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { 0 }},
 
 /* rflt 0,b,u6   00111bbb01101110FBBBuuuuuu111110 */
-{ "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }},
+{ "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }},
 
 /* rflt 0,b,limm   00111bbb00101110FBBB111110111110 */
-{ "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { 0 }},
+{ "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }},
 
 /* rflt a,b,limm   00111bbb00101110FBBB111110AAAAAA */
-{ "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { 0 }},
+{ "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }},
 
 /* rflt a,limm,limm    0011111000101110F111111110AAAAAA */
-{ "rflt", 0x3e2e7f80, 0xffffffc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "rflt", 0x3e2e7f80, 0xffffffc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { 0 }},
 
 /* rflt a,limm,u6   0011111001101110F111uuuuuuAAAAAA */
-{ "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }},
+{ "rflt", 0x3e6e7000, 0xfffff000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, NPS_RFLT_UIMM6 }, { 0 }},
 
 /* rflt 0,limm,u6   0011111001101110F111uuuuuu111110 */
-{ "rflt", 0x3e6e703e, 0xfffff03f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, NPS_RFLT_UIMM6 }, { 0 }},
+{ "rflt", 0x3e6e703e, 0xfffff03f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, NPS_RFLT_UIMM6 }, { 0 }},
 
 /* crc16<.r> a,b,c  00111bbb00110011RBBBCCCCCCAAAAAA */
-{ "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { C_NPS_R }},
+{ "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
 
 /* crc16<.r> a,limm,c  0011111000110011R111CCCCCCAAAAAA */
-{ "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { C_NPS_R }},
+{ "crc16", 0x3e337000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }},
 
 /* crc16<.r> a,b,u6  00111bbb01110011RBBBuuuuuuAAAAAA */
-{ "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, UIMM6_20 }, { C_NPS_R }},
+{ "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
 
 /* crc16<.r> 0,b,c  00111bbb00110011RBBBCCCCCC111110 */
-{ "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { C_NPS_R }},
+{ "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
 
 /* crc16<.r> 0,limm,c  0011111000110011R111CCCCCC111110 */
-{ "crc16", 0x3e33703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { C_NPS_R }},
+{ "crc16", 0x3e33703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { C_NPS_R }},
 
 /* crc16<.r> 0,b,u6  00111bbb01110011RBBBuuuuuu111110 */
-{ "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_R }},
+{ "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }},
 
 /* crc16<.r> 0,b,limm  00111bbb00110011RBBB111110111110 */
-{ "crc16", 0x38330fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { C_NPS_R }},
+{ "crc16", 0x38330fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { C_NPS_R }},
 
 /* crc16<.r> a,b,limm  00111bbb00110011RBBB111110AAAAAA */
-{ "crc16", 0x38330f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { C_NPS_R }},
+{ "crc16", 0x38330f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { C_NPS_R }},
 
 /* crc16<.r> a,limm,limm  0011111000110011R111111110AAAAAA */
-{ "crc16", 0x3e337f80, 0xffff7fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { C_NPS_R }},
+{ "crc16", 0x3e337f80, 0xffff7fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_R }},
 
 /* crc16<.r> a,limm,u6  0011111001110011R111uuuuuuAAAAAA */
-{ "crc16", 0x3e737000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_R }},
+{ "crc16", 0x3e737000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_R }},
 
 /* crc16<.r> 0,limm,u6  0011111001110011R111uuuuuu111110 */
-{ "crc16", 0x3e73703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
+{ "crc16", 0x3e73703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
 
 /* crc32<.r> a,b,c             00111 bbb 00 110100 R BBB CCCCCC AAAAAA */
-{ "crc32", 0x38340000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, RC }, { C_NPS_R }},
+{ "crc32", 0x38340000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }},
 
 /* crc32<.r> a,limm,c          00111 110 00 110100 R 111 CCCCCC AAAAAA */
-{ "crc32", 0x3e347000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, RC }, { C_NPS_R }},
+{ "crc32", 0x3e347000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, RC }, { C_NPS_R }},
 
 /* crc32<.r> a,b,u6            00111 bbb 01 110100 R BBB uuuuuu AAAAAA */
-{ "crc32", 0x38740000, 0xf8ff0000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, UIMM6_20 }, { C_NPS_R }},
+{ "crc32", 0x38740000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }},
 
 /* crc32<.r> 0,b,c             00111 bbb 00 110100 R BBB CCCCCC 111110 */
-{ "crc32", 0x3834003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, RC }, { C_NPS_R }},
+{ "crc32", 0x3834003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }},
 
 /* crc32<.r> 0,limm,c          00111 110 00 110100 R 111 CCCCCC 111110 */
-{ "crc32", 0x3e34703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, RC }, { C_NPS_R }},
+{ "crc32", 0x3e34703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, RC }, { C_NPS_R }},
 
 /* crc32<.r> 0,b,u6            00111 bbb 01 110100 R BBB uuuuuu 111110 */
-{ "crc32", 0x3874003e, 0xf8ff003f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_R }},
+{ "crc32", 0x3874003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_R }},
 
 /* crc32<.r> 0,b,limm          00111 bbb 00 110100 R BBB 111110 111110 */
-{ "crc32", 0x38340fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, RB, LIMM }, { C_NPS_R }},
+{ "crc32", 0x38340fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { C_NPS_R }},
 
 /* crc32<.r> a,b,limm          00111 bbb 00 110100 R BBB 111110 AAAAAA */
-{ "crc32", 0x38340f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, RB, LIMM }, { C_NPS_R }},
+{ "crc32", 0x38340f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { C_NPS_R }},
 
 /* crc32<.r> a,limm,limm       00111 110 00 110100 R 111 111110 AAAAAA */
-{ "crc32", 0x3e347f80, 0xffff7fc0, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, LIMMdup }, { C_NPS_R }},
+{ "crc32", 0x3e347f80, 0xffff7fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_R }},
 
 /* crc32<.r> a,limm,u6         00111 110 01 110100 R 111 uuuuuu AAAAAA */
-{ "crc32", 0x3e747000, 0xffff7000, ARC_OPCODE_NPS400, BITOP, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_R }},
+{ "crc32", 0x3e747000, 0xffff7000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_R }},
 
 /* crc32<.r> 0,limm,u6         00111 110 01 110100 R 111 uuuuuu 111110 */
-{ "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_NPS400, BITOP, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
+{ "crc32", 0x3e74703e, 0xffff703f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_R }},
 
 /****                 Arithmetic & Logic Instructions                 ****/
 
 #define ADDB_LIKE(NAME,SUBOP2)                                          \
-  { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, NPS_ADDB_SIZE }, { C_NPS_F, C_NPS_SX }},
+  { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, NPS_ADDB_SIZE }, { C_NPS_F, C_NPS_SX }},
 
 ADDB_LIKE ("addb", 0)
 ADDB_LIKE ("subb", 4)
@@ -159,7 +159,7 @@ ADDB_LIKE ("adcb", 5)
 ADDB_LIKE ("sbcb", 6)
 
 #define ANDB_LIKE(NAME,SUBOP2,SIZE_OPERAND)                             \
-  { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, SIZE_OPERAND }, { C_NPS_F }},
+  { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, SIZE_OPERAND }, { C_NPS_F }},
 
 ANDB_LIKE ("andb", 1, NPS_ANDB_SIZE)
 ANDB_LIKE ("xorb", 2, NPS_ANDB_SIZE)
@@ -170,40 +170,40 @@ ANDB_LIKE ("shlb", 0xb, NPS_ANDB_SIZE)
 ANDB_LIKE ("shrb", 0xc, NPS_ANDB_SIZE)
 
 #define NOTB_LIKE(NAME,SUBOP2)                                          \
-  { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_ANDB_SIZE }, { C_NPS_F }},
+  { NAME, (0x48000000 | SUBOP2), 0xf80f001f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_ANDB_SIZE }, { C_NPS_F }},
 
 NOTB_LIKE ("notb", 0x9)
 NOTB_LIKE ("cntbb", 0xa)
 
 #define DIV_LIKE(NAME,DIV_MODE)                                          \
-  { NAME, (0x4800000d | DIV_MODE << 14), 0xf80fc3ff, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, }, { C_NPS_F }}, \
-  { NAME, (0x4800020d | DIV_MODE << 14), 0xf8efc21f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_DIV_UIMM4, NPS_SRC1_POS }, { C_NPS_F }},
+  { NAME, (0x4800000d | DIV_MODE << 14), 0xf80fc3ff, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC1_POS, NPS_SRC2_POS, }, { C_NPS_F }}, \
+  { NAME, (0x4800020d | DIV_MODE << 14), 0xf8efc21f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_DIV_UIMM4, NPS_SRC1_POS }, { C_NPS_F }},
 
 DIV_LIKE ("div", 0x1)
 DIV_LIKE ("mod", 0x2)
 DIV_LIKE ("divm", 0x0)
 
-{ "qcmp", 0x4810000e, 0xf81f001e, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, NPS_QCMP_M3 }, { C_NPS_AR_AL }},
-{ "qcmp", 0x481001ee, 0xf81f01fe, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2 }, { C_NPS_AR_AL }},
-{ "qcmp", 0x481001ee, 0xf81f81fe, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1  }, { C_NPS_AR_AL }},
-{ "qcmp", 0x481001ee, 0xf81fc1fe, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE  }, { C_NPS_AR_AL }},
+{ "qcmp", 0x4810000e, 0xf81f001e, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, NPS_QCMP_M3 }, { C_NPS_AR_AL }},
+{ "qcmp", 0x481001ee, 0xf81f01fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2 }, { C_NPS_AR_AL }},
+{ "qcmp", 0x481001ee, 0xf81f81fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE, NPS_QCMP_M1  }, { C_NPS_AR_AL }},
+{ "qcmp", 0x481001ee, 0xf81fc1fe, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS, NPS_QCMP_SIZE  }, { C_NPS_AR_AL }},
 
-{ "calcsd", 0x48000010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
-{ "calcxd", 0x48004010, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
+{ "calcsd", 0x48000010, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
+{ "calcxd", 0x48004010, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_CALC_ENTRY_SIZE }, { C_NPS_F }},
 
-{ "calcbsd", 0x48000030, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
-{ "calcbxd", 0x48004030, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calcbsd", 0x48000030, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calcbxd", 0x48004030, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 
-{ "calckey", 0x48000050, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
-{ "calcxkey", 0x48004050, 0xf80f407f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calckey", 0x48000050, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "calcxkey", 0x48004050, 0xf80f407f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 
-{ "mxb", 0x580b0000, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
-{ "mxb", 0x580b8000, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
-{ "imxb", 0x580b0001, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
-{ "imxb", 0x580b8001, 0xf81f8007, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
+{ "mxb", 0x580b0000, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
+{ "mxb", 0x580b8000, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
+{ "imxb", 0x580b0001, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR }, { 0 }},
+{ "imxb", 0x580b8001, 0xf81f8007, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_FIELD_START_POS, NPS_FIELD_SIZE, NPS_SHIFT_FACTOR, NPS_BITS_TO_SCRAMBLE }, { C_NPS_S }},
 
 #define ADDL_LIKE(NAME,SUBOP2,SHIM)                                     \
-  { NAME, (0x48000000 | (SUBOP2 << 16)), 0xf80f0000, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST, NPS_R_SRC1, SHIM }, { C_NPS_F }},
+  { NAME, (0x48000000 | (SUBOP2 << 16)), 0xf80f0000, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST, NPS_R_SRC1, SHIM }, { C_NPS_F }},
 
 ADDL_LIKE ("addl", 0xA, NPS_SIMM16)
 ADDL_LIKE ("subl", 0xB, NPS_SIMM16)
@@ -211,190 +211,190 @@ ADDL_LIKE ("orl", 0xC, NPS_UIMM16)
 ADDL_LIKE ("andl", 0xD, NPS_UIMM16)
 ADDL_LIKE ("xorl", 0xE, NPS_UIMM16)
 
-{ "andab", 0x48000011, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
-{ "andab", 0x48008011, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
-{ "orab", 0x48000012, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
-{ "orab", 0x48008012, 0xf80f801f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "andab", 0x48000011, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "andab", 0x48008011, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "orab", 0x48000012, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
+{ "orab", 0x48008012, 0xf80f801f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_SRC2_POS_5B, NPS_BITOP_SIZE }, { C_NPS_F } },
 
-{ "lbdsize", 0x382f0005, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { RB, RC }, { C_F }},
+{ "lbdsize", 0x382f0005, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { RB, RC }, { C_F }},
 
-{ "bdlen", 0x48000013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
-{ "bdlen", 0x48004013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
-{ "bdlen", 0x48008013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
-{ "bdlen", 0x4800c013, 0xf80fc01f, ARC_OPCODE_NPS400, ARITH, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "bdlen", 0x48000013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
+{ "bdlen", 0x48004013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
+{ "bdlen", 0x48008013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BDLEN_MAX_LEN }, { C_NPS_F }},
+{ "bdlen", 0x4800c013, 0xf80fc01f, ARC_OPCODE_ARC700, ARITH, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B }, { C_NPS_F }},
 
 /* csma a,b,c   00111bbb00100001FBBBCCCCCCAAAAAA */
-{ "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { 0 }},
+{ "csma", 0x382a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }},
 
 /* csma a,limm,c   0011111000100001F111CCCCCCAAAAAA */
-{ "csma", 0x3e2a7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+{ "csma", 0x3e2a7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { 0 }},
 
 /* csma a,b,u6   00111bbb01100001FBBBuuuuuuAAAAAA */
-{ "csma", 0x386a0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "csma", 0x386a0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { 0 }},
 
 /* csma 0,b,c   00111bbb00100001FBBBCCCCCC111110 */
-{ "csma", 0x382a003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+{ "csma", 0x382a003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { 0 }},
 
 /* csma 0,limm,c   0011111000100001F111CCCCCC111110 */
-{ "csma", 0x3e2a703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+{ "csma", 0x3e2a703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { 0 }},
 
 /* csma 0,b,u6   00111bbb01100001FBBBuuuuuu111110 */
-{ "csma", 0x386a003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+{ "csma", 0x386a003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { 0 }},
 
 /* csma 0,b,limm   00111bbb00100001FBBB111110111110 */
-{ "csma", 0x382a0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+{ "csma", 0x382a0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { 0 }},
 
 /* csma a,b,limm   00111bbb00100001FBBB111110AAAAAA */
-{ "csma", 0x382a0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+{ "csma", 0x382a0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { 0 }},
 
 /* csma a,limm,limm    0011111000100001F111111110AAAAAA */
-{ "csma", 0x3e2a7f80, 0xffffffc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "csma", 0x3e2a7f80, 0xffffffc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { 0 }},
 
 /* csma a,limm,u6   0011111001100001F111uuuuuuAAAAAA */
-{ "csma", 0x3e6a7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "csma", 0x3e6a7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { 0 }},
 
 /* csma 0,limm,u6   0011111001100001F111uuuuuu111110 */
-{ "csma", 0x3e6a703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+{ "csma", 0x3e6a703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { 0 }},
 
 /* csms a,b,c   00111bbb00101100FBBBCCCCCCAAAAAA */
-{ "csms", 0x382c0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { 0 }},
+{ "csms", 0x382c0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { 0 }},
 
 /* csma a,limm,c   0011111000101100F111CCCCCCAAAAAA */
-{ "csms", 0x3e2c7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { 0 }},
+{ "csms", 0x3e2c7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { 0 }},
 
 /* csms a,b,u6   00111bbb01101100FBBBuuuuuuAAAAAA */
-{ "csms", 0x386c0000, 0xf8ff8000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { 0 }},
+{ "csms", 0x386c0000, 0xf8ff8000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { 0 }},
 
 /* csms 0,b,c   00111bbb00101100FBBBCCCCCC111110 */
-{ "csms", 0x382c003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { 0 }},
+{ "csms", 0x382c003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { 0 }},
 
 /* csms 0,limm,c   0011111000101100F111CCCCCC111110 */
-{ "csms", 0x3e2c703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { 0 }},
+{ "csms", 0x3e2c703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { 0 }},
 
 /* csms 0,b,u6   00111bbb01101100FBBBuuuuuu111110 */
-{ "csms", 0x386c003e, 0xf8ff803f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { 0 }},
+{ "csms", 0x386c003e, 0xf8ff803f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { 0 }},
 
 /* csms 0,b,limm   00111bbb00101100FBBB111110111110 */
-{ "csms", 0x382c0fbe, 0xf8ff8fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { 0 }},
+{ "csms", 0x382c0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { 0 }},
 
 /* csms a,b,limm   00111bbb00101100FBBB111110AAAAAA */
-{ "csms", 0x382c0f80, 0xf8ff8fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { 0 }},
+{ "csms", 0x382c0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { 0 }},
 
 /* csms a,limm,limm   0011111000101100F111111110AAAAAA */
-{ "csms", 0x3e2c7f80, 0xffffffc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { 0 }},
+{ "csms", 0x3e2c7f80, 0xffffffc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { 0 }},
 
 /* csms a,limm,u6   0011111001101100F111uuuuuuAAAAAA */
-{ "csms", 0x3e6c7000, 0xfffff000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { 0 }},
+{ "csms", 0x3e6c7000, 0xfffff000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { 0 }},
 
 /* csms 0,limm,u6   0011111001101100F111uuuuuu111110 */
-{ "csms", 0x3e6c703e, 0xfffff03f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { 0 }},
+{ "csms", 0x3e6c703e, 0xfffff03f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { 0 }},
 
 /* cbba a,b,c   00111bbb00101101FBBBCCCCCCAAAAAA */
-{ "cbba", 0x382d0000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_F }},
+{ "cbba", 0x382d0000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_F }},
 
 /* cbba a,limm,c    0011111000101101F111CCCCCCAAAAAA */
-{ "cbba", 0x3e2d7000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { C_F }},
+{ "cbba", 0x3e2d7000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { C_F }},
 
 /* cbba a,b,u6   00111bbb01101101FBBBuuuuuuAAAAAA */
-{ "cbba", 0x386d0000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "cbba", 0x386d0000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 
 /* cbba 0,b,c   00111bbb00101101FBBBCCCCCC111110 */
-{ "cbba", 0x382d003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { C_F }},
+{ "cbba", 0x382d003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { C_F }},
 
 /* cbba 0,limm,c   0011111000101101F111CCCCCC111110 */
-{ "cbba", 0x3e2d703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { C_F }},
+{ "cbba", 0x3e2d703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { C_F }},
 
 /* cbba 0,b,u6   00111bbb01101101FBBBuuuuuu111110 */
-{ "cbba", 0x386d003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "cbba", 0x386d003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 
 /* cbba 0,b,limm   00111bbb00101101FBBB111110111110 */
-{ "cbba", 0x382d0fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { C_F }},
+{ "cbba", 0x382d0fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { C_F }},
 
 /* cbba a,b,limm   00111bbb00101101FBBB111110AAAAAA */
-{ "cbba", 0x382d0f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { C_F }},
+{ "cbba", 0x382d0f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { C_F }},
 
 /* cbba a,limm,limm   0011111000101101F111111110AAAAAA */
-{ "cbba", 0x3e2d7f80, 0xffff7fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "cbba", 0x3e2d7f80, 0xffff7fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 
 /* cbba a,limm,u6   0011111001101101F111uuuuuuAAAAAA */
-{ "cbba", 0x3e6d7000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "cbba", 0x3e6d7000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 
 /* cbba 0,limm,u6   0011111001101101F111uuuuuu111110 */
-{ "cbba", 0x3e6d703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+{ "cbba", 0x3e6d703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 
 /* zncv<.rd|.wr> a,b,c   00111bbb001101010BBBCCCCCCAAAAAA */
-{ "zncv", 0x38350000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_NPS_ZNCV }},
+{ "zncv", 0x38350000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> a,b,u6   00111bbb011101010BBBuuuuuuAAAAAA */
-{ "zncv", 0x38750000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, UIMM6_20}, { C_NPS_ZNCV }},
+{ "zncv", 0x38750000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, UIMM6_20}, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> b,b,s12   00111bbb101101010BBBssssssSSSSSS */
-{ "zncv", 0x38b50000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RB, RBdup, SIMM12_20 }, { C_NPS_ZNCV }},
+{ "zncv", 0x38b50000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RB, RBdup, SIMM12_20 }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> a,b,limm   00111bbb001101010BBB111110AAAAAA */
-{ "zncv", 0x38350f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, LIMM }, { C_NPS_ZNCV }},
+{ "zncv", 0x38350f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, LIMM }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> a,limm,c   00111110001101010111CCCCCCAAAAAA */
-{ "zncv", 0x3e357000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, RC }, { C_NPS_ZNCV }},
+{ "zncv", 0x3e357000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, RC }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> a,limm,u6   00111110011101010111uuuuuuAAAAAA */
-{ "zncv", 0x3e757000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
+{ "zncv", 0x3e757000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> a,limm,limm   00111110001101010111111110AAAAAA */
-{ "zncv", 0x3e357f80, 0xffff7fc0, ARC_OPCODE_NPS400, ARITH, NONE, { RA, LIMM, LIMMdup }, { C_NPS_ZNCV }},
+{ "zncv", 0x3e357f80, 0xffff7fc0, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, LIMM, LIMMdup }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> 0,b,c 00111bbb001101010BBBCCCCCC111110 */
-{ "zncv", 0x3835003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, RC }, { C_NPS_ZNCV }},
+{ "zncv", 0x3835003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, RC }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> 0,b,u6   00111bbb011101010BBBuuuuuu111110 */
-{ "zncv", 0x3875003e, 0xf8ff003f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, UIMM6_20 }, { C_NPS_ZNCV }},
+{ "zncv", 0x3875003e, 0xf8ff003f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, UIMM6_20 }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> 0,b,limm   00111bbb001101010BBB111110111110 */
-{ "zncv", 0x38350fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, RB, LIMM }, { C_NPS_ZNCV }},
+{ "zncv", 0x38350fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, RB, LIMM }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> 0,limm,c   00111110001101010111CCCCCC111110 */
-{ "zncv", 0x3e35703e, 0xffff703f, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, RC }, { C_NPS_ZNCV }},
+{ "zncv", 0x3e35703e, 0xffff703f, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, RC }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> 0,limm,u6   00111110011101010111uuuuuu111110 */
-{ "zncv", 0x3e75703e, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
+{ "zncv", 0x3e75703e, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, UIMM6_20 }, { C_NPS_ZNCV }},
 
 /* zncv<.rd|.wr> 0,limm,s12   00111110101101010111ssssssSSSSSS */
-{ "zncv", 0x3eb57000, 0xffff7000, ARC_OPCODE_NPS400, ARITH, NONE, { ZA, LIMM, SIMM12_20 }, { C_NPS_ZNCV }},
+{ "zncv", 0x3eb57000, 0xffff7000, ARC_OPCODE_ARC700, ARITH, NPS400, { ZA, LIMM, SIMM12_20 }, { C_NPS_ZNCV }},
 
 /* hofs a,b,c */
-{ "hofs", 0x38360000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, RC }, { C_F }},
+{ "hofs", 0x38360000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, RC }, { C_F }},
 
 /* hofs a,b,min_hofs,psbc */
-{ "hofs", 0x38760000, 0xf8ff0000, ARC_OPCODE_NPS400, ARITH, NONE, { RA, RB, NPS_MIN_HOFS, NPS_PSBC }, { C_F }},
+{ "hofs", 0x38760000, 0xf8ff0000, ARC_OPCODE_ARC700, ARITH, NPS400, { RA, RB, NPS_MIN_HOFS, NPS_PSBC }, { C_F }},
 
 /****                  Protocol Decoder Instructions                  ****/
 
 /* dctcp b,c  00111bbb001011110bbbcccccc000000 */
-{ "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }},
+{ "dctcp", 0x382f0000, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }},
 
 /* dcip a,b,c  00111bbb001011110bbbccccccaaaaaa */
-{ "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }},
+{ "dcip", 0x38290000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }},
 
 /* dcet b,c  00111bbb001011110bbbcccccc000010 */
-{ "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_NPS400, NET, NONE, { RB, RC }, { 0 }},
+{ "dcet", 0x382f0002, 0xf8ff803f, ARC_OPCODE_ARC700, NET, NPS400, { RB, RC }, { 0 }},
 
 /* dcet a,b,c  00111bbb001000000bbbccccccaaaaaa */
-{ "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_NPS400, NET, NONE, { RA, RB, RC }, { 0 }},
+{ "dcet", 0x38200000, 0xf8ff8000, ARC_OPCODE_ARC700, NET, NPS400, { RA, RB, RC }, { 0 }},
 
 /****                        ACL Instructions                         ****/
 
 /* dcacl<.f> a,b,c  00111bbb001001010bbbccccccaaaaaa */
-{ "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_NPS400, ACL, NONE, { RA, RB, RC }, { C_F }},
+{ "dcacl", 0x38250000, 0xf8ff0000, ARC_OPCODE_ARC700, ACL, NPS400, { RA, RB, RC }, { C_F }},
 
 /****                        DPI Instructions                         ****/
 
 /* hash dst,src1,src2,width,perm,nonlinear,basemat */
-{ "hash", 0x58180000, 0xf81f0000, ARC_OPCODE_NPS400, DPI, NONE, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_PERM, NPS_HASH_NONLINEAR, NPS_HASH_BASEMAT }, { 0 }},
+{ "hash", 0x58180000, 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_PERM, NPS_HASH_NONLINEAR, NPS_HASH_BASEMAT }, { 0 }},
 
 /* hash.pN dst,src1,src2,width,len,ofs,basemat */
 
 #define HASH_P(FUNC, SUBOP2)                                            \
-  { "hash", (0x58100000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_NPS400, DPI, NONE, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_LEN, NPS_HASH_OFS, NPS_HASH_BASEMAT2 }, { C_NPS_P##FUNC }},
+  { "hash", (0x58100000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_HASH_WIDTH, NPS_HASH_LEN, NPS_HASH_OFS, NPS_HASH_BASEMAT2 }, { C_NPS_P##FUNC }},
 
 HASH_P(0, 0x9)
 HASH_P(1, 0xA)
@@ -402,149 +402,149 @@ HASH_P(2, 0xB)
 HASH_P(3, 0xC)
 
 /* tr<.f> a,b,c   00111bbb00100001FBBBCCCCCCAAAAAA */
-{ "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, RC }, { C_F }},
+{ "tr", 0x38210000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }},
 
 /* tr<.f> a,limm,c   0011111000100001F111CCCCCCAAAAAA */
-{ "tr", 0x3e217000, 0xffff7000, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, RC }, { C_F }},
+{ "tr", 0x3e217000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }},
 
 /* tr<.f> a,b,u6   00111bbb01100001FBBBuuuuuuAAAAAA */
-{ "tr", 0x38610000, 0xf8ff0000, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "tr", 0x38610000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 
 /* tr<.f> 0,b,c   00111bbb00100001FBBBCCCCCC111110 */
-{ "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, RC }, { C_F }},
+{ "tr", 0x3821003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }},
 
 /* tr<.f> 0,limm,c   0011111000100001F111CCCCCC111110 */
-{ "tr", 0x3e21703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, RC }, { C_F }},
+{ "tr", 0x3e21703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }},
 
 /* tr<.f> 0,b,u6   00111bbb01100001FBBBuuuuuu111110 */
-{ "tr", 0x3861003e, 0xf8ff003f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "tr", 0x3861003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 
 /* tr<.f> 0,b,limm   00111bbb00100001FBBB111110111110 */
-{ "tr", 0x38210fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, LIMM }, { C_F }},
+{ "tr", 0x38210fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }},
 
 /* tr<.f> a,b,limm   00111bbb00100001FBBB111110AAAAAA */
-{ "tr", 0x38210f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, LIMM }, { C_F }},
+{ "tr", 0x38210f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }},
 
 /* tr<.f> a,limm,limm   0011111000100001F111111110AAAAAA */
-{ "tr", 0x3e217f80, 0xffff7fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "tr", 0x3e217f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 
 /* tr<.f> a,limm,u6   0011111001100001F111uuuuuuAAAAAA */
-{ "tr", 0x3e617000, 0xffff7000, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "tr", 0x3e617000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 
 /* tr<.f> 0,limm,u6   0011111001100001F111uuuuuu111110 */
-{ "tr", 0x3e61703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+{ "tr", 0x3e61703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 
 /* utf8 a,b,c       00111bbb00100011FBBBCCCCCCAAAAAA */
-{ "utf8", 0x38220000, 0xf8ff0000, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, RC }, { C_F }},
+{ "utf8", 0x38220000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }},
 
 /* utf8 a,limm,c    0011111000100011F111CCCCCCAAAAAA */
-{ "utf8", 0x3e227000, 0xffff7000, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, RC }, { C_F }},
+{ "utf8", 0x3e227000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }},
 
 /* utf8 a,b,u6      00111bbb01100011FBBBuuuuuuAAAAAA */
-{ "utf8", 0x38620000, 0xf8ff0000, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "utf8", 0x38620000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 
 /* utf8 0,b,c       00111bbb00100011FBBBCCCCCC111110 */
-{ "utf8", 0x3822003e, 0xf8ff003f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, RC }, { C_F }},
+{ "utf8", 0x3822003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }},
 
 /* utf8 0,limm,c    0011111000100011F111CCCCCC111110 */
-{ "utf8", 0x3e22703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, RC }, { C_F }},
+{ "utf8", 0x3e22703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }},
 
 /* utf8 0,b,u6      00111bbb01100011FBBBuuuuuu111110 */
-{ "utf8", 0x3862003e, 0xf8ff003f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "utf8", 0x3862003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 
 /* utf8 0,b,limm    00111bbb00100011FBBB111110111110 */
-{ "utf8", 0x38220fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, LIMM }, { C_F }},
+{ "utf8", 0x38220fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }},
 
 /* utf8 a,b,limm    00111bbb00100011FBBB111110AAAAAA */
-{ "utf8", 0x38220f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, LIMM }, { C_F }},
+{ "utf8", 0x38220f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }},
 
 /* utf8 a,limm,limm 0011111000100011F111111110AAAAAA */
-{ "utf8", 0x3e227f80, 0xffff7fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "utf8", 0x3e227f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 
 /* utf8 a,limm,u6   0011111001100011F111uuuuuuAAAAAA */
-{ "utf8", 0x3e627000, 0xffff7000, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "utf8", 0x3e627000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 
 /* utf8 0,limm,u6   0011111001100011F111uuuuuu111110 */
-{ "utf8", 0x3e62703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+{ "utf8", 0x3e62703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 
 /* e4by dst,src1,src2,index0,index1,index2,index3 */
-{ "e4by", 0x581d0000, 0xf81f0000, ARC_OPCODE_NPS400, DPI, NONE, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_E4BY_INDEX0, NPS_E4BY_INDEX1, NPS_E4BY_INDEX2, NPS_E4BY_INDEX3 }, { 0 }},
+{ "e4by", 0x581d0000, 0xf81f0000, ARC_OPCODE_ARC700, DPI, NPS400, { NPS_DPI_DST, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_E4BY_INDEX0, NPS_E4BY_INDEX1, NPS_E4BY_INDEX2, NPS_E4BY_INDEX3 }, { 0 }},
 
 /* addf<.f> a,b,c       00111bbb00100011FBBBCCCCCCAAAAAA */
-{ "addf", 0x38230000, 0xf8ff0000, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, RC }, { C_F }},
+{ "addf", 0x38230000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, RC }, { C_F }},
 
 /* addf<.f> a,limm,c    0011111000100011F111CCCCCCAAAAAA */
-{ "addf", 0x3e237000, 0xffff7000, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, RC }, { C_F }},
+{ "addf", 0x3e237000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, RC }, { C_F }},
 
 /* addf<.f> a,b,u6      00111bbb01100011FBBBuuuuuuAAAAAA */
-{ "addf", 0x38630000, 0xf8ff0000, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, UIMM6_20 }, { C_F }},
+{ "addf", 0x38630000, 0xf8ff0000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, UIMM6_20 }, { C_F }},
 
 /* addf<.f> 0,b,c       00111bbb00100011FBBBCCCCCC111110 */
-{ "addf", 0x3823003e, 0xf8ff003f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, RC }, { C_F }},
+{ "addf", 0x3823003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, RC }, { C_F }},
 
 /* addf<.f> 0,limm,c    0011111000100011F111CCCCCC111110 */
-{ "addf", 0x3e23703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, RC }, { C_F }},
+{ "addf", 0x3e23703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, RC }, { C_F }},
 
 /* addf<.f> 0,b,u6      00111bbb01100011FBBBuuuuuu111110 */
-{ "addf", 0x3863003e, 0xf8ff003f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, UIMM6_20 }, { C_F }},
+{ "addf", 0x3863003e, 0xf8ff003f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, UIMM6_20 }, { C_F }},
 
 /* addf<.f> 0,b,limm    00111bbb00100011FBBB111110111110 */
-{ "addf", 0x38230fbe, 0xf8ff0fff, ARC_OPCODE_NPS400, DPI, NONE, { ZA, RB, LIMM }, { C_F }},
+{ "addf", 0x38230fbe, 0xf8ff0fff, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, RB, LIMM }, { C_F }},
 
 /* addf<.f> a,b,limm    00111bbb00100011FBBB111110AAAAAA */
-{ "addf", 0x38230f80, 0xf8ff0fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, RB, LIMM }, { C_F }},
+{ "addf", 0x38230f80, 0xf8ff0fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, RB, LIMM }, { C_F }},
 
 /* addf<.f> a,limm,limm 0011111000100011F111111110AAAAAA */
-{ "addf", 0x3e237f80, 0xffff7fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, LIMMdup }, { C_F }},
+{ "addf", 0x3e237f80, 0xffff7fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, LIMMdup }, { C_F }},
 
 /* addf<.f> a,limm,u6   0011111001100011F111uuuuuuAAAAAA */
-{ "addf", 0x3e637000, 0xffff7000, ARC_OPCODE_NPS400, DPI, NONE, { RA, LIMM, UIMM6_20 }, { C_F }},
+{ "addf", 0x3e637000, 0xffff7000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, LIMM, UIMM6_20 }, { C_F }},
 
 /* addf<.f> 0,limm,u6   0011111001100011F111uuuuuu111110 */
-{ "addf", 0x3e63703e, 0xffff703f, ARC_OPCODE_NPS400, DPI, NONE, { ZA, LIMM, UIMM6_20 }, { C_F }},
+{ "addf", 0x3e63703e, 0xffff703f, ARC_OPCODE_ARC700, DPI, NPS400, { ZA, LIMM, UIMM6_20 }, { C_F }},
 
 /* ldbit<.x2|.x4>.di<.cl> a,[b]       00010bbb00000000SBBB10011XAAAAAA */
-{ "ldbit", 0x10000980, 0xf8ff8980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
+{ "ldbit", 0x10000980, 0xf8ff8980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 
 /* ldbit<.x2|.x4>.di<.cl> a,[b,s9]    00010bbbssssssssSBBB10011XAAAAAA */
-{ "ldbit", 0x10000980, 0xf8000980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
+{ "ldbit", 0x10000980, 0xf8000980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 
 /* ldbit<.x2|.x4>.di<.cl> a,[limm]    0001011000000000011110011XAAAAAA */
-{ "ldbit", 0x16007980, 0xfffff980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
+{ "ldbit", 0x16007980, 0xfffff980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 
 /* ldbit<.x2|.x4>.di<.cl> a,[limm,s9] 00010110ssssssssS11110011XAAAAAA */
-{ "ldbit", 0x16007980, 0xff007980, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
+{ "ldbit", 0x16007980, 0xff007980, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, SIMM9_8, BRAKETdup }, { C_NPS_LDBIT_X_1, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL1 }},
 
 /* ldbit<.x2|.x4>.di<.cl> a,[b,c]     00100bbb0011011X1BBBCCCCCCAAAAAA */
-{ "ldbit", 0x20368000, 0xf83e8000, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
+{ "ldbit", 0x20368000, 0xf83e8000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
 
 /* ldbit<.x2|.x4>.di<.cl> a,[b,limm]  00100bbb0011011X1BBB111110AAAAAA */
-{ "ldbit", 0x20368f80, 0xf83e8fc0, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
+{ "ldbit", 0x20368f80, 0xf83e8fc0, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, RB, LIMM, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
 
 /* ldbit<.x2|.x4>.di<.cl> a,[limm,c]  001001100011011X1111CCCCCCAAAAAA */
-{ "ldbit", 0x2636f000, 0xff3ef000, ARC_OPCODE_NPS400, DPI, NONE, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
+{ "ldbit", 0x2636f000, 0xff3ef000, ARC_OPCODE_ARC700, DPI, NPS400, { RA, BRAKET, LIMM, RC, BRAKETdup }, { C_NPS_LDBIT_X_2, C_NPS_LDBIT_DI, C_NPS_LDBIT_CL2 }},
 
 /****                  Pipeline Control Instructions                  ****/
 
 /* schd<.rw|.rd> */
-{ "schd", 0x3e6f7004, 0xffffff7f, ARC_OPCODE_NPS400, CONTROL, NONE, { 0 }, { C_NPS_SCHD_RW }},
+{ "schd", 0x3e6f7004, 0xffffff7f, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SCHD_RW }},
 
 /* schd.wft.<.ie1|.ie2|.ie12> */
-{ "schd", 0x3e6f7044, 0xfffffcff, ARC_OPCODE_NPS400, CONTROL, NONE, { 0 }, { C_NPS_SCHD_TRIG, C_NPS_SCHD_IE }},
+{ "schd", 0x3e6f7044, 0xfffffcff, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SCHD_TRIG, C_NPS_SCHD_IE }},
 
 /* sync<.rd|.wr> */
-{ "sync", 0x3e6f703f, 0xffffffbf, ARC_OPCODE_NPS400, CONTROL, NONE, { 0 }, { C_NPS_SYNC }},
+{ "sync", 0x3e6f703f, 0xffffffbf, ARC_OPCODE_ARC700, CONTROL, NPS400, { 0 }, { C_NPS_SYNC }},
 
 /* hwscd.off B */
-{ "hwschd", 0x386f00bf, 0xf8ff8fff, ARC_OPCODE_NPS400, CONTROL, NONE, { RB }, { C_NPS_HWS_OFF }},
+{ "hwschd", 0x386f00bf, 0xf8ff8fff, ARC_OPCODE_ARC700, CONTROL, NPS400, { RB }, { C_NPS_HWS_OFF }},
 
 /* hwscd.restore 0,C */
-{ "hwschd", 0x3e6f7003, 0xfffff03f, ARC_OPCODE_NPS400, CONTROL, NONE, { ZA, RC }, { C_NPS_HWS_RESTORE }},
+{ "hwschd", 0x3e6f7003, 0xfffff03f, ARC_OPCODE_ARC700, CONTROL, NPS400, { ZA, RC }, { C_NPS_HWS_RESTORE }},
 
 /****      Load / Store From (0x57f00000 + Offset) Instructions       ****/
 
 #define XLDST_LIKE(NAME,SUBOP2)                                          \
-  { NAME, (0x58000000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_NPS400, MEMORY, NONE, { NPS_R_DST, BRAKET, NPS_XLDST_UIMM16, BRAKETdup }, { 0 }},
+  { NAME, (0x58000000 | (SUBOP2 << 16)), 0xf81f0000, ARC_OPCODE_ARC700, MEMORY, NPS400, { NPS_R_DST, BRAKET, NPS_XLDST_UIMM16, BRAKETdup }, { 0 }},
 
 XLDST_LIKE("xldb", 0x8)
 XLDST_LIKE("xldw", 0x9)

diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 25db8684ca3b66a941495e14ba5e880478f11abf..df18167e1a6d061d89b0198b43d4590a75ad5b4c 100644 (file)
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -2486,59 +2486,59 @@ const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
 const struct arc_long_opcode arc_long_opcodes[] =
   {
     /* mrgb - (48 bit instruction).  */
-    { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
+    { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
       0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
 
     /* mrgb.cl - (48 bit instruction).  */
-    { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
+    { { "mrgb", 0x5803, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
       0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_SRC_POS1, NPS_BITOP_SIZE1, NPS_BITOP_DST_POS2, NPS_BITOP_SRC_POS2, NPS_BITOP_SIZE2 }},
 
     /* mov2b - (48 bit instruction).  */
-    { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
+    { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
       0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
 
     /* mov2b.cl - (48 bit instruction).  */
-    { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
+    { { "mov2b", 0x5800, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
       0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2 }},
 
     /* ext4 - (48 bit instruction).  */
-    { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
+    { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
       0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
 
     /* ext4.cl - (48 bit instruction).  */
-    { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
+    { { "ext4b", 0x5801, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
       0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_INS_EXT, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2 }},
 
     /* ins4 - (48 bit instruction).  */
-    { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
+    { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC1_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { 0 }},
       0x00000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
 
     /* ins4.cl - (48 bit instruction).  */
-    { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
+    { { "ins4b", 0x5802, 0xf81f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B_SHORT, NPS_R_SRC2_3B_SHORT,  IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
       0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_SRC_POS1, NPS_BITOP_SRC_POS2, NPS_BITOP_DST_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_INS_EXT }},
 
     /* mov3b - (64 bit instruction).  */
-    { { "mov3b", 0x58100000, 0xf81f801f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
+    { { "mov3b", 0x58100000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
       0x80000000, 0x80000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
 
     /* mov4b - (64 bit instruction).  */
-    { { "mov4b", 0x58100000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
+    { { "mov4b", 0x58100000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
       0x00000000, 0x00000000, { IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
 
     /* mov3bcl - (64 bit instruction).  */
-    { { "mov3bcl", 0x58110000, 0xf81f801f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
+    { { "mov3bcl", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { 0 }},
       0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
 
     /* mov4bcl - (64 bit instruction).  */
-    { { "mov4bcl", 0x58110000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
+    { { "mov4bcl", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { 0 }},
       0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
 
     /* mov3b.cl - (64 bit instruction).  */
-    { { "mov3b", 0x58110000, 0xf81f801f, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
+    { { "mov3b", 0x58110000, 0xf81f801f, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3_POS4, IGNORED, IGNORED, LIMM }, { C_NPS_CL }},
       0x80000000, 0x80000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3 }},
 
     /* mov4b.cl - (64 bit instruction).  */
-    { { "mov4b", 0x58110000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { C_NPS_CL }},
+    { { "mov4b", 0x58110000, 0xf81f0000, ARC_OPCODE_ARC700, BITOP, NPS400, { NPS_R_DST_3B, NPS_R_SRC2_3B, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, IGNORED, NPS_BITOP_DST_POS3, IGNORED, IGNORED, NPS_BITOP_DST_POS4, NPS_BITOP_MOD4_LSB, NPS_BITOP_SRC_POS4, LIMM }, { C_NPS_CL }},
       0x00000000, 0x00000000, { IGNORED, IGNORED, NPS_BITOP_DST_POS1, NPS_BITOP_MOD1, NPS_BITOP_SRC_POS1, NPS_BITOP_DST_POS2, NPS_BITOP_MOD2, NPS_BITOP_SRC_POS2, IGNORED, NPS_BITOP_MOD3, NPS_BITOP_SRC_POS3, IGNORED, NPS_BITOP_MOD4_MSB, IGNORED}},
 };