Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
    Hand merge.

--HG--
extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558

diff --cc configs/example/fs.py
Simple merge

diff --cc configs/example/se.py
Simple merge

diff --cc src/cpu/o3/fetch_impl.hh
Simple merge

diff --cc src/cpu/o3/lsq_unit.hh
Simple merge

diff --cc src/cpu/o3/lsq_unit_impl.hh
index dc1a99d878653f70116331d6da7a1f59b793202e,63ffcece1b605982a3ea7847b8eb8b5309a86ea6..3f9db912f455ffa1816d8b6a4b61a6964cb1793a
--- 1/src/cpu/o3/lsq_unit_impl.hh
--- 2/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@@ -608,13 -608,13 +608,13 @@@ LSQUnit<Impl>::writebackStores(
  
          DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
                  "to Addr:%#x, data:%#x [sn:%lli]\n",
 -                storeWBIdx, storeQueue[storeWBIdx].inst->readPC(),
 +                storeWBIdx, inst->readPC(),
                  req->getPaddr(), *(inst->memData),
 -                storeQueue[storeWBIdx].inst->seqNum);
 +                inst->seqNum);
  
          // @todo: Remove this SC hack once the memory system handles it.
-         if (req->getFlags() & LOCKED) {
-             if (req->getFlags() & UNCACHEABLE) {
+         if (req->isLocked()) {
+             if (req->isUncacheable()) {
                  req->setScResult(2);
              } else {
                  if (cpu->lockFlag) {

diff --cc src/cpu/simple/timing.cc
Simple merge

diff --cc src/cpu/simple/timing.hh
index 8a20d1cfe3c5e73f7c82430d3f42924287f8ae62,18e13aeb22fbd1fd2498706f9a5c629d78e9d995..988ddeded88a6de704256c1ce9ce625250c62338
--- 1/src/cpu/simple/timing.hh
--- 2/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@@ -166,7 -166,7 +166,8 @@@ class TimingSimpleCPU : public BaseSimp
      Packet *ifetch_pkt;
      Packet *dcache_pkt;
  
+     int cpu_id;
 +    Tick previousTick;
  
    public:
  

diff --cc src/mem/physical.cc
index 0580954de1c8aee38ab4592137ebda8f7e409b86,96d78bd991592fa6b052bae1f407a55b0bf1d044..7303f278e80154ede039cf1056244883f2c94912
--- 1/src/mem/physical.cc
--- 2/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@@ -113,10 -195,12 +195,12 @@@ PhysicalMemory::checkLockedAddrList(Req
  void
  PhysicalMemory::doFunctionalAccess(Packet *pkt)
  {
 -    assert(pkt->getAddr() + pkt->getSize() < params()->addrRange.size());
 +    assert(pkt->getAddr() + pkt->getSize() <= params()->addrRange.size());
  
-     switch (pkt->cmd) {
-       case Packet::ReadReq:
+     if (pkt->isRead()) {
+         if (pkt->req->isLocked()) {
+             trackLoadLocked(pkt->req);
+         }
          memcpy(pkt->getPtr<uint8_t>(),
                 pmemAddr + pkt->getAddr() - params()->addrRange.start,
                 pkt->getSize());

diff --cc tests/configs/o3-timing-mp.py
index 09935d574ae8873ecd594acbdb9358a68db0eb1e,55af8be0dfe9511e16140baee7af471338d8c862..68631b3d251d816fbd0c5dd17b662eed491ce219
--- 1/tests/configs/o3-timing-mp.py
--- 2/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@@ -53,7 -54,7 +53,7 @@@ class L2(BaseCache)
      write_buffers = 8
  
  nb_cores = 4
- cpus = [ DerivO3CPU() for i in xrange(nb_cores) ]
 -cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
++cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
  
  # system simulated
  system = System(cpu = cpus, physmem = PhysicalMemory(), membus =