use cachesize reported in wishbone2lasmi

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index 0db10b2e9b3cd96ec020f697e60011b3a5d09d9e..28ae0b411bf2e592347bc5fe9824742c2f267b95 100644 (file)
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
@@ -34,12 +34,11 @@ class GenSoC(Module):
                "sram":         0x10000000, # (shadow @0x90000000)
                "csr":          0x60000000, # (shadow @0xe0000000)
        }
-       def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_size=0, with_uart=True, cpu_type="lm32",
+       def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, with_uart=True, cpu_type="lm32",
                                csr_data_width=8, csr_address_width=14):
                self.clk_freq = clk_freq
                self.cpu_reset_address = cpu_reset_address
                self.sram_size = sram_size
-               self.l2_size = l2_size
                self.cpu_type = cpu_type
                self.csr_data_width = csr_data_width
                self.csr_address_width = csr_address_width
@@ -71,8 +70,7 @@ class GenSoC(Module):
                if with_uart:
                        self.submodules.uart = uart.UART(platform.request("serial"), clk_freq, baud=115200)
                platform_id = 0x554E if not hasattr(platform, "identifier") else platform.identifier
-               self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq),
-                       log2_int(l2_size) if l2_size else 0)
+               self.submodules.identifier = identifier.Identifier(platform_id, int(clk_freq))
                self.submodules.timer0 = timer.Timer()
 
        def register_rom(self, rom_wb_if, bios_size=0xa000):
@@ -155,8 +153,9 @@ class SDRAMSoC(GenSoC):
        csr_map = {
                "dfii":                                 6,
                "lasmicon":                             7,
-               "memtest_w":                    8,
-               "memtest_r":                    9
+               "wishbone2lasmi":               8,
+               "memtest_w":                    9,
+               "memtest_r":                    10
        }
        csr_map.update(GenSoC.csr_map)
 
@@ -166,7 +165,8 @@ class SDRAMSoC(GenSoC):
        mem_map.update(GenSoC.mem_map)
 
        def __init__(self, platform, clk_freq, cpu_reset_address, with_memtest=False, sram_size=4096, l2_size=8192, with_uart=True, ramcon_type="lasmicon", **kwargs):
-               GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size, with_uart, **kwargs)
+               GenSoC.__init__(self, platform, clk_freq, cpu_reset_address, sram_size, with_uart, **kwargs)
+               self.l2_size = l2_size
                self.with_memtest = with_memtest
                self.ramcon_type = ramcon_type
                self._sdram_phy_registered = False

diff --git a/misoclib/identifier/__init__.py b/misoclib/identifier/__init__.py
index e736d3aea66d95d8fd628d8a3499bd9852525212..dd018fe69cc17588bae6d680eab0d323bb7493f2 100644 (file)
--- a/misoclib/identifier/__init__.py
+++ b/misoclib/identifier/__init__.py
@@ -4,11 +4,10 @@ from migen.bank.description import *
 from misoclib.identifier import git
 
 class Identifier(Module, AutoCSR):
-       def __init__(self, sysid, frequency, l2_size, revision=None):
+       def __init__(self, sysid, frequency, revision=None):
                self._sysid = CSRStatus(16)
                self._revision = CSRStatus(32)
                self._frequency = CSRStatus(32)
-               self._l2_size = CSRStatus(8)
 
                ###
 
@@ -18,6 +17,5 @@ class Identifier(Module, AutoCSR):
                self.comb += [
                        self._sysid.status.eq(sysid),
                        self._revision.status.eq(revision),
-                       self._frequency.status.eq(frequency),
-                       self._l2_size.status.eq(l2_size)
+                       self._frequency.status.eq(frequency)
                ]

diff --git a/software/libbase/system.c b/software/libbase/system.c
index 2f65aeb1da0157e8a48a2bd90be807773c76c1e8..ea4c7617f357735a7a047167f9347934d8e433e4 100644 (file)
--- a/software/libbase/system.c
+++ b/software/libbase/system.c
@@ -67,6 +67,7 @@ void flush_cpu_dcache(void)
 #endif
 }
 
+#ifdef WISHBONE2LASMI_BASE
 void flush_l2_cache(void)
 {
        unsigned int l2_nwords;
@@ -74,7 +75,7 @@ void flush_l2_cache(void)
        register unsigned int addr;
        register unsigned int dummy;
 
-       l2_nwords = 1 << (identifier_l2_size_read() - 2);
+       l2_nwords = 1 << wishbone2lasmi_cachesize_read();
        for(i=0;i<2*l2_nwords;i++) {
                addr = SDRAM_BASE + i*4;
 #ifdef __lm32__
@@ -84,3 +85,4 @@ void flush_l2_cache(void)
 #endif
        }
 }
+#endif