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nv50/ir/opt: check BB equality before instruction ordering in CSE
authorChristoph Bumiller <e0425955@student.tuwien.ac.at>
Thu, 22 Mar 2012 10:58:31 +0000 (11:58 +0100)
committerChristoph Bumiller <e0425955@student.tuwien.ac.at>
Sat, 14 Apr 2012 19:54:02 +0000 (21:54 +0200)
src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp patch | blob | history

diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp
index 35ddca34b194d946eb0f18a7122b03af9c67e8b8..259bb5636c5e9faaf371f3dc06081c82fe4f0793 100644 (file)
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_peephole.cpp
@@ -2096,7 +2096,7 @@ LocalCSE::visit(BasicBlock *bb)
             for (Value::UseIterator it = src->uses.begin();
                  it != src->uses.end(); ++it) {
                Instruction *ik = (*it)->getInsn();
-               if (ik && ik->serial < ir->serial && ik->bb == ir->bb)
+               if (ik && ik->bb == ir->bb && ik->serial < ir->serial)
                   if (tryReplace(&ir, ik))
                      break;
             }